Video PLL

The video PLL circuit is only present in home consoles, it was added as a way to improve composite video quality by adjusting the main clock frequency with the color burst frequency.

=Operation=



is generated by from the main clock: Square, 24167829Hz / 384 / 16 = 3933Hz (16 lines)

is generated by LSPC2 from (color burst frequency, NTSC 3579545Hz): Not square, DIVO is counter's 10th bit (512 DIVI periods low) and reset at 912 (398 DIVI periods high ?) = 3933Hz also.

DIVO and REF are compared to generate to adjustment voltage for the varicap diode to make sure 24M = DIVI / 910 * 16 * 384 ?

also feeds the video encoder.

=First generation=



It was added during the production of first generation AES consoles as a correction board wired to different locations on the main board.

The divider was made using 74LS161 4-bit counters.

Board's reference is PL241S ?

=Second generation=



When SNK made the second generation chipset, the bodge became part of the system with the inclusion of the divider logic in.