68k instructions timings

TODO: CSS template for cputiming is ugly and broken.

Mirroring information from http://oldwww.nvg.ntnu.no/amiga/MC680x0_Sections/mc68000timing.HTML

The number of bus read and write cycles is shown in parenthesis as (r/w).

In the following tables the headings have the following meanings:
 * An : Address register operand
 * Dn : Data register operand
 * ea : Operand specified by an effective address
 * M : Memory effective address operand

To get the execution time, multiply the cycles count by 83.33ns (1/12MHz).

A VBlank interrupt lasts exactly 40 lines * 384 pixels * 2 = 30720 cycles (2.56ms).

=Effective address operand calculation=

This table lists the number of clock periods required to compute an instruction's effective address. It includes fetching of any extension words, the address computation, and fetching of the memory operand.

Notes:
 * Pre-dec is slower than post-inc
 * There are no write cycles involved in processing the effective address
 * The size of the index register (ix) does not affect execution time

=Move instructions=

These following two tables indicate the number of clock periods for the move instruction. This data includes instruction fetch, operand reads, and operand writes.

Byte and word
The size of the index register (ix) does not affect execution time.

Long
The size of the index register (ix) does not affect execution time.

=Standard instructions=

=Immediate instructions=

=Single operand instructions=

=Shift and rotate instructions=

=Bit manipulation instructions=

=Conditional instructions=

=JMP, JSR, LEA, PEA and MOVEM instructions=

=Multi-precision instructions=

=Miscellaneous instructions=

=Move Peripheral instructions=

=Exception processing=