MV2F

Revised 2 slot board with the second generation chipset.

Pinouts
todo: formatting, maybe pics

C ROM / LSPC2 / NEO-ZMC2
todo. Pair of NEO-257 on far left of board used for this? 32 bits per slot multiplexed to NEO-ZMC2?

S ROM / LSPC2 / NEO-B1
FIXD0~FIXD7 is multiplexed from each from by NEO-257 @ J9. Same one is used for Z80 D0~D7 for cart M1 access.

Selected FIX data is output to NEO-B1 from Y0~Y7.

The 257 seems to have common enable/select lines. See M ROM section for those as cart M ROM/S ROM are always enabled together.

ADPCM-A
YM2610 RAD0~RAD7 goes through NEO-G0 @ K9 and out to each cart slot through a separate set of pins. (NEO-G0 needs a proper set of pin names).

Control signals and other address lines buffered through NEO-E0 to both cart slots @ F8.

Direction control of NEO-G0 (D0~D7) @ K9 is set to inverted /ROE from YM2610.

ADPCM-B
YM2610 PAD0~PAD7 goes through NEO-G0 @ K9 and out to each cart slot through a separate set of pins.

Control signals and other address lines buffered through NEO-E0 to both cart slots @ F8.

Direction control of NEO-G0 (D8~D15) @ K9 is set to inverted /POE from YM2610.

P ROM / 68k access
todo. some NEO-G0 for D0~D15? NEO-E0 for A1~A23?

M ROM / Z80 access
Z80 A0~A15 is buffered through NEO-E0 @ K10 to SDA0~SDA15 of both cart slots.

Z80 D0~D7 is multiplexed from each slot by NEO-257 @ J9. No need for bidirectional D0~D7 since only reads can be done from cart.

Multiplexer slot selection from NEO-F0, /OE from NEO-D0 and OE from 74HC259 to NEO-257. The 257 must only output to Z80 when it is trying to read ROM (NEO-D0) and the cart M1/S1 is selected (74HC259).

NEO-D0 signals for Z80 reads are also buffered through NEO-E0 @ K10.