Display timing

(Need trad)

Upper 9 bits of register REG_HBLANKCNT ($3C0006):
 * $00F8-$00FF : Vertical sync (8)
 * $0100-$010F : Top border (16)
 * $0110-$01EF : Active display (224)
 * $01F0-$01FF : Bottom border (16)

From mvstech.txt (by Charles MacDonald): Measured in reference to main 24 MHz clock (mclk):

Horizontal timing

Pulse widths: 111 mclks horizontal sync                   27.75 pixels 256 mclks horizontal blanking                  64 pixels 1280 mclks active display                      320 pixels 1536 mclks per scanline                        384 pixels

State to state timing: 118 mclks /HSYNC rising to /HBLANK rising    29.5 pixels (left border) 1280 mclks /HBLANK rising to /HBLANK falling   320 pixels (display) 27 mclks /HBLANK falling to /HSYNC falling  6.75 pixels (right border) 111 mclks /HSYNC falling to /HSYNC rising   27.75 pixels (horizontal sync)

384 pixels per scanline: (rounding up)

28 pixels horizontal sync pulse width 29 pixels /HSYNC low to /HBLANK high 320 pixels /HBLANK high to /HBLANK low 7 pixels /HBLANK low to /HSYNC low

Vertical timing

264 scanlines per frame:

8 scanlines vertical sync pulse 16 scanlines top border 224 scanlines active display 16 scanlines bottom border

Frame timing

Frame rate is 6 MHz / 384 / 264 = 59.18 Hz.