68k interrupts

There are 3 interrupt levels on the AES and MVS, and 4 on the CD hardware.

Interrupts need to be acknowledged by writing to register.
 * bit 2: Acknowledge vblank interrupt
 * bit 1: Acknowledge timer interrupt
 * bit 0: Acknowledge cold start interrupt

Multiple bits can be set:

Bits 8~10 of the SR register can be used to mask them.

=Vertical blank interrupt=

The vblank interrupt is almost always used. It occurs when the rendering of a frame finishes (~60 times per second). See display timing.

=Timer interrupt=

The timer interrupt's behavior can be programmed through the GPU's memory mapped registers. It is triggered by a 32-bit down counter clocked by the 6MHz pixel clock, and a corresponding reset register. When the counter reaches 0, an interrupt is generated. Intervals can range from 166.7ns (dangerous interrupt flood) to 11.9 minutes (?).

It can be used for special video effects such as scanline effects, for example:
 * The interlaced Sammy logo in Viewpoint
 * Sengoku 2's intro
 * The road in Riding hero
 * Neo Turf Masters's ground perspective

=AES/MVS interrupt levels=


 * Vblank: Level 0
 * Timer: Level 1
 * Pending after cold reset: Level 2

=CD interrupt levels=


 * VBlank: Level 1 !
 * Timer: Level 0 !
 * CDC interrupt: Level 3 !

Level 2 isn't used ?