Signals


 * 6M, 12M, 24M: 6MHz, 12MHz, and 24MHz clock signals
 * 2H1: S ROM A3
 * 4MB: 4MHz inverted
 * A1~A23: 68k address bus
 * A22I,A23I: A22 and A23 modified for 68k vector table swap
 * AS: 68k Address Strobe
 * CA4: C ROM A4
 * CR0~CR31: C ROMs data bus (2*16bits), holds data for one 8 pixels line
 * D0~D15: 68k data bus
 * /DTACK: 68k Data Transmit ACKnowledge
 * FIXD0~FIXD7: S ROM data bus
 * P0~P23: C ROM, S ROM and LO ROM address/data bus (multiplexed)
 * PCK1B: Clock to latch C ROM address from P0~P23 (mapping) on rising edge
 * PCK2B: Clock to latch S ROM address from P0~P15 (mapping) on rising edge
 * /PORTADRS: $200000-$2FFFFF (P2+ ROM/Security chip) any access
 * /PORTOEL: $200000-$2FFFFF (P2+ ROM/Security chip) odd byte read
 * /PORTOEU: $200000-$2FFFFF (P2+ ROM/Security chip) even byte read
 * /PORTWEL: $200000-$2FFFFF (P2+ ROM/Security chip) odd byte write
 * /PORTWEU: $200000-$2FFFFF (P2+ ROM/Security chip) even byte write
 * /PWAIT0, /PWAIT1: adds 0 to 3 cycle delay for P2 ROM reads
 * R/W: 68k Read/Write
 * /ROMOE: $000000-$0FFFFF (P1 ROM) read
 * /ROMOEL: $000000-$0FFFFF (P1 ROM) odd byte read
 * /ROMOEU: $000000-$0FFFFF (P1 ROM) even byte read
 * /ROMWAIT: add 1-cycle delay for P1 ROM reads
 * /SROMOE: $C00000-$CFFFFF (BIOS) read
 * /SROMOEL: $C00000-$CFFFFF (BIOS) odd byte read
 * /SROMOEU: $C00000-$CFFFFF (BIOS) even byte read
 * SDA0~SDA15 : Z80 address bus
 * SDD0~SDD7: Z80 data bus
 * SDRAD0~SDRAD7: ADPCM-A ROM multiplexed bus (data/address)
 * SDRA8,SDRA9,SDRA20~SDRA23: ADPCM-A ROM address bus
 * SDPAD0~SDPAD7: ADPCM-B ROM multiplexed bus (data/address)
 * SDPA8,SDPA9,SDPA10,SDPA11: ADPCM-B ROM address bus
 * SYSTEM: low when onboard ROMs selected
 * SYSTEMB: inverted SYSTEM
 * PA0~PA11: Palette RAM address bus