NEO-B1



The NEO-B1 chip is found in second revision cartridge-based systems.

Graphics
Both FIX graphics from the S ROM and sprite graphics from the C ROM are fed to the NEO-B1 for display on screen. Sprite graphics are sourced from the C ROM multiplexer (NEO-ZMC2, PRO-CT0 or NEO-CMC), while FIX graphics are sourced directly from the currently enabled FIX ROM.

The palette RAM address lines are directly connected to the NEO-B1 for pixel output. The data output of the palette RAM is latched by a pair of 8bit registers, which in turn output to the video DAC. The NEO-B1 arbitrates access to palette RAM and will pass the 68k address through to the palette RAM when reading/writing/testing the palette RAM. Priority is always given to the 68k which results in harmless display glitches when games access palette RAM while rendering the screen.

Watchdog
The watchdog is integrated into the NEO-B1. /HALT and /RESET are generated by this chip on power-on and whenever the 68k fails to write the watchdog register in time. It seems to decode the write to watchdog itself instead of using the NEO-C1.

Pinout
(Max size:File:neo-b1_pinout.png)


 * A1~A21: 68k address bus
 * A22I,A23I: 68k A22,A23 passed through NEO-E0
 * FIX0~FIX7: FIX ROM data bus
 * PCK1/PCK2: Latch signals, shared with LSPC2-A2 (inverted for NEO-273)
 * PA0~PA11: Palette RAM address bus
 * TDO0~TDO11: NC on the MV1F
 * GAD0~GAD3: Pixel data (?) from NEO-ZMC2
 * TDI0~TDI3: Pixel data (?) from NEO-ZMC2
 * TA0~TA7,P8~P15,TDI4~TDI11: Shared "P*" 24bit bus with LSPC2-A2
 * FLIP: Horizontal flip pixel line ?
 * WE1~WE4,CK1~CK4,SS1/SS2: Shared with LSPC2-A2
 * TMS0,TMS1: Watchdog clock ?