NeoGeo Development Wiki - User contributions [en]

Backup RAM

2025-05-24T15:42:09Z

Hpman:

The backup RAM is a [[battery-backed_RAM|battery-powered]] 64KiB RAM space used by the [[MVS]] to store game scores, cab infos and income logs. Access can be handled by [[BIOS calls]].

[[68k memory map|Memory region]]: $D00000~$D0FFFF (Mirrored up to $DFFFFF ?).

== Data structure ==

All offset are taken from the sp-s2.bin system ROM.

{| class="regdef"
| '''Start'''
| '''End'''
| '''Size'''
| '''Data'''
| '''Description'''
|-
|$D00000
|$D0000F
|16
|$00
|Unused, fill with $00
|-
|$D00010
|$D0001F
|16
|"BACKUP RAM OK!Ç"
|The routine at $C125C8 will check if this string is present, if not it will test the ram (using the test_ram routine at $C13134) and re-init the backupram
|-
|$D00020
|$D00021
|2
|
|Coin deposit related (rising edge finding), old and new value of REG_STATUS_A
|-
|$D00022
|$D00023
|2
|
|Temp value for the coin deposit rising edge finding
|-
|$D00024
|$D00025
|2
|
|Internal coin counter (not credit)
|-
|'''$D00026'''
|'''$D0002F'''
|
|
|?
|-
|$D00034
|$D00035
|2
|$00
|"Internal" credit counters for player 1 and player 2 (BCD)
|-
|'''$D00036'''
|'''$D00039'''
|
|
|?
|-
|$D0003A
|$D00045
|12
|
|Cab settings.
;$D0003A: Coins needed for crediting player 1 (initialized to $01)
;$D0003B: Credits added to player 1 (initialized to $01)
;$D0003C: Coins needed for crediting player 2 (initialized to $01)
;$D0003D: Credits added to player 2 (initialized to $02)
;$D00042: Game select (1=Free, 0=Only when credited) (initialized to 0)
;$D00043: Game start compulsion (0 = enabled, 1 = disabled)
;$D00044: Game start compulsion time (max time in seconds in BCD between inserting a coin and starting the game) (initialized to $30)
;$D00046: Demo sound (1=Without) (initialized to 0)
|-
|$D00046
|$D00046
|1
|SOUND_STOP
|No sound at all if non-zero (except coinage sound effect)
|-
|$D00047
|$D00047
|1
|SLOT NUMBER
|Number of detected slots (2 for slot1)
|-
|$D00048
|$D0004B
|4
|PLAY TIME
|Counter of second played on the game in hex.

Reset to 0 by [[SYSTEM_RETURN]].
|-
|$D0004C
|$D0004C
|1
|PLAY_TIME_FRAME_TIMER
|Frame timer, start at $3C, decremented each frame. When the counter reach $00, PLAY_TIME is incremented and the counter is reseted to $3C
|-
|'''$D0004D'''
|'''$D00057'''
|
|
|?
|-
|$D00058
|$D00058
|1
|
|First slot number with a boot logo flag to 0 (playable by the system ROM)
|-
|$D0005A
|$D0005D
|4
|HHMMSSFF
|Timer based on frames.
*FF: frame down-counter ($3C to $00)
*SS: second counter ($00 to $3B)
*MM: minute counter ($00 to $3B)
*HH: hour counter *4 ($00 to $60 by 4 steps)
|-
|$D0005E
|$D00103
|
|
|?
|-
|$D00104
|$D00107
|4
|YYMMDDdd
|Current date
|-
|$D00108
|$D00108
|1
|Selected slot number (start at 0)
|Output directly to the EL panels
|-
|'''$D00109'''
|'''$D00109'''
|1
|EL_PANEL
|State of the EL-PANEL ???
|-
|$D0010A
|$D0010D
|4
|
|Detailed game start book address
|-
|$D0010E
|$D00111
|4
|
|Total game start book address
|-
|$D00112
|$D00115
|4
|
|Detailed cabinet coin book address (add 0x240 for the start book one)
|-
|$D00116
|$D00119
|4
|
|Current month cabinet coin book address (add 0xC0 for the start book one)
|-
|'''$D0011A'''
|'''$D00121'''
|
|
|?
|-
|$D00122
|$D00122
|1
|Changes daily
|Slot index ($0 to $23) for book keeping data.

Updated each time system is turned on on a new day
|-
|$D00124
|$D00127
|4
|Slot-1 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID
|-
|$D00128
|$D0012B
|4
|Slot-2 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID.
On a slot1 always unset (slot1 are slot2 with the second one empty)
|-
|$D0012C
|$D0012F
|4
|Slot-3 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID
|-
|$D00130
|$D00133
|4
|Slot-4 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID
|-
|$D00134
|$D00137
|4
|Slot-5 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID
|-
|$D00138
|$D0013B
|4
|Slot-6 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID
|-
|$D0013C
|$D0013F
|4
|Slot-7 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID
|-
|$D00140
|$D00143
|4
|Slot-8 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID
|-
|$D00144
|$D00147
|4
|YYMMDDdd
|Slot-1 book creation time YEAR-MONTH-DAY-day number
|-
|$D00148
|$D0014B
|4
|YYMMDDdd
|Slot-2 book creation time YEAR-MONTH-DAY-day number
|-
|$D0014C
|$D0014F
|4
|YYMMDDdd
|Slot-3 book creation time YEAR-MONTH-DAY-day number
|-
|$D00150
|$D00153
|4
|YYMMDDdd
|Slot-4 book creation time YEAR-MONTH-DAY-day number
|-
|$D00154
|$D00157
|4
|YYMMDDdd
|Slot-5 book creation time YEAR-MONTH-DAY-day number
|-
|$D00158
|$D0015B
|4
|YYMMDDdd
|Slot-6 book creation time YEAR-MONTH-DAY-day number
|-
|$D0015C
|$D0015F
|4
|YYMMDDdd
|Slot-7 book creation time YEAR-MONTH-DAY-day number
|-
|$D00160
|$D00163
|4
|YYMMDDdd
|Slot-8 book creation time YEAR-MONTH-DAY-day number
|-
|'''$D00164'''
|'''$D001A3'''
|
|
|?
|-
|$D001A4
|$D001A7
|4
|
|Current month game start book
|-
|'''$D001A8'''
|'''$D0021F'''
|
|
|?
|-
|$D00220
|$D0029F
|16*8
|
|Games soft DIPs settings (in which order ?)
|-
|$D002A0
|$D002AF
|16
|
|bram block 0 game name
|-
|$D002B0
|$D002BF
|16
|
|bram block 1 game name
|-
|$D002C0
|$D002CF
|16
|
|bram block 2 game name
|-
|$D002D0
|$D002DF
|16
|
|bram block 3 game name
|-
|$D002E0
|$D002EF
|16
|
|bram block 4 game name
|-
|$D002F0
|$D002FF
|16
|
|bram block 5 game name
|-
|$D00300
|$D0030F
|16
|
|bram block 6 game name
|-
|$D00310
|$D0031F
|16
|
|bram block 7 game name
|-
|$D00320
|$D0131F
|$1000
|
|bram block 1 data
|-
|$D01320
|$D0231F
|$1000
|
|bram block 2 data
|-
|$D02320
|$D0331F
|$1000
|
|bram block 3 data
|-
|$D03320
|$D0431F
|$1000
|
|bram block 4 data
|-
|$D04320
|$D0531F
|$1000
|
|bram block 5 data
|-
|$D05320
|$D0631F
|$1000
|
|bram block 6 data
|-
|$D06320
|$D0731F
|$1000
|
|bram block 7 data
|-
|$D07320
|$D0831F
|$1000
|
|bram block 8 data
|-
|$D08320
|$D0951F
|$1200
|YYMMDDdd - PLAY - CONTINUE - TIME
|Bookkeeping - Daily game play data (8 slots of $24 * $10 entries)
|-
|$D09520
|$D09B1F
|$600
|YYMMDDdd - PLAY - CONTINUE - TIME
|Bookkeeping - Monthly game play data (8 slots of 12 * $10 entries)
|-
|$D09B20
|$D09B9F
|$80
|YYMMDDdd - PLAY - CONTINUE - TIME
|Bookkeeping - Total game play data (8 slots $10 entries)
|-
|$D09BA0
|$D09DDF
|$240
|YYMMDDdd - COIN1 - COIN2 - SERVICE
|Bookkeeping - Daily cab coin data

Each entry is $10 byte long
|-
|$D09DE0
|$D0A01F
|$240
|YYMMDDdd - PLAY - CONTINUE - TIME
|Bookkeeping - Daily cab play data

Each entry is $10 byte long
|-
|$D0A020
|$D0A0DF
|$C0
|00000000 - COIN1 - COIN2 - SERVICE
|Bookkeeping - Monthly cab coin data ($10 bytes entries * 12)
|-
|$D0A0E0
|$D0A19F
|$C0
|00000000 - PLAY - CONTINUE - TIME
|Bookkeeping - Monthly cab play data ($10 bytes entries * 12)
|}

[[Category:Cartridge systems]]

Backup RAM

2025-05-24T15:39:04Z

Hpman: Bookkeeping info

The backup RAM is a [[battery-backed_RAM|battery-powered]] 64KiB RAM space used by the [[MVS]] to store game scores, cab infos and income logs. Access can be handled by [[BIOS calls]].

[[68k memory map|Memory region]]: $D00000~$D0FFFF (Mirrored up to $DFFFFF ?).

== Data structure ==

All offset are taken from the sp-s2.bin system ROM.

{| class="regdef"
| '''Start'''
| '''End'''
| '''Size'''
| '''Data'''
| '''Description'''
|-
|$D00000
|$D0000F
|16
|$00
|Unused, fill with $00
|-
|$D00010
|$D0001F
|16
|"BACKUP RAM OK!Ç"
|The routine at $C125C8 will check if this string is present, if not it will test the ram (using the test_ram routine at $C13134) and re-init the backupram
|-
|$D00020
|$D00021
|2
|
|Coin deposit related (rising edge finding), old and new value of REG_STATUS_A
|-
|$D00022
|$D00023
|2
|
|Temp value for the coin deposit rising edge finding
|-
|$D00024
|$D00025
|2
|
|Internal coin counter (not credit)
|-
|'''$D00026'''
|'''$D0002F'''
|
|
|?
|-
|$D00034
|$D00035
|2
|$00
|"Internal" credit counters for player 1 and player 2 (BCD)
|-
|'''$D00036'''
|'''$D00039'''
|
|
|?
|-
|$D0003A
|$D00045
|12
|
|Cab settings.
;$D0003A: Coins needed for crediting player 1 (initialized to $01)
;$D0003B: Credits added to player 1 (initialized to $01)
;$D0003C: Coins needed for crediting player 2 (initialized to $01)
;$D0003D: Credits added to player 2 (initialized to $02)
;$D00042: Game select (1=Free, 0=Only when credited) (initialized to 0)
;$D00043: Game start compulsion (0 = enabled, 1 = disabled)
;$D00044: Game start compulsion time (max time in seconds in BCD between inserting a coin and starting the game) (initialized to $30)
;$D00046: Demo sound (1=Without) (initialized to 0)
|-
|$D00046
|$D00046
|1
|SOUND_STOP
|No sound at all if non-zero (except coinage sound effect)
|-
|$D00047
|$D00047
|1
|SLOT NUMBER
|Number of detected slots (2 for slot1)
|-
|$D00048
|$D0004B
|4
|PLAY TIME
|Counter of second played on the game in hex.

Reset to 0 by [[SYSTEM_RETURN]].
|-
|$D0004C
|$D0004C
|1
|PLAY_TIME_FRAME_TIMER
|Frame timer, start at $3C, decremented each frame. When the counter reach $00, PLAY_TIME is incremented and the counter is reseted to $3C
|-
|'''$D0004D'''
|'''$D00057'''
|
|
|?
|-
|$D00058
|$D00058
|1
|
|First slot number with a boot logo flag to 0 (playable by the system ROM)
|-
|$D0005A
|$D0005D
|4
|HHMMSSFF
|Timer based on frames.
*FF: frame down-counter ($3C to $00)
*SS: second counter ($00 to $3B)
*MM: minute counter ($00 to $3B)
*HH: hour counter *4 ($00 to $60 by 4 steps)
|-
|$D0005E
|$D00103
|
|
|?
|-
|$D00104
|$D00107
|4
|YYMMDDdd
|Current date
|-
|$D00108
|$D00108
|1
|Selected slot number (start at 0)
|Output directly to the EL panels
|-
|'''$D00109'''
|'''$D00109'''
|1
|EL_PANEL
|State of the EL-PANEL ???
|-
|$D0010A
|$D0010D
|4
|
|Detailed game start book address
|-
|$D0010E
|$D00111
|4
|
|Total game start book address
|-
|$D00112
|$D00115
|4
|
|Detailed cabinet coin book address (add 0x240 for the start book one)
|-
|$D00116
|$D00119
|4
|
|Current month cabinet coin book address (add 0xC0 for the start book one)
|-
|'''$D0011A'''
|'''$D00121'''
|
|
|?
|-
|$D00122
|$D00122
|1
|Changes daily
|Slot index for book keeping data.

Updated each time system is turned on on a new day
|-
|$D00124
|$D00127
|4
|Slot-1 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID
|-
|$D00128
|$D0012B
|4
|Slot-2 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID.
On a slot1 always unset (slot1 are slot2 with the second one empty)
|-
|$D0012C
|$D0012F
|4
|Slot-3 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID
|-
|$D00130
|$D00133
|4
|Slot-4 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID
|-
|$D00134
|$D00137
|4
|Slot-5 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID
|-
|$D00138
|$D0013B
|4
|Slot-6 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID
|-
|$D0013C
|$D0013F
|4
|Slot-7 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID
|-
|$D00140
|$D00143
|4
|Slot-8 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID
|-
|$D00144
|$D00147
|4
|YYMMDDdd
|Slot-1 book creation time YEAR-MONTH-DAY-day number
|-
|$D00148
|$D0014B
|4
|YYMMDDdd
|Slot-2 book creation time YEAR-MONTH-DAY-day number
|-
|$D0014C
|$D0014F
|4
|YYMMDDdd
|Slot-3 book creation time YEAR-MONTH-DAY-day number
|-
|$D00150
|$D00153
|4
|YYMMDDdd
|Slot-4 book creation time YEAR-MONTH-DAY-day number
|-
|$D00154
|$D00157
|4
|YYMMDDdd
|Slot-5 book creation time YEAR-MONTH-DAY-day number
|-
|$D00158
|$D0015B
|4
|YYMMDDdd
|Slot-6 book creation time YEAR-MONTH-DAY-day number
|-
|$D0015C
|$D0015F
|4
|YYMMDDdd
|Slot-7 book creation time YEAR-MONTH-DAY-day number
|-
|$D00160
|$D00163
|4
|YYMMDDdd
|Slot-8 book creation time YEAR-MONTH-DAY-day number
|-
|'''$D00164'''
|'''$D001A3'''
|
|
|?
|-
|$D001A4
|$D001A7
|4
|
|Current month game start book
|-
|'''$D001A8'''
|'''$D0021F'''
|
|
|?
|-
|$D00220
|$D0029F
|16*8
|
|Games soft DIPs settings (in which order ?)
|-
|$D002A0
|$D002AF
|16
|
|bram block 0 game name
|-
|$D002B0
|$D002BF
|16
|
|bram block 1 game name
|-
|$D002C0
|$D002CF
|16
|
|bram block 2 game name
|-
|$D002D0
|$D002DF
|16
|
|bram block 3 game name
|-
|$D002E0
|$D002EF
|16
|
|bram block 4 game name
|-
|$D002F0
|$D002FF
|16
|
|bram block 5 game name
|-
|$D00300
|$D0030F
|16
|
|bram block 6 game name
|-
|$D00310
|$D0031F
|16
|
|bram block 7 game name
|-
|$D00320
|$D0131F
|$1000
|
|bram block 1 data
|-
|$D01320
|$D0231F
|$1000
|
|bram block 2 data
|-
|$D02320
|$D0331F
|$1000
|
|bram block 3 data
|-
|$D03320
|$D0431F
|$1000
|
|bram block 4 data
|-
|$D04320
|$D0531F
|$1000
|
|bram block 5 data
|-
|$D05320
|$D0631F
|$1000
|
|bram block 6 data
|-
|$D06320
|$D0731F
|$1000
|
|bram block 7 data
|-
|$D07320
|$D0831F
|$1000
|
|bram block 8 data
|-
|$D08320
|$D0951F
|$1200
|YYMMDDdd - PLAY - CONTINUE - TIME
|Bookkeeping - Daily game play data (8 slots of $24 * $10 entries)
|-
|$D09520
|$D09B1F
|$600
|YYMMDDdd - PLAY - CONTINUE - TIME
|Bookkeeping - Monthly game play data (8 slots of 12 * $10 entries)
|-
|$D09B20
|$D09B9F
|$80
|YYMMDDdd - PLAY - CONTINUE - TIME
|Bookkeeping - Total game play data (8 slots $10 entries)
|-
|$D09BA0
|$D09DDF
|$240
|YYMMDDdd - COIN1 - COIN2 - SERVICE
|Bookkeeping - Daily cab coin data

Each entry is $10 byte long
|-
|$D09DE0
|$D0A01F
|$240
|YYMMDDdd - PLAY - CONTINUE - TIME
|Bookkeeping - Daily cab play data

Each entry is $10 byte long
|-
|$D0A020
|$D0A0DF
|$C0
|00000000 - COIN1 - COIN2 - SERVICE
|Bookkeeping - Monthly cab coin data ($10 bytes entries * 12)
|-
|$D0A0E0
|$D0A19F
|$C0
|00000000 - PLAY - CONTINUE - TIME
|Bookkeeping - Monthly cab play data ($10 bytes entries * 12)
|}

[[Category:Cartridge systems]]

Backup RAM

2025-05-14T16:06:05Z

Hpman:

The backup RAM is a [[battery-backed_RAM|battery-powered]] 64KiB RAM space used by the [[MVS]] to store game scores, cab infos and income logs. Access can be handled by [[BIOS calls]].

[[68k memory map|Memory region]]: $D00000~$D0FFFF (Mirrored up to $DFFFFF ?).

== Data structure ==

All offset are taken from the sp-s2.bin system ROM.

{| class="regdef"
| '''Start'''
| '''End'''
| '''Size'''
| '''Data'''
| '''Description'''
|-
|$D00000
|$D0000F
|16
|$00
|Unused, fill with $00
|-
|$D00010
|$D0001F
|16
|"BACKUP RAM OK!Ç"
|The routine at $C125C8 will check if this string is present, if not it will test the ram (using the test_ram routine at $C13134) and re-init the backupram
|-
|$D00020
|$D00021
|2
|
|Coin deposit related (rising edge finding), old and new value of REG_STATUS_A
|-
|$D00022
|$D00023
|2
|
|Temp value for the coin deposit rising edge finding
|-
|$D00024
|$D00025
|2
|
|Internal coin counter (not credit)
|-
|'''$D00026'''
|'''$D0002F'''
|
|
|?
|-
|$D00034
|$D00035
|2
|$00
|"Internal" credit counters for player 1 and player 2 (BCD)
|-
|'''$D00036'''
|'''$D00039'''
|
|
|?
|-
|$D0003A
|$D00045
|12
|
|Cab settings.
;$D0003A: Coins needed for crediting player 1 (initialized to $01)
;$D0003B: Credits added to player 1 (initialized to $01)
;$D0003C: Coins needed for crediting player 2 (initialized to $01)
;$D0003D: Credits added to player 2 (initialized to $02)
;$D00042: Game select (1=Free, 0=Only when credited) (initialized to 0)
;$D00043: Game start compulsion (0 = enabled, 1 = disabled)
;$D00044: Game start compulsion time (max time in seconds in BCD between inserting a coin and starting the game) (initialized to $30)
;$D00046: Demo sound (1=Without) (initialized to 0)
|-
|$D00046
|$D00046
|1
|SOUND_STOP
|No sound at all if non-zero (except coinage sound effect)
|-
|$D00047
|$D00047
|1
|SLOT NUMBER
|Number of detected slots (2 for slot1)
|-
|$D00048
|$D0004B
|4
|PLAY TIME
|Counter of second played on the game in hex.

Reset to 0 by [[SYSTEM_RETURN]].
|-
|$D0004C
|$D0004C
|1
|PLAY_TIME_FRAME_TIMER
|Frame timer, start at $3C, decremented each frame. When the counter reach $00, PLAY_TIME is incremented and the counter is reseted to $3C
|-
|'''$D0004D'''
|'''$D00057'''
|
|
|?
|-
|$D00058
|$D00058
|1
|
|First slot number with a boot logo flag to 0 (playable by the system ROM)
|-
|$D0005A
|$D0005D
|4
|HHMMSSFF
|Timer based on frames.
*FF: frame down-counter ($3C to $00)
*SS: second counter ($00 to $3B)
*MM: minute counter ($00 to $3B)
*HH: hour counter *4 ($00 to $60 by 4 steps)
|-
|$D0005E
|$D00103
|
|
|?
|-
|$D00104
|$D00107
|4
|YYMMDDdd
|Current date
|-
|$D00108
|$D00108
|1
|Selected slot number (start at 0)
|Output directly to the EL panels
|-
|'''$D00109'''
|'''$D00109'''
|1
|EL_PANEL
|State of the EL-PANEL ???
|-
|$D0010A
|$D0010D
|4
|
|Detailed game start book address
|-
|$D0010E
|$D00111
|4
|
|Total game start book address
|-
|$D00112
|$D00115
|4
|
|Detailed cabinet coin book address (add 0x240 for the start book one)
|-
|$D00116
|$D00119
|4
|
|Current month cabinet coin book address (add 0xC0 for the start book one)
|-
|'''$D0011A'''
|'''$D00121'''
|
|
|?
|-
|$D00122
|$D00123
|2
|$23
|The init_backupram routine write $23 there, purpose unknown.
|-
|$D00124
|$D00127
|4
|Slot-1 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID
|-
|$D00128
|$D0012B
|4
|Slot-2 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID.
On a slot1 always unset (slot1 are slot2 with the second one empty)
|-
|$D0012C
|$D0012F
|4
|Slot-3 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID
|-
|$D00130
|$D00133
|4
|Slot-4 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID
|-
|$D00134
|$D00137
|4
|Slot-5 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID
|-
|$D00138
|$D0013B
|4
|Slot-6 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID
|-
|$D0013C
|$D0013F
|4
|Slot-7 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID
|-
|$D00140
|$D00143
|4
|Slot-8 [[NGH number]] and bram game block ID (see below)
|If not present $0000 as NGH and $FFFF as game name ID
|-
|$D00144
|$D00147
|4
|YYMMDDdd
|Slot-1 book creation time YEAR-MONTH-DAY-day number
|-
|$D00148
|$D0014B
|4
|YYMMDDdd
|Slot-2 book creation time YEAR-MONTH-DAY-day number
|-
|$D0014C
|$D0014F
|$4
|YYMMDDdd
|Slot-3 book creation time YEAR-MONTH-DAY-day number
|-
|$D00150
|$D00153
|4
|YYMMDDdd
|Slot-4 book creation time YEAR-MONTH-DAY-day number
|-
|$D00154
|$D00157
|4
|YYMMDDdd
|Slot-5 book creation time YEAR-MONTH-DAY-day number
|-
|$D00158
|$D0015B
|4
|YYMMDDdd
|Slot-6 book creation time YEAR-MONTH-DAY-day number
|-
|$D0015C
|$D0015F
|4
|YYMMDDdd
|Slot-7 book creation time YEAR-MONTH-DAY-day number
|-
|$D00160
|$D00163
|4
|YYMMDDdd
|Slot-8 book creation time YEAR-MONTH-DAY-day number
|-
|'''$D00164'''
|'''$D001A3'''
|
|
|?
|-
|$D001A4
|$D001A7
|4
|
|Current month game start book
|-
|'''$D001A8'''
|'''$D0021F'''
|
|
|?
|-
|$D00220
|$D0029F
|16*8
|
|Games soft DIPs settings (in which order ?)
|-
|$D002A0
|$D002AF
|16
|
|bram block 0 game name
|-
|$D002B0
|$D002BF
|16
|
|bram block 1 game name
|-
|$D002C0
|$D002CF
|16
|
|bram block 2 game name
|-
|$D002D0
|$D002DF
|16
|
|bram block 3 game name
|-
|$D002E0
|$D002EF
|16
|
|bram block 4 game name
|-
|$D002F0
|$D002FF
|16
|
|bram block 5 game name
|-
|$D00300
|$D0030F
|16
|
|bram block 6 game name
|-
|$D00310
|$D0031F
|16
|
|bram block 7 game name
|-
|$D00320
|$D0131F
|$1000
|
|bram block 1 data
|-
|$D01320
|$D0231F
|$1000
|
|bram block 2 data
|-
|$D02320
|$D0331F
|$1000
|
|bram block 3 data
|-
|$D03320
|$D0431F
|$1000
|
|bram block 4 data
|-
|$D04320
|$D0531F
|$1000
|
|bram block 5 data
|-
|$D05320
|$D0631F
|$1000
|
|bram block 6 data
|-
|$D06320
|$D0731F
|$1000
|
|bram block 7 data
|-
|$D07320
|$D0831F
|$1000
|
|bram block 8 data
|-
|$D09BA0
|$D09DE0
|$240
|YYMMDDdd - COIN1 - COIN2 - SERVICE
|Bookkeeping - Current month coin

Each entry is $10 byte long
|-
|$D09DE0
|$D0A01F
|$240
|YYMMDDdd - PLAY - CONTINUE - TIME
|Bookkeeping - Current month play

Each entry is $10 byte long
|-
|$D0A020
|$D0A0DF
|$C0
|00000000 - COIN1 - COIN2 - SERVICE
|Bookkeeping - Year coin
|-
|$D0A0E0
|$D0A19F
|$C0
|00000000 - PLAY - CONTINUE - TIME
|Bookkeeping - Year play
|}

[[Category:Cartridge systems]]

BIOSF CDDACMD

2019-07-10T16:25:20Z

Hpman:

==BIOSF_CDDACMD ($C0056A): Issue CDDA command ==

Command.b/track.b pair in D0. Can hook the [[68k interrupts|VBL interrupt]] for a while, depending on command.

See [[CDDA]].

[[Category:BIOS calls]]

CDDA

2019-07-10T16:07:28Z

Hpman: /* Commands */

'''This article needs checking and research'''.

CDDA stands for "CD Digital Audio". When loading a game, the "CDDA flag" byte at location $107 in the [[68k program header]] is checked with bit 7 masked off.

* $00 or $01 is for games which use the Z80 RAM default location $FEF8 to play CDDA tracks.
* $02 and up seems to be for games which either use a custom Z80 RAM location, or the BIOS call.

==Z80 RAM check method==
This method was probably implemented to simplify the porting of small games to the NeoGeo CD. Games that didn't need in-game file loading only had to have their vector table and [[sound driver]] code replaced. The sound driver itself translates the regular music commands to CDDA command/track pairs and drops them to a specific location in its RAM, which is then read back and executed by the BIOS when using the [[SYSTEM_IO]] ($C0044A) [[BIOS calls|call]] (see difference between the MVS and CD versions of Puzzled: no calls for music, M1 replaced).

In the sound drivers of CD games, a table is used to figure out if a received command concerns the YM2610 (mostly sound effects) or is a CDDA track.

Putting the CDDA flag byte at $107 to 0 or 1 enables this method and sets the Z80 return address to $FEF8.
Setting the CDDA flag to any other values allows to choose the address (word at $13A). If the address is 0, this method isn't used.

For example, [[Puzzled]] uses this method. The CDDA flag is set to 0 in the program header. The 68k sends the exact same "play music" Z80 commands as the MVS version of the game, the sound driver then converts them to CDDA ones and drops them at $FEF8. Command $0743 gets translated to $0532 (intro music, track 32).

==Direct method==

BIOS call $C0056A. Command/track pair in D0. (track number in BCD format).

Metal Slug 2 waits for a location in the BIOS RAM to be non-zero before calling $C0056A (?):
<pre>
#:
move.b d0,$300001 ;Watchdog kick, interrupts are disabled ?
tst.b $10F6D9
beq.s #
jsr $C0056A
</pre>

Viewpoint sends the command 4 ($04xx, xx being the track number):
The CDDA flag ($107) is $02, and $13A is $0000.

==Commands==

Commands are a two bytes (command type/track) put together into a short (ex: 0x0102)

{{16BitRegister|?|1|-|4|Sync|1|Command|2|Track # (BCD)|8}}

Commands are:
*0x0: read track (loop)
*0x1: read track (no loop)
*0x2: pause (ignores track parameter)
*0x3: resume (ignores track parameter)

Sync bit setting is:
*0: Seamless play
*1: Halt gameplay while drive is seeking

Commands over $07 are ignored.

Set $13A to $0000 if not using the Z80 RAM.
Set to $FFFF if using the default $FEF8 value.

'''BIOSF_SYSTEM_IO must be called every VBlank for direct CDDA commands to work.'''

CDDA data can be picked up through [[memory mapped registers]] CDDA_LEFTSTREAM and CDDA_RIGHTSTREAM.

[[Category:Audio system]]
[[Category:CD systems]]

CDDA

2019-07-10T16:07:15Z

Hpman: CDDA Commands

'''This article needs checking and research'''.

CDDA stands for "CD Digital Audio". When loading a game, the "CDDA flag" byte at location $107 in the [[68k program header]] is checked with bit 7 masked off.

* $00 or $01 is for games which use the Z80 RAM default location $FEF8 to play CDDA tracks.
* $02 and up seems to be for games which either use a custom Z80 RAM location, or the BIOS call.

==Z80 RAM check method==
This method was probably implemented to simplify the porting of small games to the NeoGeo CD. Games that didn't need in-game file loading only had to have their vector table and [[sound driver]] code replaced. The sound driver itself translates the regular music commands to CDDA command/track pairs and drops them to a specific location in its RAM, which is then read back and executed by the BIOS when using the [[SYSTEM_IO]] ($C0044A) [[BIOS calls|call]] (see difference between the MVS and CD versions of Puzzled: no calls for music, M1 replaced).

In the sound drivers of CD games, a table is used to figure out if a received command concerns the YM2610 (mostly sound effects) or is a CDDA track.

Putting the CDDA flag byte at $107 to 0 or 1 enables this method and sets the Z80 return address to $FEF8.
Setting the CDDA flag to any other values allows to choose the address (word at $13A). If the address is 0, this method isn't used.

For example, [[Puzzled]] uses this method. The CDDA flag is set to 0 in the program header. The 68k sends the exact same "play music" Z80 commands as the MVS version of the game, the sound driver then converts them to CDDA ones and drops them at $FEF8. Command $0743 gets translated to $0532 (intro music, track 32).

==Direct method==

BIOS call $C0056A. Command/track pair in D0. (track number in BCD format).

Metal Slug 2 waits for a location in the BIOS RAM to be non-zero before calling $C0056A (?):
<pre>
#:
move.b d0,$300001 ;Watchdog kick, interrupts are disabled ?
tst.b $10F6D9
beq.s #
jsr $C0056A
</pre>

Viewpoint sends the command 4 ($04xx, xx being the track number):
The CDDA flag ($107) is $02, and $13A is $0000.

==Commands==

Commands are a two bytes (command type/track) ut together into a short (ex: 0x0102)

{{16BitRegister|?|1|-|4|Sync|1|Command|2|Track # (BCD)|8}}

Commands are:
*0x0: read track (loop)
*0x1: read track (no loop)
*0x2: pause (ignores track parameter)
*0x3: resume (ignores track parameter)

Sync bit setting is:
*0: Seamless play
*1: Halt gameplay while drive is seeking

Commands over $07 are ignored.

Set $13A to $0000 if not using the Z80 RAM.
Set to $FFFF if using the default $FEF8 value.

'''BIOSF_SYSTEM_IO must be called every VBlank for direct CDDA commands to work.'''

CDDA data can be picked up through [[memory mapped registers]] CDDA_LEFTSTREAM and CDDA_RIGHTSTREAM.

[[Category:Audio system]]
[[Category:CD systems]]

BIOSF CDDACMD

2019-07-10T15:44:43Z

Hpman:

==BIOSF_CDDACMD ($C0056A): Issue CDDA command ==

Command.b/track.b pair in D0. Can hooks the [[68k interrupts|VBL interrupt]] for a while, depending on command.

See [[CDDA]].

[[Category:BIOS calls]]

L0 ROM

2019-06-10T21:50:59Z

Hpman: /* Example of GPU processing */

[[File:aes_lo.jpg|right|thumb|Toshiba LO ROM chip taken from an AES system.]]
[[File:cd2_lo.jpg|right|thumb|LO ROM chip found on a CDM3-2 board.]]

The L0 ROM is a 64KiB (sometimes 128KiB with A16 tied to ground) ROM chip found in every NeoGeo systems, which contains byte values used by {{Chipname|LSPC}} to shrink [[sprites]] '''vertically'''.

The dump is called 000-lo.lo in [[system ROM]] sets.

=Hash=

* CRC32: 5A86CFF2
* SHA-1: 5992277DEBADEB64D1C1C64B0A92D9293EAF7E4A

=Data format=

The data is made of 256 tables of 256 bytes, each table corresponding to a vertical shrinking value for sprites.

For the first 256 lines (top half of a full sprite), the index in the table is the line number of the sprite currently being drawn (scanline - Y position).

Each byte entry in the table is used as 2 nibbles:
*The upper nibble is the tile number index to read in the tilemap in [[VRAM]] SCB1 (0 to 15).
*The lower nibble is the line number of that tile to fetch in the [[C ROM]]s.

For the last 256 lines (bottom half of a full sprite), the index in the table is complemented: the table is read backwards.

*The upper nibble is the tile number index XOR $1F to read in the tilemap in VRAM SCB1 (16 to 31).
*The lower nibble is the line number XOR $F of that tile to fetch in the C ROMs.

==Example of GPU processing==
[[File:Ngscaling.png|right|thumb]]

(Maybe place this part in the LSPC page ?)

Sprite with Y zoom value = $1B and tile height = 2 (32 pixels).

{|class=wikitable
!Sprite line #
!L0 address
!L0 data
!Tilemap index
!Tile line used
|-
|0||$1B00||$00||0||0
|-
|1||$1B01||$08||0||8
|-
|2||$1B02||$10||1||0
|-
|colspan=5|...
|-
|26||$1B1A||$E8||14||8
|-
|27||$1B1B||$F8||15||8
|-
|28||$1B1C||$FF||15||15
|-
|29||$1B1D||$FF||15||15
|-
|colspan=5|...
|}

==Datasheet==

Official TC531001 datasheet: [[http://www.alldatasheet.com/datasheet-pdf/pdf/115078/TOSHIBA/TC531001.html]]

[[Category:Chips]]

Fix bankswitching

2019-02-24T02:39:06Z

Hpman:

In some late games, the [[S ROM]] 128KiB size limit was expanded with the use of {{Chipname|NEO-CMC}} chips.

This was devised as some sort of hack, taking advantage that the [[VDC]] continues rendering the [[fix layer]] outside of the visible screen area. This allows the chips to use the normally unused $7500~$75FF [[VRAM]] region to add bits to the tile numbers.

The chips use latches to store the additional bits at the beginning of a line, and "distributes" them during render. Synchronization might just be free running, started by /RESET and clocked with 6MB ?

Games marked [*] do hold 512KB fix data, however they ultimately only use a 128KB section, making the banking mechanism pointless.

NEO-CMC 042 has been observed using type 1 only. NEO-CMC 050 has been observed using both type 1 and type 2.

==Type 1 (per line banking)==

Infos from Mr K (MAME).

Used by:
* [[Garou - Mark of the Wolves]] (NEO-CMC 042)
* [[Metal Slug 3]] (NEO-CMC 042) [*]
* [[Metal Slug 4]] (NEO-CMC 050) [*] (parental advisory screen glitched due to wrong banking)

Type 1 allows fix data up to 512KiB (16384 tiles instead of 4096), by changing the bank (4 maximum) for groups of 2 line of tiles (or more ?). For this, the $7500~$75BF area in VRAM is used.

* The $7500~$753F area even words (32 total) contain a flag to indicate if the bank has to be changed for the corresponding tile line.
* The $7580~$75BF area even words (32 total) contain bank numbers for each of the tile lines.

If for a given line, the flag is set to $0200 (group size ?), the bank is read, changed, and will remain the same until it's changed again (it doesn't go back to 0 if the next line doesn't have the flag set).

Bank number:
{{16BitRegister|Has to be $FF ($0F works?)|8|Unused ?|6|Bank number|2}}

Bank bits are inverted (00 = bank 3, 11 = bank 0).

'''This needs further research, see MAME video/neogeo.c'''

==Type 2 (per tile banking)==

[[File:Cmc50bs.png|400px|right]]

Used by:
* [[The King of Fighters 2000]] (NEO-CMC 050)
* [[Matrimelee]] (NEO-CMC 050) [*]
* [[SNK vs. Capcom - SVC Chaos]] (NEO-CMC 050)
* [[The King of Fighters 2003]] (NEO-CMC 050)

Type 2 allows to add 2 bits to all the fix tile indexes individually, also allowing to use 16384 tiles at most but in a simpler manner and with no restrictions. For this, the $7500~$75DF area of VRAM is used.

Each word in this area gives the bank number for 6 horizontally consecutive fix tiles corresponding to the line:
{{16BitRegister|Unused ?|4|a|2|b|2|c|2|d|2|e|2|f|2}}

Those bank bits are inverted (00 = bank 3, 11 = bank 0).

The words are organized as in the fix map for a PAL screen (first and last lines aren't used): from top to bottom and left to right. The "e" and "f" group of bits are unused in the last column ($75C0+).

Examples:
*Tile at X=0, Y=1 has its bank number in bits a of $7500
*Tile at X=0, Y=5 has its bank number in bits a of $7504
*Tile at X=3, Y=2 has its bank number in bits d of $7501
*Tile at X=7, Y=9 has its bank number in bits b of $7528

[[Category:Video system]]

Fix bankswitching

2019-02-24T01:53:53Z

Hpman:

In some late games, the [[S ROM]] 128KiB size limit was expanded with the use of {{Chipname|NEO-CMC}} chips.

This was devised as some sort of hack, taking advantage that the [[VDC]] continues rendering the [[fix layer]] outside of the visible screen area. This allows the chips to use the normally unused $7500~$75FF [[VRAM]] region to add bits to the tile numbers.

The chips use latches to store the additional bits at the beginning of a line, and "distributes" them during render. Synchronization might just be free running, started by /RESET and clocked with 6MB ?

Games marked [*] do hold 512KB fix data, however they ultimately only use a 128KB section, making the banking mechanism pointless.

NEO-CMC 042 has been observed using type 1 only. NEO-CMC 050 has been observed using both type 1 and type 2.

==Type 1 (per line banking)==

Infos from Mr K (MAME).

Used by:
* [[Garou - Mark of the Wolves]] (NEO-CMC 042)
* [[Metal Slug 3]] (NEO-CMC 042) [*]
* [[Metal Slug 4]] (NEO-CMC 050) [*] (parental advisory screen glitched due to wrong banking)

The 042 version of NEO-CMC allows fix data up to 512KiB (16384 tiles instead of 4096), by changing the bank (4 maximum) for groups of 2 line of tiles (or more ?). For this, the $7500~$75BF area in VRAM is used.

* The $7500~$753F area even words (32 total) contain a flag to indicate if the bank has to be changed for the corresponding tile line.
* The $7580~$75BF area even words (32 total) contain bank numbers for each of the tile lines.

If for a given line, the flag is set to $0200 (group size ?), the bank is read, changed, and will remain the same until it's changed again (it doesn't go back to 0 if the next line doesn't have the flag set).

Bank number:
{{16BitRegister|Has to be $FF ($0F works?)|8|Unused ?|6|Bank number|2}}

Bank bits are inverted (00 = bank 3, 11 = bank 0).

'''This needs further research, see MAME video/neogeo.c'''

==Type 2 (per tile banking)==

[[File:Cmc50bs.png|400px|right]]

Used by:
* [[The King of Fighters 2000]] (NEO-CMC 050)
* [[Matrimelee]] (NEO-CMC 050) [*]
* [[SNK vs. Capcom - SVC Chaos]] (NEO-CMC 050)
* [[The King of Fighters 2003]] (NEO-CMC 050)

The 050 version of NEO-CMC allows to add 2 bits to all the fix tile indexes individually, also allowing to use 16384 tiles at most but in a simpler manner and with no restrictions. For this, the $7500~$75DF area of VRAM is used.

Each word in this area gives the bank number for 6 horizontally consecutive fix tiles corresponding to the line:
{{16BitRegister|Unused ?|4|a|2|b|2|c|2|d|2|e|2|f|2}}

Those bank bits are inverted (00 = bank 3, 11 = bank 0).

The words are organized as in the fix map for a PAL screen (first and last lines aren't used): from top to bottom and left to right. The "e" and "f" group of bits are unused in the last column ($75C0+).

Examples:
*Tile at X=0, Y=1 has its bank number in bits a of $7500
*Tile at X=0, Y=5 has its bank number in bits a of $7504
*Tile at X=3, Y=2 has its bank number in bits d of $7501
*Tile at X=7, Y=9 has its bank number in bits b of $7528

[[Category:Video system]]

Fix bankswitching

2019-02-24T01:51:00Z

Hpman:

In some late games, the [[S ROM]] 128KiB size limit was expanded with the use of {{Chipname|NEO-CMC}} chips.

This was devised as some sort of hack, taking advantage that the [[VDC]] continues rendering the [[fix layer]] outside of the visible screen area. This allows the chips to use the normally unused $7500~$75FF [[VRAM]] region to add bits to the tile numbers.

The chips use latches to store the additional bits at the beginning of a line, and "distributes" them during render. Synchronization might just be free running, started by /RESET and clocked with 6MB ?

Games marked [*] do hold 512KB fix data, however they ultimately only use a 128KB section, making the banking mechanism pointless.

NEO-CMC 042 has been observed using type 1 only. NEO-CMC 050 has been observed using both type 1 and type 2.

==Type 1 (per line banking)==

Infos from Mr K (MAME).

Used by:
* [[Garou - Mark of the Wolves]] (NEO-CMC 042)
* [[Metal Slug 3]] (NEO-CMC 042) [*]
* [[Metal Slug 4]] (NEO-CMC 050) [*]

The 042 version of NEO-CMC allows fix data up to 512KiB (16384 tiles instead of 4096), by changing the bank (4 maximum) for groups of 2 line of tiles (or more ?). For this, the $7500~$75BF area in VRAM is used.

* The $7500~$753F area even words (32 total) contain a flag to indicate if the bank has to be changed for the corresponding tile line.
* The $7580~$75BF area even words (32 total) contain bank numbers for each of the tile lines.

If for a given line, the flag is set to $0200 (group size ?), the bank is read, changed, and will remain the same until it's changed again (it doesn't go back to 0 if the next line doesn't have the flag set).

Bank number:
{{16BitRegister|Has to be $FF ($0F works?)|8|Unused ?|6|Bank number|2}}

Bank bits are inverted (00 = bank 3, 11 = bank 0).

'''This needs further research, see MAME video/neogeo.c'''

==Type 2 (per tile banking)==

[[File:Cmc50bs.png|400px|right]]

Used by:
* [[The King of Fighters 2000]] (NEO-CMC 050)
* [[Matrimelee]] (NEO-CMC 050) [*]
* [[SNK vs. Capcom - SVC Chaos]] (NEO-CMC 050)
* [[The King of Fighters 2003]] (NEO-CMC 050)

The 050 version of NEO-CMC allows to add 2 bits to all the fix tile indexes individually, also allowing to use 16384 tiles at most but in a simpler manner and with no restrictions. For this, the $7500~$75DF area of VRAM is used.

Each word in this area gives the bank number for 6 horizontally consecutive fix tiles corresponding to the line:
{{16BitRegister|Unused ?|4|a|2|b|2|c|2|d|2|e|2|f|2}}

Those bank bits are inverted (00 = bank 3, 11 = bank 0).

The words are organized as in the fix map for a PAL screen (first and last lines aren't used): from top to bottom and left to right. The "e" and "f" group of bits are unused in the last column ($75C0+).

Examples:
*Tile at X=0, Y=1 has its bank number in bits a of $7500
*Tile at X=0, Y=5 has its bank number in bits a of $7504
*Tile at X=3, Y=2 has its bank number in bits d of $7501
*Tile at X=7, Y=9 has its bank number in bits b of $7528

[[Category:Video system]]

Phantom

2019-01-25T14:39:53Z

Hpman: typo

Made by [[!Arcade!]].

Completely passive PROG board.

CHA board has a potted [[NEO-ZMC2]] or [[NEO-CMC]].

[[Metal Slug X - Super Vehicle-001]] fix suggested by DavidG: patch CHA A29 (SDRD1) to PROG B35 (/RESET).

[[Metal Slug X - Super Vehicle-001]] fix, making sense edition: attach a pullup resistor to the /RESET line.

/SLOTCS is routed to 4MB, because reasons. Re-route to ground to fix link cable features.

[[Category:Cartridge systems]]
[[Category:Chips]]

Phantom

2019-01-25T14:28:08Z

Hpman:

Made by [[!Arcade!]].

Completely passive PROG board.

CHA board has a potted [[NEO-ZMC2]] or [[NEO-CMC]].

[[Metal Slug X - Super Vehicle-001]] fix suggested by DavidG: patch CHA A29 (SDRD1) to PROG B35 (/RESET).

[[Metal Slug X - Super Vehicle-001]] fix, making sense edition: attach a pullup resistor to the /RESET line.

/SLOTCS is routed to 4MB, because reasons. Re-oute to ground to fix link cable features.

[[Category:Cartridge systems]]
[[Category:Chips]]

68k instructions timings

2018-11-25T16:44:10Z

Hpman: /* JMP, JSR, LEA, PEA and MOVEM instructions */

Mirrored information from [[http://oldwww.nvg.ntnu.no/amiga/MC680x0_Sections/mc68000timing.HTML oldwww.nvg.ntnu.no]]

The number of bus '''r'''ead and '''w'''rite cycles are shown in parenthesis as (r/w). Any other cycles are internal.

In the following tables, the headings have the following meanings:
* An : Address register operand
* Dn : Data register operand
* ea : Operand specified by an effective address
* M : Memory effective address operand

To get the real execution time, multiply the total cycles count by 83.33ns ([[Clock|1/12MHz]]). An example is given in each section.

The [[68k interrupts|vertical blank]] lasts exactly 40 lines * 384 pixels * 2 cycles per pixel = 30720 cycles (2.56ms).

See [[optimization]].

=Effective address operand calculation=

This table lists the number of clock periods required to compute an instruction's effective address. It includes fetching of any extension words, the address computation, and fetching of the memory operand.

{|class="wikitable"
!Syntax||Adressing mode||B,W||L
|-
|Dn
|Data register direct
|class="green"|0(0/0)
|class="green"|0(0/0)
|-
|An
|Address register direct
|class="green"|0(0/0)
|class="green"|0(0/0)
|-
|(An)
|Address register indirect
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|-
|(An)+
|Address register indirect, post inc.
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|-
| -(An)
|Address register indirect, pre dec.
|class="yellow"|6(1/0)
|class="orange"|10(2/0)
|-
|d(An)
|Address register indirect, displacement
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|d(An,ix)
|Address register indirect, index
|class="orange"|10(2/0)
|class="red"|14(3/0)
|-
|xxx.w
|Absolute short
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|xxx.l
|Absolute long
|class="orange"|12(3/0)
|class="red"|16(4/0)
|-
|d(PC)
|PC with displacement
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|d(PC,ix)
|PC with index
|class="yellow"|10(2/0)
|class="red"|14(3/0)
|-
|#xxx
|Immediate
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|}

Notes:
* Pre-dec is slower than post-inc
* There are no write cycles involved in processing the effective address
* The size of the index register (ix) does not affect execution time

=Move instructions=

These following two tables indicate the number of clock periods for the move instruction. This data includes instruction fetch, operand reads, and operand writes.

==Byte and word==

Example: '''move.b (a0)+,$10201D''' (Byte (An)+ to xxx.L) takes 20 cycles.

{|class="wikitable"
!  || Dn || An || (An) || (An)+ || -(An) || d(An) || d(An,ix) || xxx.W || xxx.L
|-
!Dn
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|8(1/1)||class="green"|8(1/1)
|class="green"|8(1/1)||class="yellow"|12(2/1)||class="yellow"|14(2/1)||class="yellow"|12(2/1)||class="yellow"|16(3/1)
|-
!An
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|8(1/1)||class="green"|8(1/1)
|class="green"|8(1/1)||class="yellow"|12(2/1)||class="yellow"|14(2/1)||class="yellow"|12(2/1)||class="yellow"|16(3/1)
|-
!(An)
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|12(2/1)||class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|-
!(An)+
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|-
!-(An)
|class="green"|10(2/0)||class="green"|10(2/0)||class="yellow"|14(2/1)||class="yellow"|14(2/1)||class="yellow"|14(2/1)
|class="orange"|18(3/1)||class="orange"|20(4/1)||class="orange"|18(3/1)||class="orange"|22(4/1)
|-
!d(An)
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!d(An,ix)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|18(3/1)||class="orange"|18(3/1)||class="orange"|18(3/1)
|class="orange"|22(4/1)||class="red"|24(4/1)||class="orange"|22(4/1)||class="red"|26(5/1)
|-
!xxx.W
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!xxx.L
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|20(4/1)||class="orange"|20(4/1)||class="orange"|20(4/1)
|class="red"|24(5/1)||class="red"|26(5/1)||class="red"|24(5/1)||class="red"|28(6/1)
|-
!d(PC)
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!d(PC,ix)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|18(3/1)||class="orange"|18(3/1)||class="orange"|18(3/1)
|class="orange"|22(4/1)||class="red"|24(4/1)||class="orange"|22(4/1)||class="red"|26(5/1)
|-
!#xxx
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|}

The size of the index register (ix) does not affect execution time.

==Long==

Example: '''move.l $05012C,4(a1,d0)''' (Long xxx.L to d(An,ix)) takes 34 cycles.

{|class="wikitable"
!  || Dn || An || (An) || (An)+ || -(An) || d(An) || d(An,ix) || xxx.W || xxx.L
|-
!Dn
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|12(1/2)||class="green"|12(1/2)||class="green"|12(1/2)
|class="yellow"|16(2/2)||class="yellow"|18(2/2)||class="yellow"|16(2/2)||class="yellow"|20(3/2)
|-
!An
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|12(1/2)||class="green"|12(1/2)||class="green"|12(1/2)
|class="yellow"|16(2/2)||class="yellow"|18(2/2)||class="yellow"|16(2/2)||class="yellow"|20(3/2)
|-
!(An)
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|-
!(An)+
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|-
!-(An)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|22(3/2)||class="orange"|22(3/2)||class="orange"|22(3/2)
|class="orange"|26(4/2)||class="orange"|28(4/2)||class="orange"|26(4/2)||class="red"|30(5/2)
|-
!d(An)
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(6/2)
|-
!d(An,ix)
|class="yellow"|18(4/0)||class="yellow"|18(4/0)||class="orange"|26(4/2)||class="orange"|26(4/2)||class="orange"|26(4/2)
|class="red"|30(5/2)||class="red"|32(5/2)||class="red"|30(5/2)||class="red"|34(6/2)
|-
!xxx.W
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(6/2)
|-
!xxx.L
|class="yellow"|20(5/0)||class="yellow"|20(5/0)||class="orange"|28(5/2)||class="orange"|28(5/2)||class="orange"|28(5/2)
|class="red"|32(6/2)||class="red"|34(6/2)||class="red"|32(6/2)||class="red"|36(7/2)
|-
!d(PC)
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(5/2)
|-
!d(PC,ix)
|class="yellow"|18(4/0)||class="yellow"|18(4/0)||class="orange"|26(4/2)||class="orange"|26(4/2)||class="orange"|26(4/2)
|class="red"|30(5/2)||class="red"|32(5/2)||class="red"|30(5/2)||class="red"|34(6/2)
|-
!#xxx
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|}

The size of the index register (ix) does not affect execution time.

=Standard instructions=

Example: '''add.w d3,a7''' (Word ea Dn + An) takes 8 cycles.

The number of clock periods shown in this table indicates the time required to perform the operations, store the results and read the next instruction. The total number of clock periods must be added respectively to those of the effective address calculation where indicated (+).

{|class="wikitable"
!  || Size || <ea>,An * || <ea>,Dn || Dn,<M>
|-
!rowspan=2|ADD
|B,W
|class="orange"|8(1/0)+||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
|class="yellow"|6(1/0)+**||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|-
!rowspan=2|AND
|B,W
| - ||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
| - ||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|-
!rowspan=2|CMP
|B,W
|class="yellow"|6(1/0)+||class="green"|4(1/0)+|| -
|-
|L
|class="yellow"|6(1/0)+||class="yellow"|6(1/0)+|| -
|-
!DIVS
| - || - ||class="red"|158(1/0)+|| -
|-
!DIVU
| - || - ||class="red"|140(1/0)+|| -
|-
!rowspan=2|EOR
|B,W
| - ||class="green"|4(1/0) ***||class="orange"|8(1/1) +
|-
|L
| - ||class="orange"|8(1/0) ***||class="red"|12(1/2) +
|-
!MULS
| - || - ||class="red"|70(1/0)+*|| -
|-
!MULU
| - || - ||class="red"|70(1/0)+*|| -
|-
!rowspan=2|OR
|B,W
| - ||class="green"|4(1/0) +**||class="orange"|8(1/1) +
|-
|L
| - ||class="yellow"|6(1/0) +**||class="red"|12(1/2) +
|-
!rowspan=2|SUB
|B,W
|class="orange"|8(1/0)+||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
|class="yellow"|6(1/0)+**||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|}

<syntaxhighlight lang="text">
notes: + Add effective address calculation time
^ Word or long only
* Indicates maximum value
** The base time of six clock periods is increased to eight
if the effective address mode is register direct or
immediate (effective address time should also be added)
*** Only available effective address mode is data register direct

DIVS,DIVU - The divide algorithm used by the MC68000 provides less
than 10% difference between the best and the worst case
timings.
MULS,MULU - The multiply algorithm requires 38+2n clocks where
n is defined as:
MULU: n = the number of ones in the <ea>
MULS: n = concatenate the <ea> with a zero as the LSB;
n is the resultant number of 10 or 01 patterns
in the 17-bit source; i.e., worst case happens
when the source is $5555
</syntaxhighlight>

=Immediate instructions=

The number of clock periods periods shown in this table includes the time to fetch immediate operands, perform the operations, store the results and read the next operation. The total number of clock periods must be added respectively to those of the effective address calculation where indicated (+).

{|class="wikitable"
!  || Size || #,Dn || #,An || #,M
|-
!rowspan=2|ADDI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|ADDQ
|B,W
|class="green"|4(1/0)||class="yellow"|8(1/0)*||class="orange"|12(1/2)+
|-
|L
|class="yellow"|8(1/0)||class="yellow"|8(1/0)||class="orange"|12(1/2)+
|-
!rowspan=2|ANDI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(1/2)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/1)+
|-
!rowspan=2|CMPI
|B,W
|class="green"|8(2/0)|| - ||class="green"|8(2/0)+
|-
|L
|class="orange"|14(3/0)|| - ||class="yellow"|12(3/1)+
|-
!rowspan=2|EORI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!MOVEQ
|L
|class="green"|4(1/0)|| - || -
|-
!rowspan=2|ORI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|SUBI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|SUBQ
|B,W
|class="green"|4(1/0)||class="yellow"|8(1/0)*||class="yellow"|8(1/1)+
|-
|L
|class="yellow"|8(1/0)||class="yellow"|8(1/0)||class="orange"|12(1/2)+
|}

<syntaxhighlight lang="text">
+ Add effective address calculation time
* word only
</syntaxhighlight>

=Single operand instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the single operand
instructions. The number of clock periods and the number of read and write cycles
must be added respectively to those of the effective address calculation
where indicated.

instruction size register memory

CLR byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NBCD byte 6(1/0) 8(1/1) +
NEG byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NEGX byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NOT byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
Scc byte,false 4(1/0) 8(1/1) +
byte,true 6(1/0) 8(1/1) +
TAS # byte 4(1/0) 10(1/1) +
TST byte,word 4(1/0) 4(1/0) +
long 4(1/0) 4(1/0) +

+ add effective address calculation time
# This instruction should never be used on the Amiga as its invisiable
read/write cycle can disrupt system DMA.
</syntaxhighlight>

=Shift and rotate instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the shift and rotate
instructions. The number of clock periods and the number of read and write
cycles must be added respectively to those of the effective address
calculation where indicated.

instruction size register memory

ASR,ASL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
LSR,LSL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
ROR,ROL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
ROXR,ROXL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -

+ add effective address calculation time
n is the shift or rotate count
</syntaxhighlight>

=Bit manipulation instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods required for the bit
manipulation instructions. The number of clock periods and the number of read and
write cycles must be added respectively to those of the effective address
calculation where indicated. Dynamic: register, static: immediate.

instruction size dynamic static
register memory register memory
BCHG byte - 8(1/1) + - 12(2/1) +
long 8(1/0) * - 12(2/0) * -
BCLR byte - 8(1/1) + - 12(2/1) +
long 10(1/0) * - 14(2/0) * -
BSET byte - 8(1/1) + - 12(2/1) +
long 8(1/0) * - 12(2/0) * -
BTST byte - 4(1/0) + - 8(2/0) +
long 6(1/0) - 10(2/0) -

+ add effective address calculation time
* indicates maximum value
</syntaxhighlight>

=Conditional instructions=

{|class="wikitable"
!Mnemonic || Displacement || Branch taken || Not taken
|-
|rowspan=2|Bcc
|byte
|class="yellow"|10(2/0)||class="green"|8(1/0)
|-
|word
|class="yellow"|10(2/0)||class="orange"|12(1/0)
|-
|rowspan=2|BRA
|byte
|class="yellow"|10(2/0)
|
|-
|word
|class="yellow"|10(2/0)
|
|-
|rowspan=2|BSR
|byte
|class="red"|18(2/2)
|
|-
|word
|class="red"|18(2/2)
|
|-
|rowspan=2|DBcc
|cc true
|
|class="orange"|12(2/0)
|-
|cc false
|class="yellow"|10(2/0)
|class="orange"|14(3/0)
|}

=JMP, JSR, LEA, PEA and MOVEM instructions=

<syntaxhighlight lang="text">
This Table indicates the number of clock periods required for the jump,
jump-to-subroutine, load effective address, push effective address and
move multiple registers instructions.

instr size (An) (An)+ -(An) d(An) d(An,ix)+ xxx.W xxx.L d(PC) d(PC,ix)*
JMP - 8(2/0) - - 10(2/0) 14(3/0) 10(2/0) 12(3/0) 10(2/0) 14(3/0)
JSR - 16(2/2) - - 18(2/2) 22(2/2) 18(2/2) 20(3/2) 18(2/2) 22(2/2)
LEA - 4(1/0) - - 8(2/0) 12(2/0) 8(2/0) 12(3/0) 8(2/0) 12(2/0)
PEA - 12(1/2) - - 16(2/2) 20(2/2) 16(2/2) 20(3/2) 16(2/2) 20(2/2)
MOVEM word 12+4n 12+4n - 16+4n 18+4n 16+4n 20+4n 16+4n 18+4n
M->R (3+n/0) (3+n/0) - (4+n/0) (4+n/0) (4+n/0) (5+n/0) (4+n/0) (4+n/0)
long 12+8n 12+8n - 16+8n 18+8n 16+8n 20+8n 16+8n 18+8n
(3+2n/0) (3+2n/0) - (4+2n/0) (4+2n/0) (4+2n/0) (5+2n/0) (4+2n/0) (4+2n/0)
MOVEM word 8+4n - 8+4n 12+4n 14+4n 12+4n 16+4n - -
R->M (2/n) - (2/n) (3/n) (3/n) (3/n) (4/n) - -
long 8+8n - 8+8n 12+8n 14+8n 12+8n 16+8n - -
(2/2n) - (2/2n) (3/2n) (3/2n) (3/2n) (4/2n) - -

n is the number of registers to move
* is the size of the index register (ix) does not affect the instruction's
execution time
</syntaxhighlight>

=Multi-precision instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the multi-precision
instructions. The number of clock periods includes the time to fetch both
operands, perform the operations, store the results and read the next
instructions.

instruction size op Dn,Dn op M,M

ADDX byte,word 4(1/0) 18(3/1)
long 8(1/0) 30(5/2)
CMPM byte,word - 12(3/0)
long - 20(5/0)
SUBX byte,word 4(1/0) 18(3/1)
long 8(1/0) 30(5/2)
ABCD byte 6(1/0) 18(3/1)
SBCD byte 6(1/0) 18(3/1)
</syntaxhighlight>

=Miscellaneous instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the following
miscellaneous instructions. The number of clock periods and plus the number
of read and write cycles must be added to those of the effective address
calculation where indicated.

instruction size register memory

ANDI to CCR byte 20(3/0) -
ANDI to SR word 20(3/0) -
CHK - 10(1/0) + -
EORI to CCR byte 20(3/0) -
EORI to SR word 20(3/0) -
ORI to CCR byte 20(3/0) -
ORI to SR word 20(3/0) -
MOVE from SR - 6(1/0) 8(1/1)+
MOVE to CCR - 12(1/0) 12(1/0)+
MOVE to SR - 12(1/0) 12(1/0)+
EXG - 6(1/0) -
EXT word 4(1/0) -
long 4(1/0) -
LINK - 16(2/2) -
MOVE from USP - 4(1/0) -
MOVE to USP - 4(1/0) -
NOP - 4(1/0) -
RESET - 132(1/0) -
RTE - 20(5/0) -
RTR - 20(5/0) -
RTS - 16(4/0) -
STOP - 4(0/0) -
SWAP - 4(1/0) -
TRAPV (No Trap) - 4(1/0) -
UNLK - 12(3/0) -

+ add effective address calculation time
</syntaxhighlight>

=Move Peripheral instructions=

<syntaxhighlight lang="text">
instruction size register->memory memory->register

MOVEP word 16(2/2) 16(4/0)
long 24(2/4) 24(6/0)
</syntaxhighlight>

=Exception processing=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for exception processing.
The number of clock periods includes the time for all stacking, the vector
fetch and the fetch of the first two instruction words of the handler routine.

exception periods

address error 50(4/7)
bus error 50(4/7)
CHK instruction (trap taken) 44(5/3)+
Divide by Zero 42(5/3)
illegal instruction 34(4/3)
interrupt 44(5/3)*
privilege violation 34(4/3)
_____
RESET ** 40(6/0)
trace 34(4/3)
TRAP instruction 38(4/3)
TRAPV instruction (trap taken) 34(4/3)

+ add effective address calculation time
* the interrupt acknowledge cycle is assumed to take four
clock periods
_____ ____
** indicates the time from when RESET and HALT are first
sampled as negated to when instruction execution starts
</syntaxhighlight>

[[Category:Base system]]
[[Category:Code]]

Fatal Fury 2

2018-10-22T10:55:23Z

Hpman: Build date

{{GameInfo|right
|en_title=Fatal Fury 2
|jp_title=Garou Densetsu 2 - arata-naru tatakai
|jp_title2=餓狼伝説 2
|developer=SNK
|ngh_id=047
|megcount=106
|mvs_release=yes
|mvs_release_en=y
|mvs_release_jp=y
|mvs_romset=fatfury2
|mvs_date=1992
|mvs_pchip=
|mvs_pboard=PROG-G2
|mvs_cboard=CHA42G-1
|aes_release=y
|aes_release_jp=y
|aes_release_en=y
|aes_romset=fatfury2
|aes_date=05/03/93
|cd_release=y
|cd_release_jp=y
|cd_release_en=y
|cd_date=09/09/94
}}

<center>
<gallery widths="320" heights="240">
File:FF2build.png|Fatal Fury 2 build date.
</gallery>
</center>

==Protection==

Uses {{Chipname|PRO-CT0}} as a protection chip.

If one of the multiple protection checks fail, a flag is silently set. The game runs correctly during the first match, but the opponent in the second match will not be able to get hit, and the timer in next matches will be set to 2 seconds.

If this happens on a real system, the cartridge might be a [[bootleg]] or simply defective.

==Protection code==

Uses lots of bogus addresses to confuse hackers.

<syntaxhighlight>
00296A:
move #$5555,$255552 ;LOAD
move.b $255551,$10AC2E ;Read GAD/GBD: $FF
move.b d0,$255551 ;Clock
move.b $2FFFF1,$10AC2F ;Read GAD/GBD: $00
move.b d0,$2FFFF1 ;Clock
move.b $200001,$10AC30 ;Read GAD/GBD: $FF
move.b d0,$2FF001 ;Clock
move.b $2FF001,$10AC31 ;Read GAD/GBD: $00
cmpi.l #$FF00FF00,$10AC2E ;Compare reads
beq +
move #$3328,24580(a5) ;Lock up flag ?
+:
rts
</syntaxhighlight>

<pre>
Load C: 00110011001100110011001100110011 ($33333333)

PRO-CT0 serialize:
00110011 3
00110011 2
00110011 1
00110011 0

GAD/GBD to D7~D0 remap (no effect):

00110011 1
00110011 0
00110011 3
00110011 2
||||||||
00FF00FF ->
</pre>

<syntaxhighlight>
012530:
move #$1234,$256782 ;LOAD C $366A061A (00110110 01101010 00000110 00011010)
move.b $236001,18642(a5) ;Read GAD/GBD
move.b #$20,$236001 ;Clock
move.b $236001,18643(a5) ;Read GAD/GBD
move.b #$20,$236001 ;Clock
move.b $236001,18644(a5) ;Read GAD/GBD
move.b #$20,$236001 ;Clock
move.b $236001,18645(a5) ;Read GAD/GBD
move.b #$20,$236001 ;Clock
move.l 18642(a5),d0
subi.l #$F05A3601,d0 ;Compare reads
rts
</syntaxhighlight>

<pre>
Load C: 00110110011010100000011000011010 ($366A061A)

PRO-CT0 serialize:
00110110 3
01101010 2
00000110 1
00011010 0

GAD/GBD to D7~D0 remap:

00000110 1
00011010 0
00110110 3
01101010 2
||||||||
01365AF0 ->

</pre>

<syntaxhighlight>
move #$1824,$242812 ;LOAD C
move.b $236009,18642(a5) ;Read GAD/GBD with H (reverse)
move.b #$20,$236009 ;Clock
move.b $236009,18643(a5) ;Read GAD/GBD with H (reverse)
move.b #$20,$236009 ;Clock
move.b $236009,18644(a5) ;Read GAD/GBD with H (reverse)
move.b #$20,$236009 ;Clock
move.b $236009,18645(a5) ;Read GAD/GBD with H (reverse)
move.b #$20,$236009 ;Clock
move.l 18642(a5),d0
subi.l #$81422418,d0 ;Compare reads
rts
</syntaxhighlight>

<pre>
Load C: 00100100100000010100001000011000 ($24814218)

PRO-CT0 serialize:
00100100 3
10000001 2
01000010 1
00011000 0

GAD/GBD to D7~D0 remap:

01000010 1
00011000 0
00100100 3
10000001 2
||||||||
18244281 <-

</pre>

<syntaxhighlight>
move #$1234,$256782 ;LOAD C
move.b $236005,18642(a5) ;Read GAD/GBD with EVEN (nibble swap)
move.b #$20,$236005 ;Clock
move.b $236005,18643(a5) ;Read GAD/GBD with EVEN (nibble swap)
move.b #$20,$236005 ;Clock
move.b $236005,18644(a5) ;Read GAD/GBD with EVEN (nibble swap)
move.b #$20,$236005 ;Clock
move.b $236005,18645(a5) ;Read GAD/GBD with EVEN (nibble swap)
move.b #$20,$236005 ;Clock
move.l 18642(a5),d0
subi.l #$0FA56310,d0 ;Compare reads
rts
</syntaxhighlight>

<pre>
Load C: 00110110011010100000011000011010 ($366A061A)

PRO-CT0 serialize:
00110110 3
01101010 2
00000110 1
00011010 0

GAD/GBD to D7~D0 remap:

00000110 1
00011010 0
00110110 3
01101010 2
||||||||
01365AF0 nibble swap: 1063A50F ->

</pre>

<syntaxhighlight>
move #$1824,$242812 ;LOAD C
move.b $23600D,18642(a5) ;Read GAD/GBD with H and EVEN
move.b #$20,$23600D ;Clock
move.b $23600D,18643(a5) ;Read GAD/GBD with H and EVEN
move.b #$20,$23600D ;Clock
move.b $23600D,18644(a5) ;Read GAD/GBD with H and EVEN
move.b #$20,$23600D ;Clock
move.b $23600D,18645(a5) ;Read GAD/GBD with H and EVEN
move.b #$20,$23600D ;Clock
move.l 18642(a5),d0
subi.l #$18244281,d0 ;Compare reads
rts
</syntaxhighlight>

<pre>
Load C: 00100100100000010100001000011000 ($24814218)

PRO-CT0 serialize:
00100100 3
10000001 2
01000010 1
00011000 0

GAD/GBD to D7~D0 remap:

01000010 1
00011000 0
00100100 3
10000001 2
||||||||
18244281 nibble swap: <- 81422418

</pre>

[[Category:Games]]

File:FF2build.png

2018-10-22T10:52:42Z

Hpman: FF2 build date

FF2 build date

BIOS RAM locations

2018-08-20T00:05:42Z

Hpman:

The locations are (?) guaranteed to be identical accross all [[system ROM]] versions so that games can use them regardless of the system type.

=Game Related=

{| class="regdef"
| '''Address'''
| '''DEF name'''
| '''Size'''
| '''Set by'''
| '''Description'''
|-
|$10FD84~$10FD93
|BIOS_GAME_DIP
|16 bytes
|BIOS
|[[Software DIPs]] values (game configuration)
|-
|$10FDAE
|BIOS_USER_REQUEST
|byte
|BIOS
|Request code for the [[USER subroutine]]. 0:Init, 1:Boot animation, 2:Demo, 3:Title
|-
|$10FDAF
|BIOS_USER_MODE
|byte
|BIOS/Game
|Used by the game to tell what it's doing: 0:Init/Boot animation, 1:Title/Demo, 2:Game
[[Game selection]] can only be done on MVS systems when this byte is < 2
|-
|$10FDB0
|BIOS_CREDIT_DEC
|4 bytes
|Game
|Credit decrement value for each player (1, 2, 3, 4) when calling [[CREDIT DOWN]].
|-
|$10FDB4
|BIOS_START_FLAG
|byte
|BIOS
|Used when calling the [[PLAYER START subroutine]]. The 4 LSBs correspond to the player who pushed start.
|-
|$10FDB6
|BIOS_PLAYER_MOD1
|byte
|Game
|rowspan="4|Sets player status. 0:Never played, 1:Playing, 2:Continue option being displayed, 3:Game over
|-
|$10FDB7
|BIOS_PLAYER_MOD2
|byte
|Game
|-
|$10FDB8
|BIOS_PLAYER_MOD3
|byte
|Game
|-
|$10FDB9
|BIOS_PLAYER_MOD4
|byte
|Game
|-
|$10FEC5
|BIOS_TITLE_MODE
|byte
|BIOS/Game
|Newer games set this to 1 in their command 3 [[USER subroutine]]. It prevents the system ROM from calling command 3 twice after game over if credits are already in the system.
|}

=System Related=

{| class="regdef"
| '''Address'''
| '''DEF name'''
| '''Size'''
| '''Set by'''
| '''Description'''
|-
|$10FD80
|BIOS_SYSTEM_MODE
|byte
|BIOS
|0:BIOS wants vblank (system mode), $80:Ok to use vblank (game mode)
|-
|$10FD81
|BIOS_SYSRET_STATUS
|byte
|BIOS
|Internal value which stores the function code that [[SYSTEM_RETURN]] will call.
*0 : Init bram/select valid game for eye-catcher
*1 : Set the EL-LED to the correct value
*2 : Switch to the next slot, relaunch eye-catcher
*3 : After a gameover, save the playtime for bookeeping, switch to DEMO mode, reset the workbackup ram
*4 : Switch next slot (select p1 pressed)
*5 : Switch to previous slot (select p2 pressed)
*6 : Called after a coin deposit, does nothing
|-
|$10FD82
|BIOS_MVS_FLAG
|byte
|BIOS
|System type. 0:AES, 1:MVS
|-
|$10FD83
|BIOS_COUNTRY_CODE
|byte
|BIOS
|0:Japan, 1:USA, 2:Europe
|-
|$10FE80
|BIOS_DEVMODE
|8 bytes
|BIOS
|All set to 0x00 in normal mode. Set to "1streset" string in developer mode
|}

=Joypad Related=

These values are updated by calling [[SYSTEM_IO]].

{| class="regdef"
| '''Address'''
| '''DEF name'''
| '''Size'''
| '''Set by'''
| '''Description'''
|-
|$10FD94
|BIOS_P1STATUS
|byte
|BIOS
|0:No connection, 1:Normal joypad, 2:Expanded joypad, 3:Mahjong controller, 4:Keyboard
|-
|$10FD95
|BIOS_P1PREVIOUS
|byte
|BIOS
|Inputs on previous frame [DCBA Right Left Down Up] (positive logic).
|-
|$10FD96
|BIOS_P1CURRENT
|byte
|BIOS
|Inputs on current frame [DCBA Right Left Down Up] (positive logic).
|-
|$10FD97
|BIOS_P1CHANGE
|byte
|BIOS
|Buttons just pressed, active edge [DCBA Right Left Down Up] (positive logic).
|-
|$10FD98
|BIOS_P1REPEAT
|byte
|BIOS
|Active edge + repeat every 8 frames after 16 frames. [DCBA Right Left Down Up] (positive logic).
|-
|$10FD99
|BIOS_P1TIMER
|byte
|BIOS
|Repeat timer (counts down from 8 to 0).
|-
|$10FD9A~$10FD9F
|Same for P2
|6 bytes
|BIOS
|See above
|-
|$10FDA0~$10FDA6
|Same for P3
|6 bytes
|BIOS
|See above
|-
|$10FDA7~$10FDAB
|Same for P4
|6 bytes
|BIOS
|See above
|-
|$10FDAC
|BIOS_STATCURNT
|byte
|BIOS
|Select P4, Start P4, Select P3, Start P3, Select P2, Start P2, Select P1, Start P1 (positive logic)

On AES systems the select bits are always read as 0 ?
|-
|$10FDAD
|BIOS_STATCHANGE
|byte
|BIOS
|Select P4, Start P4, Select P3, Start P3, Select P2, Start P2, Select P1, Start P1 (positive logic)

On AES systems the select bits are always read as 0 ?
|-
|$10FEDC
|BIOS_STATCURNT_RAW
|byte
|BIOS
|Select P4, Start P4, Select P3, Start P3, Select P2, Start P2, Select P1, Start P1 (positive logic)
|-
|$10FEDD
|BIOS_STATCHANGE_RAW
|byte
|BIOS
|Select P4, Start P4, Select P3, Start P3, Select P2, Start P2, Select P1, Start P1 (positive logic)
|}

=Memory Card Related=

See [[CARD]] for more details on those variables.

{| class="regdef"
| '''Address'''
| '''DEF name'''
| '''Size'''
| '''Set by'''
| '''Description'''
|-
|$10FDC4
|BIOS_CARD_COMMAND
|byte
|BIOS or Game
|Command to execute
|-
|$10FDC5
|BIOS_CARD_MODE
|byte
|BIOS?
|Internal use?
|-
|$10FDC6
|BIOS_CARD_ANSWER
|byte
|BIOS
|Answer code for the command
|-
|$10FDC8
|BIOS_CARD_START
|longword
|BIOS or Game
|Pointer to data
|-
|$10FDCC
|BIOS_CARD_SIZE
|word
|BIOS or Game
|Size of data
|-
|$10FDCE
|BIOS_CARD_FCB
|word
|BIOS or Game
|Game NGH number
|-
|$10FDD0
|BIOS_CARD_SUB
|byte or word
|BIOS or Game
|Game Subnumber
|}

=MESS OUT Related=

See [[MESS_OUT]] to know how to use this routine.

{| class="regdef"
| '''Address'''
| '''DEF name'''
| '''Size'''
| '''Set by'''
| '''Description'''
|-
|$10FDBE
|BIOS_MESS_POINT
|longword
|Game
|Buffer pointer
|-
|$10FDC2
|BIOS_MESS_BUSY
|byte
|Game
|0:Allow MESS_OUT, 1:Skip MESS_OUT
|}

=Calendar Related=

Those value are updated when [[READ_CALENDAR]] is called

{| class="regdef"
| '''Address'''
| '''DEF name'''
| '''Size'''
| '''Set by'''
| '''Description'''
|-
|$10FDD2
|BIOS_YEAR
|byte
|BIOS
|Current year
|-
|$10FDD3
|BIOS_MONTH
|byte
|BIOS
|Current month
|-
|$10FDD4
|BIOS_DAY
|byte
|BIOS
|Current day
|-
|$10FDD5
|BIOS_WEEKDAY
|byte
|BIOS
|Current weekday (Sunday = 00, Monday = 01 ... Saturday = 06)
|-
|$10FDD6
|BIOS_HOUR
|byte
|BIOS
|Current hour (24h format)
|-
|$10FDD7
|BIOS_MINUTE
|byte
|BIOS
|Current minute
|-
|$10FDD8
|BIOS_SECOND
|byte
|BIOS
|Current minute
|}

=Internal=

{| class="regdef"
| '''Address'''
| '''DEF name'''
| '''Size'''
| '''Set by'''
| '''Description'''
|-
|$10FCEF
|BIOS_SLOTCHECK
|byte
|BIOS
|[[Slot check]] passed if non-zero
|-
|$10FDDA
|BIOS_COMPULSION_TIMER
|byte
|BIOS
|Timer for the game compulsion start feature, in seconds. BCD format.
|-
|$10FDDB
|BIOS_COMPULSION_FRAME_TIMER
|byte
|BIOS
|Frame-based timer for the game compulsion start feature.

When it underflows, the timer is reset to 59 and START_COMPULSION_TIMER is decremented.
|-
|$10FE88
|BIOS_FRAME_COUNTER
|longword
|BIOS
|Frame counter, updated by SYSTEM_IO.
|-
|$10FEBF
|BIOS_BRAM_USED
|byte
|BIOS
|0:[[Backup RAM]] not currently used, 1:Currently used
|-
|$10FEE1
|BIOS_FRAME_SKIP
|byte
|BIOS
|Number of frames to skip in the routine which checks demo_end or if the player has pressed start.

Decremented in [[SYSTEM_IO]].
|-
|$10FEE3
|BIOS_INT1_SKIP
|byte
|BIOS
|Only used in [[SYSTEM_INT1]]. If non-zero, will only do the [[RTC]] check during INT1.
|-
|$10FEE4
|BIOS_INT1_FRAME_COUNTER
|byte
|BIOS
|Frame counter, only used in [[SYSTEM_INT1]]
|}

=4P mode related=

Thoses will be valid on a 4P compatible bios only

{| class="regdef"
| '''Address'''
| '''DEF name'''
| '''Size'''
| '''Set by'''
| '''Description'''
|-
|$10FEF8
|BIOS_4P_REQUESTED
|byte
|BIOS
|Keeps a local copy of hard dip 2 status on bootup.

0: dip2 wasn't set

$2: dip 2 was on.
|-
|$10FEFA
|BIOS_4P_MODE
|byte
|BIOS
|Main 4P flag, is set when hard dip 2 is on and 4P board is found.

0: regular play

$FF: 4P mode game
|-
|$10FEFB
|BIOS_4P_PLUGGED
|byte
|BIOS
|0: 4P board not found

$FF: 4P board plugged

4P compatible bios will check for 4P board regardless of dip2 switch status.
|}

=CD only=

{| class="regdef"
| '''Address'''
| '''DEF name'''
| '''Size'''
| '''Set by'''
| '''Description'''
|-
|$10FEF4
|BIOS_UPDEST
|Long
|Game
|Copy destination address
|-
|$10FEF8
|BIOS_UPSRC
|Long
|Game
|Copy source address
|-
|$10FEFC
|BIOS_UPSIZE
|Long
|Game
|Copy data size
|-
|$10FEDA
|BIOS_UPZONE
|Byte
|Game
|Copy zone (0=PRG, 1=FIX, 2=SPR, 3=Z80, 4=PCM, 5=PAT, 7=OBJ, 8=A** files)
|-
|$10FEDB
|BIOS_UPBANK
|Byte
|Game
|Copy bank
|}

=Others=

{| class="regdef"
| '''Address'''
| '''DEF name'''
| '''Size'''
| '''Set by'''
| '''Description'''
|-
|$10FCEE
|?
|byte
|GAME
|Z80/M ROM check pass

|}

[[Category:Base system]]

Palettes

2018-06-30T19:01:31Z

Hpman: Undo revision 6150 by Hpman (talk) I is stoopid

[[File:Palmap.png|500px|thumb|Palettes organization.]]
There are 2 banks (one usable at a time) of 256 palettes available. Each palette has 16 color entries, the first being the transparent index ("color 0"), the 15 others are real colors, made of 16-bit RGB definitions.

[[Sprites|Sprite]] tiles can use '''any''' of the 256 palettes, while the [[Fix layer|fix]] tiles can '''only use the first 16'''.

The maximum number of colors on screen without [[timer interrupt]] tricks is: 256 palettes * 15 colors = '''3840''' (out of 2^16 = 65536).

=Color format=

See [[colors]].

=Access=

Palettes are located at $400000 in the [[68k memory map]]. They're physically stored in the [[palette RAM]].

Byte writes are allowed, but the value will be written to both bytes of the word (/WE pins are tied together).

The palettes can be read and written at full speed at any time. During active display, since the CPU has priority over rendering, the color read or written will be displayed during at least one pixel, resulting in noticeable "snow" if multiple colors are updated. A workaround is to update the palettes only during blanking (horizontal or vertical), over multiple frames if necessary.

The bank can be set by doing a byte write to registers {{Reg|REG_PALBANK1}} or {{Reg|REG_PALBANK0}}.

=Special colors=

There are two special colors used:

* The first color of the palette bank ($400000) is the [[reference color|'''R'''eference color]] for the video output. It always has to be pure black ($8000) otherwise monitors won't be happy and other colors won't be displayed correctly.
* The last color of the palette bank ($401FFE) is the [[backdrop color|'''B'''ackdrop color]], the color of the backmost [[layer]] on the screen. Caused by line buffers in {{Chipname|NEO-B1}} being cleared to $FFF (referencing the last color of the last palette).

[[Category:Video system]]

Palettes

2018-06-30T19:00:28Z

Hpman:

[[File:Palmap.png|500px|thumb|Palettes organization.]]
There are 2 banks (one usable at a time) of 256 palettes available. Each palette has 16 color entries, the first being the transparent index ("color 0"), the 15 others are real colors, made of 16-bit RGB definitions.

[[Sprites|Sprite]] tiles can use '''any''' of the 256 palettes, while the [[Fix layer|fix]] tiles can '''only use the first 16'''.

The maximum number of colors on screen without [[timer interrupt]] tricks is: 256 palettes * 15 colors + 1 (backdrop) = '''3841''' (out of 2^16 = 65536).

=Color format=

See [[colors]].

=Access=

Palettes are located at $400000 in the [[68k memory map]]. They're physically stored in the [[palette RAM]].

Byte writes are allowed, but the value will be written to both bytes of the word (/WE pins are tied together).

The palettes can be read and written at full speed at any time. During active display, since the CPU has priority over rendering, the color read or written will be displayed during at least one pixel, resulting in noticeable "snow" if multiple colors are updated. A workaround is to update the palettes only during blanking (horizontal or vertical), over multiple frames if necessary.

The bank can be set by doing a byte write to registers {{Reg|REG_PALBANK1}} or {{Reg|REG_PALBANK0}}.

=Special colors=

There are two special colors used:

* The first color of the palette bank ($400000) is the [[reference color|'''R'''eference color]] for the video output. It always has to be pure black ($8000) otherwise monitors won't be happy and other colors won't be displayed correctly.
* The last color of the palette bank ($401FFE) is the [[backdrop color|'''B'''ackdrop color]], the color of the backmost [[layer]] on the screen. Caused by line buffers in {{Chipname|NEO-B1}} being cleared to $FFF (referencing the last color of the last palette).

[[Category:Video system]]

FM

2018-06-18T19:32:01Z

Hpman:

The FM ('''F'''requency '''M'''odulation) is part of the {{Chipname|YM2610}} sound chip. It provides '''4 channels''', each having their own set of 4 operators, panning and amplitude values. It's the most used way of producing music in games.

=Common registers=

{|class="wikitable"
!Address (Z80 port 4)
!Data (Z80 port 5)
|
|-
|$21
|{{8BitRegister|?|8}}
| Test register. Ignore or set to $00 for normal operation.
|-
|$22
|{{8BitRegister|-|4|On|1|Control|3}}
| LFO control and frequency (see below).
|-
|$28
|{{8BitRegister|Slot (OP4/OP3/OP2/OP1)|4|-|1|Channel|3|}}
| Key On/Off for each channel, with operators control.
|}

LFO frequency values are as follows:
*0 – 3.98Hz
*1 – 5.56Hz
*2 – 6.02Hz
*3 – 6.37Hz
*4 – 6.88Hz
*5 – 9.63Hz
*6 – 48.1Hz
*7 – 72.2Hz

Channel numbering:
{|class="wikitable"
!FM Channel
!Binary Code
|-
| CH1
| 001
|-
| CH2
| 010
|-
| CH3
| 101
|-
| CH4
| 110
|}
This strange numbering seems to be due to the fact YM2610 is a YM2610B with 2 removed FM channels (000 and 100).

=Channel registers=

Depending on which channel you want to write to, the {{Chipname|Z80}} ports used are different:
* Channels 1 & 2: Ports 4/5
* Channels 3 & 4: Ports 6/7

{|class="wikitable"
!colspan=4|Address||colspan=4|Data||rowspan=3|
|-
|CH1||CH2||CH3||CH4||CH1||CH2||CH3||CH4
|-
|colspan=2|Port 4||colspan=2|Port 6||colspan=2|Port 5||colspan=2|Port 7
|-
|$A1||$A2||$A1||$A2
|colspan=4|{{8BitRegister|F-Num 1|8}}
|F-Numbers and Block (1/2)
|-
|$A5||$A6||$A5||$A6
|colspan=4|{{8BitRegister|-|2|Block|3|F-Num 2|3}}
|F-Numbers and Block (2/2) (must set this first)
|-
|$B1||$B2||$B1||$B2
|colspan=4|{{8BitRegister|-|2|FB|3|ALGO|3}}
|Feedback (FB) and Algorithm (ALGO)
|-
|$B5||$B6||$B5||$B6
|colspan=4|{{8BitRegister|L|1|R|1|AMS|2|-|1|PMS|3}}
|Left (L)/Right (R) output, AM Sense (AMS), and PM Sense (PMS)
|}

2CH mode additional operator frequencies:
* OP1 frequency is stored in the usual CH2 frequency registers ($A2/$A6)
* write to Z80 ports 4/5

{|class="wikitable"
!colspan=3|Address||colspan=4|Data||rowspan=2|
|-
|OP2||OP3||OP4||colspan="4"|
|-
|$A8||$A9||$AA
|colspan=4|{{8BitRegister|2CH * F-Num 1|8}}
|2CH mode F-Num LSB
|-
|$AC||$AD||$AE
|colspan=4|{{8BitRegister|-|2|2CH * Block|3|2CH * F-Num 2|3}}
|2CH mode F-Num MSB & Block (must set this first)
|}

=Operator registers=
The ranges given for the address represent all of the parameter values. Each channel's operators are laid out as follows:

{|class="wikitable"
! Operator || 1 || 3 || 2 || 4
|-
! Channels 1, 3
| $x1 || $x5 || $x9 || $xD
|-
! Channels 2, 4
| $x2 || $x6 || $xA || $xE
|}

{|class="wikitable"
!colspan=4|Address||colspan=4|Data||rowspan=3|
|-
|CH1||CH2||CH3||CH4||CH1||CH2||CH3||CH4
|-
|colspan=2|Port 4||colspan=2|Port 6||colspan=2|Port 5||colspan=2|Port 7
|-
|colspan=4|$31-$3E
|colspan=4|{{8BitRegister|-|1|DT|3|MUL|4}}
|Detune (DT) and Multiple (MUL)
|-
|colspan=4|$41-$4E
|colspan=4|{{8BitRegister|-|1|Total Level|7|}}
|Total Level (Volume)
|-
|colspan=4|$51-$5E
|colspan=4|{{8BitRegister|KS|2|-|1|AR|5}}
|Key Scale (KS) and Attack Rate (AR)
|-
|colspan=4|$61-$6E
|colspan=4|{{8BitRegister|AM|1|-|2|DR|5}}
|AM On (AM) and Decay Rate (DR)
|-
|colspan=4|$71-$7E
|colspan=4|{{8BitRegister|-|3|SR|5}}
|Sustain Rate (SR)
|-
|colspan=4|$81-$8E
|colspan=4|{{8BitRegister|SL|4|RR|4}}
|Sustain Level (SL) and Release Rate (RR)
|-
|colspan=4|$91-$9E
|colspan=4|{{8BitRegister|-|4|SSG-EG|4}}
|Envelope generator (not to be confused with the [[SSG]] one)
|}

[[Category:Audio system]]

NEO-CMC

2018-06-03T02:22:51Z

Hpman: /* Versions */

{{ChipInfo
|picture=crt_cmc.jpg
|pkg=QFP180
|manu=toshiba
|date=1999 ?
|gates=A lot
|used_on={{PCB|CHAFIO}}...
}}

[[File:brd_cmcnoref.jpg|thumb|"CMC50"]]

Late SNK custom chip used for protection, bankswitching and latching on [[CHAFIO]] [[CHA board]]s.

Descrambling/decryption infos can be found in [[https://github.com/mamedev/mame/blob/master/src/devices/bus/neogeo/prot_cmc.cpp MAME:prot_cmc.c]]

==Versions==
This chip is a TC190G series Toshiba ASIC developed between 1990 and 1994.

The datasheet apparently can't be found anymore for any of the known types:
*TC190G06CF7008
*TC1'''90G06CF7042'''
*TC1'''90G06CF7050'''
(probably others...)

SNK merged the following designs into this chip:
*{{Chipname|NEO-ZMC}}
*{{Chipname|NEO-273}}
*{{Chipname|PRO-CT0}}
*New scrambling system that interlaces M1 + (C* + S1) to decrypt all the graphics ROMs data in real time.

The first released NEO-MVS CHAFIO PCBs came out with the '''042''' version of NEO-CMC, on the following cartridges:
*[[Zupapa!]]
*[[The King of Fighters '99 - Millennium Battle]]
*[[Ganryu]]
*[[Garou - Mark of the Wolves]]
*[[Strikers 1945 Plus]]
*[[Prehistoric Isle 2]]
*[[Metal Slug 3]]
*[[Bang Bead]]
*[[Nightmare in the Dark]]
*[[Sengoku 3]]

On this version only the [[S ROM|S1]] and [[C ROM]]s are encrypted and M1 remains unencrypted. Almost one year later, SNK decided to add one more layer, this time also encrypting M1. This new NEO-CMC chip had the '''050''' reference and was found in the following cartridges:
*[[Jockey Grand Prix]]
*[[The King of Fighters 2000]]
*[[The King of Fighters 2001]]
*[[Metal Slug 4]]
*[[Rage of the Dragons]]
*[[The King of Fighters 2002]]
*[[Matrimelee]]
*[[Pochi and Nyaa]]
*[[Metal Slug 5]]
*[[SNK vs. Capcom - SVC Chaos]]
*[[Samurai Shodown V]]
*[[The King of Fighters 2003]]
*[[Samurai Shodown V Special]]

Until today, nobody has released a cloned chip on the underground market.

==Fix handling==

See [[fix bankswitching]].

==Encryption==

Todo.

=Pinout=
[[File:Neocmc_7050_7042_pinout.png|x600px]]

OpenOffice Draw file: [[File:Neocmc_7050_7042.odg]]

Signals:
*C_e_D[0..15]: C odd data bus
*C_o_D[0..15]: C even data bus
*CX A[0..21]: C1~8 address bus
*Pins 87,88 contains a RC circuit clock driver like in a 8085 with X1 and X2 pinouts
*Pins 89 and 92 are shorted.
[[Category:Chips]]

PROGBK1

2018-06-02T14:02:51Z

Hpman: /* P1 ROM size */

[[File:Progbk1_mvs.jpg|thumb]]

The only non-protected board that can bankswitch and use all [[V ROM]] space. Really common and very useful for homebrew stuff or converts.

Often used as the PROG board in [[Neo Print]] cartridges.

=P ROMs configuration=

[[File:Progbk1p.png|650px]]

==EP ROMs /OE==

{| class="wikitable"
|-
!J1
!J2
|-
|/ROMOE
|/PORTOE
|}

==P2 ROM /CE==

{| class="wikitable"
|-
!J3
!J4
!J5
|-
|A18
|/A18
|GND (default)
|}

==P2 ROM /OE==

{| class="wikitable"
|-
!J6
!J7
!JB1
|-
|/ROMOE
|/PORTOE (default)
|/PORTOE, banks 0 and 1
|}

==P1 ROM /OE==

{| class="wikitable"
|-
!J8
!J9
!J10
!JB2
|-
|/PORTOE
|/PORTOE AND /ROMOE
|/ROMOE (default)
|/PORTOE, banks 2 and 3
|}

==P1 ROM /CE==

{| class="wikitable"
|-
!J11
!J12
!J13
|-
|A18
|/A18
|GND (default)
|}

==P1 ROM size==

{| class="wikitable"
|-
!JB3
!JB4
!Nothing
|-
|A19/NC is /PORTADRS (P1 is 16Mbit)
|A19/NC is BANK0 (because reasons?)
|P1 is 8Mbit
|}

==P2 ROM size==

{| class="wikitable"
|-
!JB5
!JB6
|-
|A20//BYTE is VCC (P2 is 16Mbit or less)
|A20//BYTE is BANK1 (P2 is 32Mbit)
|}

The [[P ROM|P1 ROM]] can be 4Mbit, 8Mbit or 16Mbit (27C400/27C800/27C160).
* ROMs can be halved and mapped to 0x000000~0x0FFFFF or 0x200000~0x2FFFFF.
* If P1 is 4Mbit or 8Mbit, then P2 can contain a bankswitched ROM (same type as P1 plus 27C322). P1 appears in 0x000000~0x0FFFFF. P2 bank appears in 0x200000~0x2FFFFF.

[[Bankswitching]] is done with the LS74. It's not needed if the game isn't banked. Any write to an odd address in the [[68k memory map|0x200000~0x2FFFFF]] range will set the bank.

=V ROMs configuration=

[[File:Progbk1v.png]]

There is a maximum of 4 [[V ROM]]s which can be 8Mbit, 16Mbit or 32Mbit (27C800/27C160) for a maximum total size of 4 * 4MiB = 16MiB.

A 4Mbit ROM can also be used, but only if there's one and only if it's in the last used slot.

The size of the largest V ROM is selected with a pair of jumpers on 6 spots (3 possible choices).

{| class="wikitable"
|-
!Largest V ROM
!Jumper set
|-
|8Mbit (1MiB)
|JV1+JV2
|-
|16Mbit (2MiB)
|JV3+JV4
|-
|32Mbit (4MiB)
|JV5+JV6
|}

This pair of V ROM jumpers effectively choose a set of 2 of the [[PCM]] chip address outputs to input to the LS139, which will enable one out of the 4 V ROMs at a time.

The JV7 to JV14 jumpers need to be set according to the ROM types. If it's less than 32Mbit, the JV7/JV8/JV9/JV10 jumper needs to be set (ground). If it's 32Mbit, the JV11/JV12/JV13/JV14 needs to be set (A20). This is because 32Mbit chips have their /BYTE pin replaced by A20.

=Other=

The LS08 is used to AND the /PORTOEU and /PORTOEL signals to get /PORTOE.

* 4x 1/2/4MiB V ROMs
* 1/2MiB P1 ROM
* 1/2/4MiB P2 ROM
* 2x 512KiB EP1/EP2 ROM
* {{Chipname|PCM}} chip
* LS139, LS08, LS74A

[[Category:Cartridge boards]]

NEO-ZMC

2018-05-27T01:50:03Z

Hpman: syntax

{{ChipInfo
|picture=crt_zmc.jpg
|pkg=SOIC24
|manu=fujitsu
|date=1995 ?
|gates=
|used_on=[[cartridges]]
}}

{{Chipname|Z80}} '''M'''emory '''C'''ontroller. Provides a hardwired 32KiB bank and [[Z80 bankswitching|switchable 16, 8, 4, and 2KiB banks]] arranged as a register file. To save pins, the Z80's upper address lines (A15~A8) are used for data input. The chip's write strobe is [[Z80 port map|port]] address decoded inside the system.

=Pinout=
[[File:Neo-zmc_pinout.png]]

OpenOffice Draw file: [[File:neo-zmc.odg]]

Pins 10, 11, 12 are surely not connected since the addressing scheme doesn't allow mapping over 512KiB.

* SDA0, SDA1, SDA8~15: Z80 address bus
* M1 A11~M1 A18: [[M1 ROM]] address lines
* SDRD0: Decoded write signal from {{Chipname|NEO-D0}} (latch on rising edge)

=Operation=

SDA8~15 is used for the bank number (data), SDA0 and SDA1 for selecting the bank zone.

{|class="wikitable"
!SDA1
!SDA0
!Z80 port
!Bank zone
!Address range
!Size
!Latch size
|-
|0||0||$08||0||$F000~$F7FF||2KiB||8 bits
|-
|0||1||$09||1||$E000~$EFFF||4KiB||7 bits
|-
|1||0||$0A||2||$C000~$DFFF||8KiB||6 bits
|-
|1||1||$0B||3||$8000~$BFFF||16KiB||5 bits
|}

==Details==
[[File:Neo-zmz_operation.png|thumb]]

SDRD0 must be high before configuring banks.

To configure a bank to be accessed (e.g. bank 0 in the $8000~$BFFF range):
* Set SDRD0 low (prepare for new bank configuration, outputs are tri-stated)
* Set SDA0~15 = '''$8003''' (select bank 0 and 16k range size) Why $8003 and not just $0003 ?
* Set SDRD0 high (latch bank, ready to convert inputs to proper output signals)
* Now, when the Z80 reads the '''$8000~BFFF''' range, NEO-ZMC will map this to the M1 ROM zone '''$00000~$03FFF''';

To configure a bank to be accessed (e.g. bank 1 in the $8000~$BFFF range):
* Set SDRD0 low (prepare for new bank configuration, outputs are tri-stated)
* Set SDA0~15 = '''$8103''' (select bank 1 and 16k range size) Why $8103 and not just $0103 ?
* Set SDRD0 high (latch bank, ready to convert inputs to proper output signals)
* Now, when the Z80 reads the '''$8000~BFFF''' range, NEO-ZMC will map this to the M1 ROM zone '''$04000~$07FFF''';

==Logic definition==

Not tested.

<pre>
reg [7:0] WINDOW_0;
reg [6:0] WINDOW_1;
reg [5:0] WINDOW_2;
reg [4:0] WINDOW_3;

assign MA = (!SDA[15]) ? {4'b0000, SDA[14:11]} : // Pass-through
(SDA[15:12] == 4'b1111) ? WINDOW_0 :
(SDA[15:12] == 4'b1110) ? {WINDOW_1, SDA[11]} :
(SDA[15:13] == 3'b110) ? {WINDOW_2, SDA[12:11]} :
{WINDOW_3, SDA[13:11]};

always @(posedge nSDRD0)
begin
case (SDA[1:0])
0: WINDOW_0 <= SDA[15:8];
1: WINDOW_1 <= SDA[14:8];
2: WINDOW_2 <= SDA[13:8];
3: WINDOW_3 <= SDA[12:8];
endcase
end
</pre>

[[Category:Audio system]]
[[Category:Chips]]

YM2610 timers

2018-05-24T22:41:06Z

Hpman: I lied :( (might still not be 100% accurate)

The {{Chipname|YM2610}} provides 2 timers (called A and B), used to time music playback by triggering [[Z80 interrupts]].

The timer A is 10 bits wide, the timer B is only 8 bits wide.

=Ranges=

* Timer A interval: 72*(1024-value)/4M : 18µs to 18432µs (55.56Khz to 54.25Hz)
* Timer B interval: 1152*(256-value)/4M : 288µs to 73.728ms (3.47kHz to 13.56Hz)
* Smaller value=longer interval!

=Registers=

{| class="regdef"
|'''Address (Z80 port 4)'''
|'''Data (Z80 port 5)'''
|-
|$24
|{{8BitRegister|TA counter load bits MSBs|8}}
|-
|$25
|{{8BitRegister|-|6|TA counter load bits LSBs|2}}
|-
|$26
|{{8BitRegister|TB counter load|8}}
|-
|$27
|{{8BitRegister|CSM mode|1|2CH mode|1|Flag reset TB|1|Flag reset TA|1|Enable TB IRQ|1|Enable TA IRQ|1|Load TB|1|Load TA|1}}
|}

=Operation=

The timers are decremented at regular intervals until they reach 0, at which point an interrupt will be generated (if enabled). The timer which caused the interrupt can be known by reading [[YM2610 registers|port $04]].

When a timer expires, it is automatically reloaded. If interrupts are enabled, care must be taken to clear the appropriate flag(s) so that they can be triggered again.

The actual counters aren't accessible, only their load value can be written.

* Writing 0 to the load bits in register $27 will reset the timer counters to zero.
* Writing 1 to the load bits will copy the respective timer load value to the timer counter. This only works when the counter is at zero.

* Flag reset refers to the same flags that are read from port $04
* 2CH mode allows each of FM channel 2 operators to run at their own frequency.
* CSM mode is for automatic key-on for operators of the second FM channel when timer A expires ?

[[Category:Audio system]]
[[Category:Code]]

FM

2018-05-22T23:19:29Z

Hpman:

The FM ('''F'''requency '''M'''odulation) is part of the {{Chipname|YM2610}} sound chip. It provides '''4 channels''', each having their own set of 4 operators, panning and amplitude values. It's the most used way of producing music in games.

=Common registers=

{|class="wikitable"
!Address (Z80 port 4)
!Data (Z80 port 5)
|
|-
|$21
|{{8BitRegister|?|8}}
| Test register. Ignore or set to $00 for normal operation.
|-
|$22
|{{8BitRegister|-|4|On|1|Control|3}}
| LFO control and frequency (see below).
|-
|$28
|{{8BitRegister|Slot (OP4/OP3/OP2/OP1)|4|-|1|Channel|3|}}
| Key On/Off for each channel, with operators control.
|}

LFO frequency values are as follows:
*0 – 3.98Hz
*1 – 5.56Hz
*2 – 6.02Hz
*3 – 6.37Hz
*4 – 6.88Hz
*5 – 9.63Hz
*6 – 48.1Hz
*7 – 72.2Hz

Channel numbering:
{|class="wikitable"
!FM Channel
!Binary Code
|-
| CH1
| 001
|-
| CH2
| 010
|-
| CH3
| 101
|-
| CH4
| 110
|}
This strange numbering seems to be due to the fact YM2610 is a YM2610B with 2 removed FM channels (000 and 100).

=Channel registers=

Depending on which channel you want to write to, the {{Chipname|Z80}} ports used are different:
* Channels 1 & 2: Ports 4/5
* Channels 3 & 4: Ports 6/7

{|class="wikitable"
!colspan=4|Address||colspan=4|Data||rowspan=3|
|-
|CH1||CH2||CH3||CH4||CH1||CH2||CH3||CH4
|-
|colspan=2|Port 4||colspan=2|Port 6||colspan=2|Port 5||colspan=2|Port 7
|-
|$A1||$A2||$A1||$A2
|colspan=4|{{8BitRegister|F-Num 1|8}}
|F-Numbers and Block (1/2)
|-
|$A5||$A6||$A5||$A6
|colspan=4|{{8BitRegister|-|2|Block|3|F-Num 2|3}}
|F-Numbers and Block (2/2) (must set this first)
|-
|$B1||$B2||$B1||$B2
|colspan=4|{{8BitRegister|-|2|FB|3|ALGO|3}}
|Feedback (FB) and Algorithm (ALGO)
|-
|$B5||$B6||$B5||$B6
|colspan=4|{{8BitRegister|L|1|R|1|AMS|2|-|1|PMS|3}}
|Left (L)/Right (R) output, AM Sense (AMS), and PM Sense (PMS)
|}

2CH mode additional operator frequencies:
* OP1 frequency is stored in the usual CH2 frequency registers ($A2/$A6)
* write to Z80 ports 4/5

{|class="wikitable"
!colspan=3|Address||colspan=4|Data||rowspan=2|
|-
|OP2||OP3||OP4||colspan="4"|
|-
|$A8||$A9||$AA
|colspan=4|{{8BitRegister|2CH * F-Num 1|8}}
|2CH mode F-Num LSB
|-
|$AC||$AD||$AE
|colspan=4|{{8BitRegister|-|2|2CH * Block|3|2CH * F-Num 2|3}}
|2CH mode F-Num MSB & Block (must set this first)
|}

=Operator registers=
The ranges given for the address represent all of the parameter values. Each channel's operators are laid out as follows:

{|class="wikitable"
! Operator || 1 || 2 || 3 || 4
|-
! Channels 1, 3
| $x1 || $x5 || $x9 || $xD
|-
! Channels 2, 4
| $x2 || $x6 || $xA || $xE
|}

{|class="wikitable"
!colspan=4|Address||colspan=4|Data||rowspan=3|
|-
|CH1||CH2||CH3||CH4||CH1||CH2||CH3||CH4
|-
|colspan=2|Port 4||colspan=2|Port 6||colspan=2|Port 5||colspan=2|Port 7
|-
|colspan=4|$31-$3E
|colspan=4|{{8BitRegister|-|1|DT|3|MUL|4}}
|Detune (DT) and Multiple (MUL)
|-
|colspan=4|$41-$4E
|colspan=4|{{8BitRegister|-|1|Total Level|7|}}
|Total Level (Volume)
|-
|colspan=4|$51-$5E
|colspan=4|{{8BitRegister|KS|2|-|1|AR|5}}
|Key Scale (KS) and Attack Rate (AR)
|-
|colspan=4|$61-$6E
|colspan=4|{{8BitRegister|AM|1|-|2|DR|5}}
|AM On (AM) and Decay Rate (DR)
|-
|colspan=4|$71-$7E
|colspan=4|{{8BitRegister|-|3|SR|5}}
|Sustain Rate (SR)
|-
|colspan=4|$81-$8E
|colspan=4|{{8BitRegister|SL|4|RR|4}}
|Sustain Level (SL) and Release Rate (RR)
|-
|colspan=4|$91-$9E
|colspan=4|{{8BitRegister|-|4|SSG-EG|4}}
|Envelope generator (not to be confused with the [[SSG]] one)
|}

[[Category:Audio system]]

FM

2018-05-22T23:13:17Z

Hpman:

The FM ('''F'''requency '''M'''odulation) is part of the {{Chipname|YM2610}} sound chip. It provides '''4 channels''', each having their own set of 4 operators, panning and amplitude values. It's the most used way of producing music in games.

=Common registers=

{|class="wikitable"
!Address (Z80 port 4)
!Data (Z80 port 5)
|
|-
|$21
|{{8BitRegister|?|8}}
| Test register. Ignore or set to $00 for normal operation.
|-
|$22
|{{8BitRegister|-|4|On|1|Control|3}}
| LFO control and frequency (see below).
|-
|$28
|{{8BitRegister|Slot (OP4/OP3/OP2/OP1)|4|-|1|Channel|3|}}
| Key On/Off for each channel.
|}

LFO frequency values are as follows:
*0 – 3.98Hz
*1 – 5.56Hz
*2 – 6.02Hz
*3 – 6.37Hz
*4 – 6.88Hz
*5 – 9.63Hz
*6 – 48.1Hz
*7 – 72.2Hz

Channel numbering:
{|class="wikitable"
!FM Channel
!Binary Code
|-
| CH1
| 001
|-
| CH2
| 010
|-
| CH3
| 101
|-
| CH4
| 110
|}
This strange numbering seems to be due to the fact YM2610 is a YM2610B with 2 removed FM channels (000 and 100).

=Channel registers=

Depending on which channel you want to write to, the {{Chipname|Z80}} ports used are different:
* Channels 1 & 2: Ports 4/5
* Channels 3 & 4: Ports 6/7

{|class="wikitable"
!colspan=4|Address||colspan=4|Data||rowspan=3|
|-
|CH1||CH2||CH3||CH4||CH1||CH2||CH3||CH4
|-
|colspan=2|Port 4||colspan=2|Port 6||colspan=2|Port 5||colspan=2|Port 7
|-
|$A1||$A2||$A1||$A2
|colspan=4|{{8BitRegister|F-Num 1|8}}
|F-Numbers and Block (1/2)
|-
|$A5||$A6||$A5||$A6
|colspan=4|{{8BitRegister|-|2|Block|3|F-Num 2|3}}
|F-Numbers and Block (2/2) (must set this first)
|-
|$B1||$B2||$B1||$B2
|colspan=4|{{8BitRegister|-|2|FB|3|ALGO|3}}
|Feedback (FB) and Algorithm (ALGO)
|-
|$B5||$B6||$B5||$B6
|colspan=4|{{8BitRegister|L|1|R|1|AMS|2|-|1|PMS|3}}
|Left (L)/Right (R) output, AM Sense (AMS), and PM Sense (PMS)
|}

2CH mode additional operator frequencies:
* OP1 frequency is stored in the usual CH2 frequency registers ($A2/$A6)
* write to Z80 ports 4/5

{|class="wikitable"
!colspan=3|Address||colspan=4|Data||rowspan=2|
|-
|OP2||OP3||OP4||colspan="4"|
|-
|$A8||$A9||$AA
|colspan=4|{{8BitRegister|2CH * F-Num 1|8}}
|2CH mode F-Num LSB
|-
|$AC||$AD||$AE
|colspan=4|{{8BitRegister|-|2|2CH * Block|3|2CH * F-Num 2|3}}
|2CH mode F-Num MSB & Block (must set this first)
|}

=Operator registers=
The ranges given for the address represent all of the parameter values. Each channel's operators are laid out as follows:

{|class="wikitable"
! Operator || 1 || 2 || 3 || 4
|-
! Channels 1, 3
| $x1 || $x5 || $x9 || $xD
|-
! Channels 2, 4
| $x2 || $x6 || $xA || $xE
|}

{|class="wikitable"
!colspan=4|Address||colspan=4|Data||rowspan=3|
|-
|CH1||CH2||CH3||CH4||CH1||CH2||CH3||CH4
|-
|colspan=2|Port 4||colspan=2|Port 6||colspan=2|Port 5||colspan=2|Port 7
|-
|colspan=4|$31-$3E
|colspan=4|{{8BitRegister|-|1|DT|3|MUL|4}}
|Detune (DT) and Multiple (MUL)
|-
|colspan=4|$41-$4E
|colspan=4|{{8BitRegister|-|1|Total Level|7|}}
|Total Level (Volume)
|-
|colspan=4|$51-$5E
|colspan=4|{{8BitRegister|KS|2|-|1|AR|5}}
|Key Scale (KS) and Attack Rate (AR)
|-
|colspan=4|$61-$6E
|colspan=4|{{8BitRegister|AM|1|-|2|DR|5}}
|AM On (AM) and Decay Rate (DR)
|-
|colspan=4|$71-$7E
|colspan=4|{{8BitRegister|-|3|SR|5}}
|Sustain Rate (SR)
|-
|colspan=4|$81-$8E
|colspan=4|{{8BitRegister|SL|4|RR|4}}
|Sustain Level (SL) and Release Rate (RR)
|-
|colspan=4|$91-$9E
|colspan=4|{{8BitRegister|-|4|SSG-EG|4}}
|Envelope generator (not to be confused with the [[SSG]] one)
|}

[[Category:Audio system]]

VRAM

2018-05-22T09:38:53Z

Hpman: typo

'''VRAM''' stands for Video RAM.

[[File:Aes_cxk5814.jpg|thumb|One of two CXK5814 2KiB RAM chips used for the upper zone of the VRAM ($8000~$87FF) on a AES system]]

The NeoGeo has 68KiB of VRAM split in two: a 64KiB lower zone, and 4KiB higher zone. Contrary to other systems, the VRAM '''does not contain actual graphics'''. It is used to store [[Sprites|sprite]] attributes, the [[fix layer]] tile map and sprite lists for video rendering.

Access to VRAM is always done through 3 [[memory mapped registers]] handled by the [[LSPC]], it does not appear in the [[68k]] address space. Every VRAM address points to a 16-bit word, not a byte.

* {{Reg|REG_VRAMADDR ($3C0000)}} sets the VRAM address for the next read/write operation.
* {{Reg|REG_VRAMRW ($3C0002)}} is the data read or to write.
* {{Reg|REG_VRAMMOD ($3C0004)}} is the signed value automatically added to the VRAM address after a write.

Due to the different access slots used internally for each of the VRAM zones, the address register must be set directly instead of relying on {{Reg|REG_VRAMMOD}} to cross zones ($0000~$7FFF to/from $8000~$FFFF).

==Memory map==
[[File:Vrammap.png|right|frame]]

{| class="regdef"
|'''Start'''
|'''End'''
|'''Words'''
|'''Zone'''
|'''Description'''
|-
|$0000
|$6FFF
|28K
|rowspan=3|Lower
|[[Sprites#SCB1|SCB1]]
|-
|$7000
|$74FF
|rowspan=2|4K
|[[Fix layer|Fix map]]
|-
|$7500
|$7FFF
|[[Fix bankswitching|Extension]]
|-
|$8000
|$81FF
|512
|rowspan=5|Upper
|[[Sprites#SCB2|SCB2]]
|-
|$8200
|$83FF
|512
|[[Sprites#SCB3|SCB3]]
|-
|$8400
|$85FF
|512
|[[Sprites#SCB4|SCB4]]
|-
|$8600
|$867F
|128
|Sprite list for even scanlines
|-
|$8680
|$86FF
|128
|Sprite list for odd scanlines
|-
|$8700
|$87FF
|256
|Unused (free)
|}

==Acces timing==

Even if VRAM can be modified even during active display, some timing restrictions have to be met in order to avoid skipping writes or reading incorrect data. This is because the [[LSPC]] can only provide a limited number of access slots for the CPU between the video rendering steps.

SNK imposed minimum waiting times to always be sure that no read or write operation to VRAM will fail:

* After writing the VRAM address, a read will return valid data after 16 CPU cycles or more (>32mclk).
* After writing the VRAM data, a new address can be set after 16 CPU cycles or more (>32mclk).
* After writing the VRAM data, another write can be done after 12 CPU cycles or more (>24mclk).

Note that these restrictions only concern the VRAM access, and not the other LSPC registers.

[[Overclocking|Overclocked]] systems often produce video glitches because games are trying to access VRAM too quickly.

==Speed==

* Lower (slow) VRAM must be 120ns or less (3mclk).
* Upper (fast) VRAM must be 35ns or less (1mclk).

[[Category:Video system]]

Logo file

2018-05-14T00:27:28Z

Hpman:

[[File:cdzload.png|frame|CDZ default loading screen.]]

[[File:kof96load.png|frame|KOF 96 custom loading screen (LOGO_E.PRG).]]

LOGO files are optional files used to create custom CD loading screens.

The [[system ROM]] automatically loads one of the following files according to the console's [[nationality]] setting, if present in the CD's root:

* LOGO_E.PRG for European nationality.
* LOGO_U.PRG for US nationality.
* LOGO_J.PRG for Japanese nationality.

The files must not be larger than ?? bytes. (KOF '99 uses 16.3KB files)

=File format=

{|class="wikitable"
!Size
!Description
|-
|Word
|Flags
|-
|Longword
|Data type
|-
|Longword
|Data pointer
|-
|Longword
|Data type
|-
|Longword
|Data pointer
|-
|...
|
|-
|Longword
|0xFFFFFFFF terminator
|-
|?
|Data previously pointed to...
|}

The first word represents flags:

* Bit 0: If set, do not draw the default 'NOW LOADING please wait' graphic (see picture top right).
* Bit 1: If set, no progress bar is drawn.
* Bit 2: If set, no animation is drawn.

No other bits seem to be checked by the system ROM.

The rest of the file's contents are "data type - pointer" longword pairs. The type codes used must be sorted in an ascending order. The file is terminated with a $FFFFFFFF type code. The valid type codes are:

*1: Fix tiles
*2: Palette
*3: Tile map
*4: Animation map

The pointer values are absolute, starting from $120000.

==Fix tiles data format==

* Offset (longword). Example: $4000 = start at tile #512
* Size (longword). Example: $2000 = load 256 tiles
* Tile data...

Like the regular [[fix graphics format]], but byteswapped.

==Palette data format==

* Palette number (word).
* 16 words of [[palettes|color data]].

Note: The default progress bar seems to use palette 0, be careful not to overwrite it. Remember that fix tiles can only use the 16 first palettes.

==Map data format==

All values are words.

* Start fix map address ($7102 is good).
* Width in tiles.
* Height in tiles.
* Fix tilemap data as found in [[VRAM]]...

Note: Mapping is done from left to right, top to bottom.

==Animation map data format==

All values are words.

* Start fix map address ($7102 is good).
* Width in tiles.
* Height in tiles.
* Number of frames in animation.
* Animation speed (in frames).
* Fix tilemap data as found in [[VRAM]]...

==Using LOGO files for in-game loading==

By default the system ROM will always use the initial LOGO file during in game loading sequences. It is possible to change this by loading new data over the buffered LOGO file data at $120000. How this gets loaded is not yet confirmed but its suspected that games request the data to be loaded as it would any other data given there is not need for 'LOGO' to be in the file name in this situation. It may also be possible the system ROM looks out for data being loaded into this region before drawing.

The ability to change the default progress bar (handled by the system ROM) is also available. The system ROM places the start address of its code to handle progress bar drawing at $11C80C. This code is then always called via 'MOVEA.L 0x11C80C,A0', 'JSR(A0)'. To use a custom progress bar simply place the start address of your custom progress bar code at $11C80C. Current progress bar state is held at address $10F691. Your code should handle all elements of drawing the progress bar.

It appears games plant their custom progress bar code into the default LOGO file as well as any further files that get loaded to this range. Below is the routine used by Samurai Shodown IV as seen in file 'JL_ST1.PRG' once in RAM. The main game program code places 0x120086 to $11C80C

<syntaxhighlight>
120086 4EF9 0012 4AD0 JMP 0x124AD0
</syntaxhighlight>

<syntaxhighlight>
124AD0 4DF9 003C 0000 LEA 0x3C0000,A6
124AD6 41F9 0012 4B00 LEA 0x124B00,A0
124ADC 1239 0010 F691 MOVE.B 0x10F691,D1
124AE2 0241 00F0 ANDI.W #0xF0,D1
124AE6 D0C1 ADDA.W D1,A0
124AE8 203C 719B A200 MOVE.L #0x719BA200,D0
124AEE 7E0F MOVEQ #0xF,D7
124AF0 1018 MOVE.B (A0)+,D0
124AF2 2C80 MOVE.L D0,(A6)
124AF4 0680 0020 0000 ADDI.L #0x200000,D0
124AFA 51CF FFF4 DBF D7,*-0xA [0xC00422]
124AFE 4E75 RTS
</syntaxhighlight>
[[Category:CD systems]]

Z80 port map

2018-05-14T00:21:27Z

Hpman:

Some infos from [[User:kyuusaku]]

The decode mask for '''reading''' ports is always $0C. The one for writes is indicated for each case.

{| class="regdef"
|'''Address'''
|'''Read'''
|'''Write'''
|'''[[Memory_mapped_registers#Address_decode_masks|Decode mask]]'''
|-
|$00
|
*Read sound code from {{Chipname|68k}}
*Acknowledge [[Z80 interrupts|NMI]]
|Clear sound code from 68k to $00
|rowspan="2"|$0C
|-
|$04-$07
|colspan="2"|[[YM2610]] I/O
|-
|$08
|Set [[Z80 memory map|$F000~$F7FF]] bank
|rowspan="4"|Enable NMIs
|rowspan="4"|$1C
|-
|$09
|Set $E000~$EFFF bank
|-
|$0A
|Set $C000~$DFFF bank
|-
|$0B
|Set $8000~$BFFF bank
|-
|$0C
|See {{Sig|SDRD1|SDRD1}}
|[[68k/Z80_communication|Reply]] to 68k
|$0C
|-
|$18
|See address $08
|Disable NMIs
|$1C
|}

Note that the [[M1 ROM|Z80 ROM]] [[Z80 bankswitching|bank selection]] is done by '''reading''' ports.

SNK used an obscure feature of the Z80: when accessing ports, the entire address bus is set, not only the lower 8 bits.

The banks can then be chosen by putting the bank number in A, the port number in C and doing IN A,(C).
This is handled by {{Chipname|NEO-ZMC}} in cartridges.

Some [[sound driver]]s use port $C0 (and others ?) in their code. Since only SDA2 and SDA3 are used for port decoding, port $C0 maps to a mirror of port $00. It's believed to be a remnant of some development tool.

[[Category:Base system]]
[[Category:Audio system]]

Z80 port map

2018-05-14T00:21:03Z

Hpman:

Some infos from [[User:kyuusaku]]

The decode mask for '''reading''' ports is always $0C. The one for writes is indicated for each case.

{| class="regdef"
|'''Address'''
|'''Read'''
|'''Write'''
|'''[[Memory_mapped_registers#Address_decode_masks|Decode mask]]'''
|-
|$00
|
*Read sound code from {{Chipname|68k}}
*Acknowledge [[Z80 interrupts|NMI]]
|Clear sound code from 68k to $00
|rowspan="2"|$0C
|-
|$04
|colspan="2"|[[YM2610]] I/O
|-
|$08
|Set [[Z80 memory map|$F000~$F7FF]] bank
|rowspan="4"|Enable NMIs
|rowspan="4"|$1C
|-
|$09
|Set $E000~$EFFF bank
|-
|$0A
|Set $C000~$DFFF bank
|-
|$0B
|Set $8000~$BFFF bank
|-
|$0C
|See {{Sig|SDRD1|SDRD1}}
|[[68k/Z80_communication|Reply]] to 68k
|$0C
|-
|$18
|See address $08
|Disable NMIs
|$1C
|}

Note that the [[M1 ROM|Z80 ROM]] [[Z80 bankswitching|bank selection]] is done by '''reading''' ports.

SNK used an obscure feature of the Z80: when accessing ports, the entire address bus is set, not only the lower 8 bits.

The banks can then be chosen by putting the bank number in A, the port number in C and doing IN A,(C).
This is handled by {{Chipname|NEO-ZMC}} in cartridges.

Some [[sound driver]]s use port $C0 (and others ?) in their code. Since only SDA2 and SDA3 are used for port decoding, port $C0 maps to a mirror of port $00. It's believed to be a remnant of some development tool.

[[Category:Base system]]
[[Category:Audio system]]

Eyecatcher

2018-05-08T09:27:11Z

Hpman: /* MAX 330 MEGA */

[[File:Eyecatcher.gif|frame|Original eye-catcher animation.]]

[[File:Eyecatcher_giga.gif|frame|"Giga shock" animation.]]

[[File:Gigapowervliner.gif|frame|Imitated, wonky animation in[[V-Liner]].]].

"Eye-catcher" is the name officially given by SNK to the bootup animation.

=Original animation=

The [[system ROM]] takes care of the animation, but the graphics data for both [[sprites]] and [[fix layer]] must be provided by the game in its {{Chipname|C ROM}}s and {{Chipname|S ROM}}.

==NEO-GEO logo==
The revolving NEO.GEO graphic consists of sprites (the bank of tiles is specified by the byte in the [[68k program header]] at address $115).

The palette is updated on the fly from data stored in the system ROM ($01F03E in {{Chipname|SP-S2}}) to implement the fading effect.

==MAX 330 MEGA==
The "MAX 330 MEGA" & "PRO-GEAR SPEC" text as seen on small or early cartridges (eg. [[Puzzle De Pon!]]) is drawn on the fix layer with tiles from banks 0 and 1. The tilemap is stored in the system ROM ($01F34A in SP-S2). Each line of text is 2 fix tiles in height, and is animated using a 'wipe in' effect from left-to-right.

The tiles used to display each line of text are:

<syntaxhighlight>
static const uint16_t max_330_mega[2][15] =
{
{ 0x05, 0x07, 0x09, 0x0B, 0x0D, 0x0F, 0x15, 0x17, 0x19, 0x1B, 0x1D, 0x1F, 0x5E, 0x60, 0x7D },
{ 0x06, 0x08, 0x0A, 0x0C, 0x0E, 0x14, 0x16, 0x18, 0x1A, 0x1C, 0x1E, 0x40, 0x5F, 0x7C, 0x7E }
};

static const uint16_t pro_gear_spec[2][17] =
{
{ 0x7F, 0x9A, 0x9C, 0x9E, 0xFF, 0xBB, 0xBD, 0xBF, 0xDA, 0xDC, 0xDE, 0xFA, 0xFC, 0x100, 0x102, 0x104, 0x106 },
{ 0x99, 0x9B, 0x9D, 0x9F, 0xBA, 0xBC, 0xBE, 0xD9, 0xDB, 0xDD, 0xDF, 0xFB, 0xFD, 0x101, 0x103, 0x105, 0x107 }
};
</syntaxhighlight>

This can be useful to customize the text in a S ROM.

==SNK logo==
The SNK logo is also drawn on the fix layer, with tiles of bank 2. It is always drawn but actually made visible at the end of the animation by switching its palette.

<syntaxhighlight>
static const uint16_t SNK[3][10] =
{
{ 0x200, 0x201, 0x202, 0x203, 0x204, 0x205, 0x206, 0x207, 0x208, 0x209 },
{ 0x20A, 0x20B, 0x20C, 0x20D, 0x20E, 0x20F, 0x214, 0x215, 0x216, 0x217 },
{ 0x218, 0x219, 0x21A, 0x21B, 0x21C, 0x21D, 0x21E, 0x21F, 0x240, 0x25E }
};
</syntaxhighlight>

The copyright "©" symbol is a single tile ($7B) written to [[VRAM]] adress $7469.

The tiles are set to [[palettes|palette]] 15. The colour 5 is initially black ($0000) and then faded-in through a cycle of progressively brighter blues to a final value of $306E.

==Palettes==
Both the revolving logo and the fix layer text use palette 15.

Here is the *final* data written to palette 15:

<syntaxhighlight>
static const uint16_t eye_catcher_pal[] =
{
0x0000, 0x0fff, 0x0ddd, 0x0aaa, 0x7555, 0x306E, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
};
</syntaxhighlight>

==Customization==
By replacing the tile data for the above tile numbers with alternate text or graphics, it is possible to somewhat customize the eye-catcher screen without requiring a custom eye-catcher routine in the game cartridge itself.

The only caveat is that tile $FF is used in the "PRO-GEAR SPEC" display (see array data above) and is also used as the blank/space character for the entire screen. Thus this tile cannot be changed without replicating it over the entire fix layer.

[[Category:Code]]
[[Category:Video system]]

Rendering logic

2018-05-06T19:54:09Z

Hpman: /* Sprite tiles */

Depending on the chipset, video is generated by 3, 2 or one unique chip:

* 3: [[LSPC-A0]], [[PRO-B0]], [[PRO-C0]] (early)
* 2: [[LSPC2-A2]], [[NEO-B1]] (most common)
* 1: [[NEO-GRC]] (CD systems), [[NEO-GRZ]] (CDZ, MV-1C...)

See [[graphics pipeline]] for an overview of the interconnections between chips and cartridges. See [[Display timing]] for the sync signal's timing.

There are two main parts in generating video:

* An address generator (LSPC), which queries the graphics ROMs in the cartridges according to the data set in [[VRAM]].
* Line buffers, to which pixels can be written in any order from the graphics ROMs data.

=Line buffers=

To render sprites, the NeoGeo uses a pair of line buffers which are each 320 pixels long (a whole scanline). When one is used for rendering, the other one is shifted out for video output. Each new scanline, the buffers are flipped. This can be seen as a kind of double-buffering, allowing pixels to be rendered in any order.

To increase bandwidth, pixels are rendered two by two in sub-pairs: there are actually 4, 160-pixels-long buffers interleaved in an odd/even fashion. This scheme was inherited from the [[Alpha68k]].

The fix layer pixels are rendered in real time over the buffers output.

==Fix tiles==

* Fix pixels are output in time with the pixel clock (6MHz, 4mclk).
* One fix tile line is therefore output in: 8 pixels * 4mclk = 32mclk. No variation.
* The S ROM outputs 8 bits at a time so: 8 bits / 4bpp = 2 pixels at a time.
* S ROM reads needed for one fix tile line: 8 pixels / 2 pixels per read = 4 reads.

Address sequence for one tile line:
{|class="wikitable"
! A4 !! 2H1 !! pixel pair
|-
| 1 || 0 || A
|-
| 1 || 1 || B
|-
| 0 || 0 || C
|-
| 0 || 1 || D
|}

2H1 bypasses the PCK* latchs.

==Sprite tiles==
16mclk = 16 pixels, 8 pixels per read.

* Sprite pixels are rendered two-by-two at 12MHz (2mclk).
* One sprite tile line is therefore output in: 16 pixels / 2 * 2mclk = 16mclk. No variation, even if shrinking is used.
* The C ROM outputs 2 * 16 = 32 bits at a time so: 32 bits / 4bpp = 8 pixels at a time.
* C ROM reads needed for one sprite tile line: 16 pixels / 8 pixels per read = 2 reads.

Address sequence for one tile line:
{|class="wikitable"
! CA4 !! 8-pixel line
|-
| 1 || A
|-
| 0 || B
|}

CA4 bypasses the PCK* latchs.

=Active lists=

The NeoGeo uses a pair of active lists, where the sprites numbers which need to be rendered on the next scanline are written to. As with the line buffers, the active lists are swapped every new scanline so that one is being filled by parsing, the other one is used for rendering.

They are located in the fast VRAM at addresses $8600 and $8680. Each list is 96-entries long.

=Slow VRAM access slots=

Slow VRAM has four 4mclk-long access slots running in sequence with no variations:

# Read sprite map even word
# Read sprite map odd word
# Read fix map
# Read/Write for CPU

=Fast VRAM access slots=

Fast VRAM is more complex and faster. It has 10 access slots with varying widths running in sequence with no variations, which can be seen as 5 parsing slots and 5 rendering slots:

{|class="wikitable"
! Slot # !! Duration !! Description
|-
|1
|2mclk
|rowspan=5|Parsing
|-
|2
|1.5mclk
|-
|3
|1.5mclk
|-
|4
|1.5mclk
|-
|5
|1.5mclk
|-
|6
|2mclk
|Read active list
|-
|7
|1.5mclk
|Read SCB2
|-
|8
|1.5mclk
|Read SCB3
|-
|9
|1.5mclk
|Read SCB4
|-
|10
|1.5mclk
|Read/write for CPU
|}

Yellow are parsing cycles, purple is the active list read, green is SCB* reads for rendering, red is for CPU access:

[[file:timing_gpu1.png]]

The parsing cycles aren't consistent, they depend on the matching of sprites. One cycle will read from SCB3 to test if its Y position matches with the current raster line. If there's a match, the next cycle will be a write to the active list. Otherwise it's another read cycle.

Fast VRAM must be fast enough (45ns) as the shortest slots are 1.5mclk (62.5ns). 1mclk (41.6ns) would be too fast and SRAM was already expensive.

=Sprite parsing=

This is still a draft. The following information shouldn't be considered as correct.

LSPC splits the workload needed to render sprites in two passes: parsing and rendering.

* Parsing for a raster line N is done during line N-2
* Rendering is done during line N-1
* Finally the line is ready for output just at the right time.

During parsing, the Y positions of 381 sprites are read to see if they will be visible on line N. If that's the case, the sprite number is written to the active list currently being filled. This goes on until 381 sprites were parsed, OR the active list is full (96 sprite numbers were written), whichever comes first.

* If sprite #382 is reached, the remaining time is used to fill the active list up to 96 entries with zeros.
* If the active list is full, sprites are still parsed up to #382 but no writes are done to the active list, whatever the matching result.

No matter how many sprites are matched in the scanline, there will always be 381 SCB3 reads and 96 active list writes.

This explains why sprite #0 cannot be used: this is the value used to top-up the active list. If there are less than 96 sprite matches (like most of the time), the sprite #0 will be rendered over and over again until the end of the list is reached.

In the next paragraphs, each character represents a parsing slot: R is an SCB3 read, W is a sprite number write to the active list, F is a filling write to the active list, - is just idle waiting. There are always 1536mclk per line / 16mclk per cycle * 5 slots per cycle = 480 slots.

==Case 1: Not a single sprite match==

Fast VRAM cycles:
<pre>
24M _|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_
Addr 200 | 201 | 202 | 203 | 204 | 681 | 00E | 20E | 40E | 600 | 205 | 206 | 207 | 208 | 209 | 682 | 00F | 20F | 40F
R/W Read Read Read Read Read Read Read Read Read Read
</pre>

381 read slots, 96 fill slots, 3 waiting slots:
<pre>
RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR
RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR
RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR
RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRFFFFFFFFFFFFFFFFFFF
FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF---
</pre>

==Case 2: Some sprites match==

Fast VRAM cycles:
<pre>
24M _|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_
Addr 200 | 201 | 600 | 202 | 203 | 681 | 00E | 20E | 40E | 600 | 601 | 204 | 205 | 602 | 206 | 682 | 00F | 20F | 40F
R/W Read Read Write Read Read Write Read Read Write Read
</pre>

If 17 sprites match: 381 read slots, 17 write slots, 96-17=79 fill slots, 3 waiting slots:
<pre>
RRRRRRWRRRRRRRRRRRRRRRRRRRRWRRRRRRRRRWRRRRRRWRRRRRRWRRRRRWRWRWRRRRRRRRRWRRRRRRRRRRRRRRWRRRRRRRRRRRRR
RRRRRRRRRRRRRRRRRRRWRWRRRRWRWRRRRRRRRRRRRRRRRRRRRRRRRWRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR
RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRWRRRWRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR
RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRFF
FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF---
</pre>

==Case 3: Exactly 96 sprites match==

Fast VRAM cycles:
<pre>
24M _|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_
Addr 200 | 600 | 201 | 601 | 202 | 681 | 00E | 20E | 40E | 600 | 602 | 203 | 204 | 603 | 604 | 682 | 00F | 20F | 40F
R/W Read Write Read Write Read Write Read Read Write Read
</pre>

381 read slots, 96 write slots, 0 fill slots, 3 waiting slots:
<pre>
RRRRRRWRRRRWRRRRRRRWRRRRRWRWRWRRWRRRRRRRRRWRRRRRRWRRWRRRRWRRRRRWRWRWRRRRRWRRRRWRRRRRRRRWRRRRRRWRRRWR
WRWRRWRRRRRRRWRRRWRRRWRRRRWRRRRRRRRWRWRRRRWRWRRRRRRRRRRRRRRRRRRRRRRRRWRRRRRRRRRRRRRRWRRRWRWRWRWRRWRW
RRRRWRRWRRWRRRWRRRWRRWRRRRWRWRWRRWRRRWRWRWRRWRRRRWRRRRRWRRWRRWRRRRRRWRRRWRRRRWRRRRRWRRWRRRWRRRWRRRRR
WRWRWRWRWRWRRRWRRRWRRRRRRRWRRRWRWRRRWRRRRRRRRRWRRRRRRRWRWRWRWRRRRRRRRRRWRRWRRRRRRWRRRRRRRRRRRRRRRRRR
RRRRRRRRRRRRRRRWRRRWRRRRWRRRWRRRRRRRWRRRRRRRWRRRRWRWRRRWRRWRRRRWRRRRRWRRRRRWR---
</pre>

==Case 4: More than 96 sprites match==

Same as case 3, except after 96 "W"s, there are only useless "R"s.

==Rendering==

# Read active list ($8600+ or $8680+) to get sprite #
# Read SCB2 zoom values ($8000+)
# Read SCB3 Y position, height, and chain bit ($8200+)
# Read SCB4 X position ($8400+)

The tile # and its attributes are also read from slow VRAM.

==CPU access to VRAM==

SNK says min. 12 68kclk between writes (so 24mclk). 1 write every 24mclk = 64 per scanline.

CPU access occurs asynchronously with the 68000 bus -> storage in LSPC. If no write is requested, then the slots are occupied by reads, effectively updating one of the two read buffers continuously with the value pointed by the last used VRAM address.

=Buffers control=

==CK signals==
CK1~4 signals are used to clock each of the 4 buffers.

* During rendering, the pulses often go by pair (1+2 or 3+4) to render pixels 2 by 2 if the corresponding WE signal is asserted (opaque pixel). Horizontal shrinking causes pulses to be skipped, so that the buffer's address isn't incremented.
* During output, the pulses are slower and always alternate (1/2/1/2... or 3/4/3/4...) to output even/odd pixels in sequence.

* If the corresponding LD* signal is high, the buffer pointer is incremented (rendering left to right).
* If the corresponding LD* signal is low, the buffer pointer is loaded from the [[P bus]] (X position of sprite, or 0 to start line output).

Inactive during H-blank.

==LD signals==
The LD1~2 signals are synchronous signals used to load the pointers for a buffer pair as two bytes.

Example P bus values for 5 full-width sprites right next to each other, starting at X=0:

<pre>0000,0808,1010,1818,2020</pre>

Example P bus values for 5 full-width sprites right next to each other, starting at X=1 (pixel pairs will be flipped by NEO-ZMC2):

<pre>0100,0908,1110,1918,2120</pre>

As sprite lines '''always''' take 16mclk to render, there's an LD* pulse every 16mclk to set the new starting address (X position) '''except''' for chained sprites. There's also always an unique pulse just before output to reset the pointers to 0.

==WE signals==
WE1~4 signals are used to tell if the pixel should be written to a buffer.

During rendering, the pulses are synchronized to CK signals.

* If the pixel is opaque, there are both pulses at the same time (write pixel).
* If the pixel is transparent, there is a CK pulse but no WE pulse (skip pixel, move to next one).
* If the pixel is skipped for horizontal shrink, there are no pulses at all (do nothing).

During output, the pulses are also synchronized to CK signals and always present. This is used to clear the buffers to the backdrop color for the next rendering cycle.

==SS signals==
The SS1/2 signals enable clearing of buffer pairs, active during output.

==Others==

* TMS0 is used to flip the buffers, related to the lowest bit of the raster counter.
* The rising edge of PCK1 and PCK2 latches fix or sprite pixels from the cart ROMs.

Fix data is read 8 pixels in advance (32mclk, confirms what Charles wrote in mvstech.txt).

[[Category:Video system]]

Development tools

2018-04-08T19:27:19Z

Hpman: DATlib update!

__NOTOC__
==68000==
{|class="wikitable"
!colspan=6 style="background-color:#ccc"|Assemblers
|-
!Name !! Author(s) !! Description !! Platform(s) !! Notes !! Download
|-
| [http://john.ccac.rwth-aachen.de:8000/as/ AS] || Alfred Arnold, et al || Multi-target assembler || (multiple) || Provided as source code and binaries (Windows, DOS) ||  
|-
| [http://sun.hasenbraten.de/vasm/ vasm] || Volker Barthelmann, et al || Multi-target assembler || (multiple) || Provided as source code "official" binaries are for older versions ||  
|-
| JAS || Charles Doty, Paul Lee, Michael Hope || Modified version of AS || Windows || (base AS version unknown; binary is circa 1999/12/30) || [[File:JAS.zip]]
|-
| Maccer || Michael Hope || Pre-processor for AS-series assemblers || (multiple) || Provided as source code and Windows binary ||  
|-
| [http://gendev.spritesmind.net/page-macX.html MaccerX] || Kaneda || Updated version of Maccer || (multiple) || Provided as source code and Windows binary; added support for XGCC (gcc) and comments ||  
|-
| SNASM68K || S.N. Systems || 680x0 assembler || Windows ||   || [http://segaretro.org/SNASM68K SNASM68K at Sega Retro] (Modified version by Nemesis)
|-
!colspan=6 style="background-color:#ccc"|Compilers
|-
!Name !! Author(s) !! Description !! Platform(s) !! Notes !! Download
|-
| NeoDev kit || Fabrice Martinez, Jeff Kurtz, et al || GCC compiler and library || (multiple) ||   || [[File:NeoDev001.zip]]
|-
!colspan=6 style="background-color:#ccc"|Disassemblers
|-
!Name !! Author(s) !! Description !! Platform(s) !! Notes !! Download
|-
| IRA || Tim Ruehsen, ported by Antirad || Intelligent ReAssembler for M680x0 || (multiple) || PC port of an Amiga app; provided as source ("PC") and binary (Windows) || [[File:Ira.zip]]
|-
| unidasm || MAMEdev || Universal Disassembler || (multiple) || Included with the Windows MAME distribution; can be built from source ||  
|}

==Z80==
{|class="wikitable"
!colspan=6 style="background-color:#ccc"|Assemblers
|-
!Name !! Author(s) !! Description !! Platform(s) !! Notes !! Download
|-
| [http://john.ccac.rwth-aachen.de:8000/as/ AS] || Alfred Arnold, et al || Multi-target assembler || (multiple) || Provided as source code and binaries (Windows, DOS) ||  
|-
| [http://sun.hasenbraten.de/vasm/ vasm] || Volker Barthelmann, et al || Multi-target assembler || (multiple) || Provided as source code "official" binaries are for older versions ||  
|-
| [https://github.com/vhelin/wla-dx WLA DX] || Ville Helin, et al || Multi-target assembler || (multiple) || Provided as source code || [http://www.niksula.cs.hut.fi/~tursas/wla/wladx_binaries_20040822.zip WLA-DX 9.2 Win32 binaries]
|-
| [http://www.nongnu.org/z80asm/ z80asm] || Bas Wijnen (and others?) || Z80 assembler || (multiple) || Provided as source code ||  
|-
!colspan=6 style="background-color:#ccc"|Compilers
|-
!Name !! Author(s) !! Description !! Platform(s) !! Notes !! Download
|-
| ZCC || Ken Yap, et al || Z80 development package with C compiler || (multiple) || Provided as source code and binaries (Windows); circa January 1996 || [[File:zcc096.zip]]
|-
| [http://sdcc.sourceforge.net/ SDCC] || Sandeep Dutta, et al || "Small Device C Compiler" || (multiple) || Provided as source code and binaries (various platforms) || [http://sdcc.sourceforge.net/snap.php Snapshot Builds]
|-
| [http://www.z88dk.org/forum/ z88dk] || (many people) || z80 C cross compiler with assembler/linker || (multiple) || Provided as source code and binaries (Windows, Mac) || [http://nightly.z88dk.org/?C=M;O=D Nightly Builds] (Hit escape as soon as you see the links for "latest")
|-
!colspan=6 style="background-color:#ccc"|Disassemblers
|-
!Name !! Author(s) !! Description !! Platform(s) !! Notes !! Download
|-
| DASM || Charles Doty || Z80 disassembler || DOS || Source code and binary included. || [[File:dasmz80.zip]]
|-
| [http://www.inkland.org.uk/dz80/ DZ80] || Inkland || Z80 disassembler || (multiple) || Provided as source code (command line version) and binaries (DOS command line, Windows GUI) ||  
|-
| unidasm || MAMEdev || Universal Disassembler || (multiple) || Included with the Windows MAME distribution; can be built from source ||  
|}

==Source Editors==
There are a lot of source code editors out there... Use whatever you're comfortable with (hopefully one with 68000 and Z80 syntax highlighting).

==Sound and Music==
{|class="wikitable"
|-
!colspan=6 style="background-color:#ccc"|Music Drivers and Tools
|-
!Name !! Author(s) !! Description !! Platform(s) !! Notes !! Download
|-
| [[MVSTracker]] || Ivan Mackintosh || FM tracker || Windows || [http://www.archaic.fr/interviews/interview-jeff-kurtz-repond-a-nos-questions/3/ Z80 driver does not work on hardware] ||  
|-
| [http://gendev.spritesmind.net/page-mvst.html MVSTracker Suite] || Pascal Bosquet, Kaneda || Modified version of MVSTracker || Windows || supports Mega Drive as well. Neo-Geo driver still doesn't work on hardware. ||  
|-
!colspan=6 style="background-color:#ccc"|Sound Editors
|-
!Name !! Author(s) !! Description !! Platform(s) !! Notes !! Download
|-
| [http://www.goldwave.com/release.php GoldWave] || GoldWave Inc. || commercial sound editor || Windows ||   ||  
|-
| [http://www.sonycreativesoftware.com/soundforgesoftware Sound Forge] || Sony || commercial sound editor || Windows, Mac ||   ||  
|-
| [http://audacity.sourceforge.net/ Audacity] || Audacity developers || open-source sound editor || (multiple) ||   ||  
|-
!colspan=6 style="background-color:#ccc"|Sound Encoders
|-
!Name !! Author(s) !! Description !! Platform(s) !! Notes !! Download
|-
| [https://github.com/freem/adpcma ADPCM-A encoder] || freem || Command-line ADPCM-A encoder || (multiple) || Provided as source code and binary (Windows) ||  
|-
| [http://www.smspower.org/forums/11965-VGMLoggingWithOtherEmulators?start=200#66597 ADPCM-B encoder] || ValleyBell and Fred/FRONT || Command-line ADPCM-B encoder || (multiple) || Provided as source code and binary (Windows) || [[File:ADPCM_Encode.zip]]
|-
| [[Neo Sound Builder]] || Jeff Kurtz/Neobitz || GUI V ROM/PCM file creator || Windows || ADPCM-A only || [https://www.facebook.com/Neobitz/photos/a.462349983789893.110879.221161891242038/1093044660720419/?type=3 announcement post]
|}

==Graphics==
{|class="wikitable"
|-
!colspan=6 style="background-color:#ccc"|Graphics Viewers and Editors
|-
!Name !! Author(s) !! Description !! Platform(s) !! Notes !! Download
|-
| [[YY-CHR]] || YY || multi-format tile editor || Windows || FIX files require plugin (YY-CHR.NET only, see below); Sprites need conversion (see tools below) || [http://www.romhacking.net/utils/119/ YY-CHR 0.99]
|-
| NGFX || blastar || Fix, Sprite, TITLE_*.SYS viewer/editor; LOGO_*.SYS viewer || Windows || WIP; not yet released. ||  
|-
!colspan=6 style="background-color:#ccc"|Graphics Converters and Tools
|-
!Name !! Author(s) !! Description !! Platform(s) !! Notes !! Download
|-
| [[DATLib]] graphics tools || HPMAN || Tools used to process and display graphics on Neo-Geo. || Windows || Animator, BuildChar, CharSplit, Framer || [https://www.dropbox.com/s/wqviye5xxzktr6y/DATlib_0.3.rar?dl=0 download]
|-
| [[NGGTool|NeoGeo Graphics ToolSuite]] || evo || Tool to convert between SNES/SFC and Neo-Geo graphics. || Windows || Fix conversion is botched (see page for details) || [http://furrtek.free.fr/noclass/neogeo/nggts.zip NGGTS]
|-
| Sprite graphics converter || IQ || Converts MVS graphics (.c*) to CD graphics (.SPR). || Windows ||   || [http://furrtek.free.fr/noclass/neogeo/gfxmvstocd.zip MVS to CD sprite converter]
|-
| [https://github.com/freem/NeoSpriteConv Neo-Geo Sprite Converter] || freem || Convert 4BPP SMS/GG/WSC graphics to Neo-Geo format. || (multiple) || Provided as source code and binary (Windows) Further work required for converting to Cart (split files by words (2 bytes)) and CD (byteswap file)-usable files. || [http://ajworld.net/neogeodev/utils/neosprconv.zip main download]
|-
| [https://github.com/Kannagi/Neoconvert Neoconvert] || Kannagi || Convert PNG to rom Cx with map, palette and HiColor. || Windows,Linux || || [https://github.com/Kannagi/Neoconvert download]
|-
| [https://github.com/Kannagi/Neoextract Neoextract] || Kannagi || extract rom Cx or s1 to bmp. || Windows,Linux || || [https://github.com/Kannagi/Neoextract download]
|}

==Other Tools==
{|class="wikitable"
|-
!Name !! Author(s) !! Description !! Platform(s) !! Notes !! Download
|-
| MemCardTool || Fabrice Martinez || Memory card manager || Windows ||   || [[File:memcardtool.zip]]
|-
| [https://github.com/freem/romwak ROMwak] || Jeff Kurtz, ported by freem || Binary image manipulation tool || (multiple) || Provided as source code and binary (Windows) ||  
|}

[[Category:Code]]

Scanline effects

2018-03-05T19:12:40Z

Hpman: Not a raster effect

[[File:Sengoku2persp.png|frame|[[Sengoku 2]] changes the shrinking and the position of a scrolling sprite block in its intro to create a mirror and perspective effect.]]

Scanline effects are special tricks using the [[timer interrupt]] to distort [[sprites]] by updating their coordinates or shrink values mid-screen.

These effects can be very CPU consuming as they can be triggered at tight intervals during active display. Consequently, they may have to use tables of precomputed values (constants, or calculated during the VBlank) to be applied fast enough.

[[Neo Turf Masters]] and [[Riding Hero]] heavily rely on this effect to render the playing field.

[[Category:Code]]
[[Category:Video system]]

World Heroes 2 Jet

2018-03-04T02:53:25Z

Hpman:

{{GameInfo|right
|en_title=World Heroes 2 Jet
|jp_title=World Heroes 2 Jet
|jp_title2=ワールドヒーローズ 2 JET
|developer=ADK / SNK
|ngh_id=064
|megcount=178
|mvs_release=yes
|mvs_release_en=y
|mvs_release_jp=y
|mvs_romset=wh2j
|mvs_date=1994
|mvs_pchip=
|mvs_pboard=PROGGSC
|mvs_cboard=CHA256
|aes_release=y
|aes_release_jp=y
|aes_release_en=y
|aes_romset=wh2j
|aes_date=10/06/94
|cd_release=y
|cd_release_jp=y
|cd_release_en=y
|cd_date=11/11/94
}}

<center>
<gallery widths="320" heights="224">
File:wh2jBuild.png|World Heroes 2 Jet build dates.

</gallery>
</center>

[[Category:Games]]

World Heroes 2 Jet

2018-03-04T02:53:02Z

Hpman:

{{GameInfo|right
|en_title=World Heroes 2 Jet
|jp_title=World Heroes 2 Jet
|jp_title2=ワールドヒーローズ 2 JET
|developer=ADK / SNK
|ngh_id=064
|megcount=178
|mvs_release=yes
|mvs_release_en=y
|mvs_release_jp=y
|mvs_romset=wh2j
|mvs_date=1994
|mvs_pchip=
|mvs_pboard=PROGGSC
|mvs_cboard=CHA256
|aes_release=y
|aes_release_jp=y
|aes_release_en=y
|aes_romset=wh2j
|aes_date=10/06/94
|cd_release=y
|cd_release_jp=y
|cd_release_en=y
|cd_date=11/11/94
}}

<center>
<gallery widths="320" heights="224">
File:wh2jBuild.png|World heroes 2 Jet build dates.

</gallery>
</center>

[[Category:Games]]

File:Wh2jBuild.png

2018-03-04T02:49:54Z

Hpman: WH2J build dates

== Summary ==
WH2J build dates
== Licensing ==
{{Non-free game screenshot}}

68k instructions timings

2018-01-22T13:58:56Z

Hpman: /* JMP, JSR, LEA, PEA and MOVEM instructions */

Mirrored information from [[http://oldwww.nvg.ntnu.no/amiga/MC680x0_Sections/mc68000timing.HTML oldwww.nvg.ntnu.no]]

The number of bus '''r'''ead and '''w'''rite cycles are shown in parenthesis as (r/w). Any other cycles are internal.

In the following tables, the headings have the following meanings:
* An : Address register operand
* Dn : Data register operand
* ea : Operand specified by an effective address
* M : Memory effective address operand

To get the real execution time, multiply the total cycles count by 83.33ns ([[Clock|1/12MHz]]). An example is given in each section.

The [[68k interrupts|vertical blank]] lasts exactly 40 lines * 384 pixels * 2 cycles per pixel = 30720 cycles (2.56ms).

See [[optimization]].

=Effective address operand calculation=

This table lists the number of clock periods required to compute an instruction's effective address. It includes fetching of any extension words, the address computation, and fetching of the memory operand.

{|class="wikitable"
!Syntax||Adressing mode||B,W||L
|-
|Dn
|Data register direct
|class="green"|0(0/0)
|class="green"|0(0/0)
|-
|An
|Address register direct
|class="green"|0(0/0)
|class="green"|0(0/0)
|-
|(An)
|Address register indirect
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|-
|(An)+
|Address register indirect, post inc.
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|-
| -(An)
|Address register indirect, pre dec.
|class="yellow"|6(1/0)
|class="orange"|10(2/0)
|-
|d(An)
|Address register indirect, displacement
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|d(An,ix)
|Address register indirect, index
|class="orange"|10(2/0)
|class="red"|14(3/0)
|-
|xxx.w
|Absolute short
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|xxx.l
|Absolute long
|class="orange"|12(3/0)
|class="red"|16(4/0)
|-
|d(PC)
|PC with displacement
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|d(PC,ix)
|PC with index
|class="yellow"|10(2/0)
|class="red"|14(3/0)
|-
|#xxx
|Immediate
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|}

Notes:
* Pre-dec is slower than post-inc
* There are no write cycles involved in processing the effective address
* The size of the index register (ix) does not affect execution time

=Move instructions=

These following two tables indicate the number of clock periods for the move instruction. This data includes instruction fetch, operand reads, and operand writes.

==Byte and word==

Example: '''move.b (a0)+,$10201D''' (Byte (An)+ to xxx.L) takes 20 cycles.

{|class="wikitable"
!  || Dn || An || (An) || (An)+ || -(An) || d(An) || d(An,ix) || xxx.W || xxx.L
|-
!Dn
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|8(1/1)||class="green"|8(1/1)
|class="green"|8(1/1)||class="yellow"|12(2/1)||class="yellow"|14(2/1)||class="yellow"|12(2/1)||class="yellow"|16(3/1)
|-
!An
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|8(1/1)||class="green"|8(1/1)
|class="green"|8(1/1)||class="yellow"|12(2/1)||class="yellow"|14(2/1)||class="yellow"|12(2/1)||class="yellow"|16(3/1)
|-
!(An)
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|12(2/1)||class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|-
!(An)+
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|-
!-(An)
|class="green"|10(2/0)||class="green"|10(2/0)||class="yellow"|14(2/1)||class="yellow"|14(2/1)||class="yellow"|14(2/1)
|class="orange"|18(3/1)||class="orange"|20(4/1)||class="orange"|18(3/1)||class="orange"|22(4/1)
|-
!d(An)
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!d(An,ix)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|18(3/1)||class="orange"|18(3/1)||class="orange"|18(3/1)
|class="orange"|22(4/1)||class="red"|24(4/1)||class="orange"|22(4/1)||class="red"|26(5/1)
|-
!xxx.W
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!xxx.L
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|20(4/1)||class="orange"|20(4/1)||class="orange"|20(4/1)
|class="red"|24(5/1)||class="red"|26(5/1)||class="red"|24(5/1)||class="red"|28(6/1)
|-
!d(PC)
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!d(PC,ix)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|18(3/1)||class="orange"|18(3/1)||class="orange"|18(3/1)
|class="orange"|22(4/1)||class="red"|24(4/1)||class="orange"|22(4/1)||class="red"|26(5/1)
|-
!#xxx
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|}

The size of the index register (ix) does not affect execution time.

==Long==

Example: '''move.l $05012C,4(a1,d0)''' (Long xxx.L to d(An,ix)) takes 34 cycles.

{|class="wikitable"
!  || Dn || An || (An) || (An)+ || -(An) || d(An) || d(An,ix) || xxx.W || xxx.L
|-
!Dn
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|12(1/2)||class="green"|12(1/2)||class="green"|12(1/2)
|class="yellow"|16(2/2)||class="yellow"|18(2/2)||class="yellow"|16(2/2)||class="yellow"|20(3/2)
|-
!An
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|12(1/2)||class="green"|12(1/2)||class="green"|12(1/2)
|class="yellow"|16(2/2)||class="yellow"|18(2/2)||class="yellow"|16(2/2)||class="yellow"|20(3/2)
|-
!(An)
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|-
!(An)+
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|-
!-(An)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|22(3/2)||class="orange"|22(3/2)||class="orange"|22(3/2)
|class="orange"|26(4/2)||class="orange"|28(4/2)||class="orange"|26(4/2)||class="red"|30(5/2)
|-
!d(An)
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(6/2)
|-
!d(An,ix)
|class="yellow"|18(4/0)||class="yellow"|18(4/0)||class="orange"|26(4/2)||class="orange"|26(4/2)||class="orange"|26(4/2)
|class="red"|30(5/2)||class="red"|32(5/2)||class="red"|30(5/2)||class="red"|34(6/2)
|-
!xxx.W
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(6/2)
|-
!xxx.L
|class="yellow"|20(5/0)||class="yellow"|20(5/0)||class="orange"|28(5/2)||class="orange"|28(5/2)||class="orange"|28(5/2)
|class="red"|32(6/2)||class="red"|34(6/2)||class="red"|32(6/2)||class="red"|36(7/2)
|-
!d(PC)
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(5/2)
|-
!d(PC,ix)
|class="yellow"|18(4/0)||class="yellow"|18(4/0)||class="orange"|26(4/2)||class="orange"|26(4/2)||class="orange"|26(4/2)
|class="red"|30(5/2)||class="red"|32(5/2)||class="red"|30(5/2)||class="red"|34(6/2)
|-
!#xxx
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|}

The size of the index register (ix) does not affect execution time.

=Standard instructions=

Example: '''add.w d3,a7''' (Word ea Dn + An) takes 8 cycles.

The number of clock periods shown in this table indicates the time required to perform the operations, store the results and read the next instruction. The total number of clock periods must be added respectively to those of the effective address calculation where indicated (+).

{|class="wikitable"
!  || Size || <ea>,An * || <ea>,Dn || Dn,<M>
|-
!rowspan=2|ADD
|B,W
|class="orange"|8(1/0)+||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
|class="yellow"|6(1/0)+**||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|-
!rowspan=2|AND
|B,W
| - ||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
| - ||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|-
!rowspan=2|CMP
|B,W
|class="yellow"|6(1/0)+||class="green"|4(1/0)+|| -
|-
|L
|class="yellow"|6(1/0)+||class="yellow"|6(1/0)+|| -
|-
!DIVS
| - || - ||class="red"|158(1/0)+|| -
|-
!DIVU
| - || - ||class="red"|140(1/0)+|| -
|-
!rowspan=2|EOR
|B,W
| - ||class="green"|4(1/0) ***||class="orange"|8(1/1) +
|-
|L
| - ||class="orange"|8(1/0) ***||class="red"|12(1/2) +
|-
!MULS
| - || - ||class="red"|70(1/0)+*|| -
|-
!MULU
| - || - ||class="red"|70(1/0)+*|| -
|-
!rowspan=2|OR
|B,W
| - ||class="green"|4(1/0) +**||class="orange"|8(1/1) +
|-
|L
| - ||class="yellow"|6(1/0) +**||class="red"|12(1/2) +
|-
!rowspan=2|SUB
|B,W
|class="orange"|8(1/0)+||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
|class="yellow"|6(1/0)+**||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|}

<syntaxhighlight lang="text">
notes: + Add effective address calculation time
^ Word or long only
* Indicates maximum value
** The base time of six clock periods is increased to eight
if the effective address mode is register direct or
immediate (effective address time should also be added)
*** Only available effective address mode is data register direct

DIVS,DIVU - The divide algorithm used by the MC68000 provides less
than 10% difference between the best and the worst case
timings.
MULS,MULU - The multiply algorithm requires 38+2n clocks where
n is defined as:
MULU: n = the number of ones in the <ea>
MULS: n = concatenate the <ea> with a zero as the LSB;
n is the resultant number of 10 or 01 patterns
in the 17-bit source; i.e., worst case happens
when the source is $5555
</syntaxhighlight>

=Immediate instructions=

The number of clock periods periods shown in this table includes the time to fetch immediate operands, perform the operations, store the results and read the next operation. The total number of clock periods must be added respectively to those of the effective address calculation where indicated (+).

{|class="wikitable"
!  || Size || #,Dn || #,An || #,M
|-
!rowspan=2|ADDI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|ADDQ
|B,W
|class="green"|4(1/0)||class="yellow"|8(1/0)*||class="orange"|12(1/2)+
|-
|L
|class="yellow"|8(1/0)||class="yellow"|8(1/0)||class="orange"|12(1/2)+
|-
!rowspan=2|ANDI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(1/2)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/1)+
|-
!rowspan=2|CMPI
|B,W
|class="green"|8(2/0)|| - ||class="green"|8(2/0)+
|-
|L
|class="orange"|14(3/0)|| - ||class="yellow"|12(3/1)+
|-
!rowspan=2|EORI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!MOVEQ
|L
|class="green"|4(1/0)|| - || -
|-
!rowspan=2|ORI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|SUBI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|SUBQ
|B,W
|class="green"|4(1/0)||class="yellow"|8(1/0)*||class="yellow"|8(1/1)+
|-
|L
|class="yellow"|8(1/0)||class="yellow"|8(1/0)||class="orange"|12(1/2)+
|}

<syntaxhighlight lang="text">
+ Add effective address calculation time
* word only
</syntaxhighlight>

=Single operand instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the single operand
instructions. The number of clock periods and the number of read and write cycles
must be added respectively to those of the effective address calculation
where indicated.

instruction size register memory

CLR byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NBCD byte 6(1/0) 8(1/1) +
NEG byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NEGX byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NOT byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
Scc byte,false 4(1/0) 8(1/1) +
byte,true 6(1/0) 8(1/1) +
TAS # byte 4(1/0) 10(1/1) +
TST byte,word 4(1/0) 4(1/0) +
long 4(1/0) 4(1/0) +

+ add effective address calculation time
# This instruction should never be used on the Amiga as its invisiable
read/write cycle can disrupt system DMA.
</syntaxhighlight>

=Shift and rotate instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the shift and rotate
instructions. The number of clock periods and the number of read and write
cycles must be added respectively to those of the effective address
calculation where indicated.

instruction size register memory

ASR,ASL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
LSR,LSL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
ROR,ROL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
ROXR,ROXL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -

+ add effective address calculation time
n is the shift or rotate count
</syntaxhighlight>

=Bit manipulation instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods required for the bit
manipulation instructions. The number of clock periods and the number of read and
write cycles must be added respectively to those of the effective address
calculation where indicated. Dynamic: register, static: immediate.

instruction size dynamic static
register memory register memory
BCHG byte - 8(1/1) + - 12(2/1) +
long 8(1/0) * - 12(2/0) * -
BCLR byte - 8(1/1) + - 12(2/1) +
long 10(1/0) * - 14(2/0) * -
BSET byte - 8(1/1) + - 12(2/1) +
long 8(1/0) * - 12(2/0) * -
BTST byte - 4(1/0) + - 8(2/0) +
long 6(1/0) - 10(2/0) -

+ add effective address calculation time
* indicates maximum value
</syntaxhighlight>

=Conditional instructions=

{|class="wikitable"
!Mnemonic || Displacement || Branch taken || Not taken
|-
|rowspan=2|Bcc
|byte
|class="yellow"|10(2/0)||class="green"|8(1/0)
|-
|word
|class="yellow"|10(2/0)||class="orange"|12(1/0)
|-
|rowspan=2|BRA
|byte
|class="yellow"|10(2/0)
|
|-
|word
|class="yellow"|10(2/0)
|
|-
|rowspan=2|BSR
|byte
|class="red"|18(2/2)
|
|-
|word
|class="red"|18(2/2)
|
|-
|rowspan=2|DBcc
|cc true
|
|class="orange"|12(2/0)
|-
|cc false
|class="yellow"|10(2/0)
|class="orange"|14(3/0)
|}

=JMP, JSR, LEA, PEA and MOVEM instructions=

<syntaxhighlight lang="text">
This Table indicates the number of clock periods required for the jump,
jump-to-subroutine, load effective address, push effective address and
move multiple registers instructions.

instr size (An) (An)+ -(An) d(An)
JMP - 8(2/0) - - 10(2/0)
JSR - 16(2/2) - - 18(2/2)
LEA - 4(1/0) - - 8(2/0)
PEA - 12(1/2) - - 16(2/2)
MOVEM word 12+4n 12+4n - 16+4n
M->R (3+n/0) (3+n/0) - (4+n/0)
long 12+8n 12+8n - 16+8n
(3+2n/0) (3+2n/0) - (4+2n/0)
MOVEM word 8+4n - 8+4n 12+4n
R->M (2/n) - (2/n) (3/n)
long 8+8n - 8+8n 12+8n
(2/2n) - (2/2n) (3/2n)

instr size d(An,ix)+ xxx.W xxx.L d(PC) d(PC,ix)*
JMP - 14(3/0) 10(2/0) 12(3/0) 10(2/0) 14(3/0)
JSR - 22(2/2) 18(2/2) 20(3/2) 18(2/2) 22(2/2)
LEA - 12(2/0) 8(2/0) 12(3/0) 8(2/0) 12(2/0)
PEA - 20(2/2) 16(2/2) 20(3/2) 16(2/2) 20(2/2)
MOVEM word 18+4n 16+4n 20+4n 16+4n 18+4n
M->R (4+n/0) (4+n/0) (5+n/0) (4+n/0) (4+n/0)
long 18+8n 16+8n 20+8n 16+8n 18+8n
(4+2n/0) (4+2n/0) (5+2n/0) (4+2n/0) (4+2n/0)
MOVEM word 14+4n 12+4n 16+4n - -
R->M (3/n) (3/n) (4/n) - -
long 14+8n 12+8n 16+8n - -
(3/2n) (3/2n) (4/2n) - -

n is the number of registers to move
* is the size of the index register (ix) does not affect the instruction's
execution time
</syntaxhighlight>

=Multi-precision instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the multi-precision
instructions. The number of clock periods includes the time to fetch both
operands, perform the operations, store the results and read the next
instructions.

instruction size op Dn,Dn op M,M

ADDX byte,word 4(1/0) 18(3/1)
long 8(1/0) 30(5/2)
CMPM byte,word - 12(3/0)
long - 20(5/0)
SUBX byte,word 4(1/0) 18(3/1)
long 8(1/0) 30(5/2)
ABCD byte 6(1/0) 18(3/1)
SBCD byte 6(1/0) 18(3/1)
</syntaxhighlight>

=Miscellaneous instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the following
miscellaneous instructions. The number of clock periods and plus the number
of read and write cycles must be added to those of the effective address
calculation where indicated.

instruction size register memory

ANDI to CCR byte 20(3/0) -
ANDI to SR word 20(3/0) -
CHK - 10(1/0) + -
EORI to CCR byte 20(3/0) -
EORI to SR word 20(3/0) -
ORI to CCR byte 20(3/0) -
ORI to SR word 20(3/0) -
MOVE from SR - 6(1/0) 8(1/1)+
MOVE to CCR - 12(1/0) 12(1/0)+
MOVE to SR - 12(1/0) 12(1/0)+
EXG - 6(1/0) -
EXT word 4(1/0) -
long 4(1/0) -
LINK - 16(2/2) -
MOVE from USP - 4(1/0) -
MOVE to USP - 4(1/0) -
NOP - 4(1/0) -
RESET - 132(1/0) -
RTE - 20(5/0) -
RTR - 20(5/0) -
RTS - 16(4/0) -
STOP - 4(0/0) -
SWAP - 4(1/0) -
TRAPV (No Trap) - 4(1/0) -
UNLK - 12(3/0) -

+ add effective address calculation time
</syntaxhighlight>

=Move Peripheral instructions=

<syntaxhighlight lang="text">
instruction size register->memory memory->register

MOVEP word 16(2/2) 16(4/0)
long 24(2/4) 24(6/0)
</syntaxhighlight>

=Exception processing=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for exception processing.
The number of clock periods includes the time for all stacking, the vector
fetch and the fetch of the first two instruction words of the handler routine.

exception periods

address error 50(4/7)
bus error 50(4/7)
CHK instruction (trap taken) 44(5/3)+
Divide by Zero 42(5/3)
illegal instruction 34(4/3)
interrupt 44(5/3)*
privilege violation 34(4/3)
_____
RESET ** 40(6/0)
trace 34(4/3)
TRAP instruction 38(4/3)
TRAPV instruction (trap taken) 34(4/3)

+ add effective address calculation time
* the interrupt acknowledge cycle is assumed to take four
clock periods
_____ ____
** indicates the time from when RESET and HALT are first
sampled as negated to when instruction execution starts
</syntaxhighlight>

[[Category:Base system]]
[[Category:Code]]

68k instructions timings

2018-01-22T13:58:19Z

Hpman: /* JMP, JSR, LEA, PEA and MOVEM instructions */

Mirrored information from [[http://oldwww.nvg.ntnu.no/amiga/MC680x0_Sections/mc68000timing.HTML oldwww.nvg.ntnu.no]]

The number of bus '''r'''ead and '''w'''rite cycles are shown in parenthesis as (r/w). Any other cycles are internal.

In the following tables, the headings have the following meanings:
* An : Address register operand
* Dn : Data register operand
* ea : Operand specified by an effective address
* M : Memory effective address operand

To get the real execution time, multiply the total cycles count by 83.33ns ([[Clock|1/12MHz]]). An example is given in each section.

The [[68k interrupts|vertical blank]] lasts exactly 40 lines * 384 pixels * 2 cycles per pixel = 30720 cycles (2.56ms).

See [[optimization]].

=Effective address operand calculation=

This table lists the number of clock periods required to compute an instruction's effective address. It includes fetching of any extension words, the address computation, and fetching of the memory operand.

{|class="wikitable"
!Syntax||Adressing mode||B,W||L
|-
|Dn
|Data register direct
|class="green"|0(0/0)
|class="green"|0(0/0)
|-
|An
|Address register direct
|class="green"|0(0/0)
|class="green"|0(0/0)
|-
|(An)
|Address register indirect
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|-
|(An)+
|Address register indirect, post inc.
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|-
| -(An)
|Address register indirect, pre dec.
|class="yellow"|6(1/0)
|class="orange"|10(2/0)
|-
|d(An)
|Address register indirect, displacement
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|d(An,ix)
|Address register indirect, index
|class="orange"|10(2/0)
|class="red"|14(3/0)
|-
|xxx.w
|Absolute short
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|xxx.l
|Absolute long
|class="orange"|12(3/0)
|class="red"|16(4/0)
|-
|d(PC)
|PC with displacement
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|d(PC,ix)
|PC with index
|class="yellow"|10(2/0)
|class="red"|14(3/0)
|-
|#xxx
|Immediate
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|}

Notes:
* Pre-dec is slower than post-inc
* There are no write cycles involved in processing the effective address
* The size of the index register (ix) does not affect execution time

=Move instructions=

These following two tables indicate the number of clock periods for the move instruction. This data includes instruction fetch, operand reads, and operand writes.

==Byte and word==

Example: '''move.b (a0)+,$10201D''' (Byte (An)+ to xxx.L) takes 20 cycles.

{|class="wikitable"
!  || Dn || An || (An) || (An)+ || -(An) || d(An) || d(An,ix) || xxx.W || xxx.L
|-
!Dn
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|8(1/1)||class="green"|8(1/1)
|class="green"|8(1/1)||class="yellow"|12(2/1)||class="yellow"|14(2/1)||class="yellow"|12(2/1)||class="yellow"|16(3/1)
|-
!An
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|8(1/1)||class="green"|8(1/1)
|class="green"|8(1/1)||class="yellow"|12(2/1)||class="yellow"|14(2/1)||class="yellow"|12(2/1)||class="yellow"|16(3/1)
|-
!(An)
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|12(2/1)||class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|-
!(An)+
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|-
!-(An)
|class="green"|10(2/0)||class="green"|10(2/0)||class="yellow"|14(2/1)||class="yellow"|14(2/1)||class="yellow"|14(2/1)
|class="orange"|18(3/1)||class="orange"|20(4/1)||class="orange"|18(3/1)||class="orange"|22(4/1)
|-
!d(An)
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!d(An,ix)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|18(3/1)||class="orange"|18(3/1)||class="orange"|18(3/1)
|class="orange"|22(4/1)||class="red"|24(4/1)||class="orange"|22(4/1)||class="red"|26(5/1)
|-
!xxx.W
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!xxx.L
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|20(4/1)||class="orange"|20(4/1)||class="orange"|20(4/1)
|class="red"|24(5/1)||class="red"|26(5/1)||class="red"|24(5/1)||class="red"|28(6/1)
|-
!d(PC)
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!d(PC,ix)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|18(3/1)||class="orange"|18(3/1)||class="orange"|18(3/1)
|class="orange"|22(4/1)||class="red"|24(4/1)||class="orange"|22(4/1)||class="red"|26(5/1)
|-
!#xxx
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|}

The size of the index register (ix) does not affect execution time.

==Long==

Example: '''move.l $05012C,4(a1,d0)''' (Long xxx.L to d(An,ix)) takes 34 cycles.

{|class="wikitable"
!  || Dn || An || (An) || (An)+ || -(An) || d(An) || d(An,ix) || xxx.W || xxx.L
|-
!Dn
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|12(1/2)||class="green"|12(1/2)||class="green"|12(1/2)
|class="yellow"|16(2/2)||class="yellow"|18(2/2)||class="yellow"|16(2/2)||class="yellow"|20(3/2)
|-
!An
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|12(1/2)||class="green"|12(1/2)||class="green"|12(1/2)
|class="yellow"|16(2/2)||class="yellow"|18(2/2)||class="yellow"|16(2/2)||class="yellow"|20(3/2)
|-
!(An)
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|-
!(An)+
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|-
!-(An)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|22(3/2)||class="orange"|22(3/2)||class="orange"|22(3/2)
|class="orange"|26(4/2)||class="orange"|28(4/2)||class="orange"|26(4/2)||class="red"|30(5/2)
|-
!d(An)
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(6/2)
|-
!d(An,ix)
|class="yellow"|18(4/0)||class="yellow"|18(4/0)||class="orange"|26(4/2)||class="orange"|26(4/2)||class="orange"|26(4/2)
|class="red"|30(5/2)||class="red"|32(5/2)||class="red"|30(5/2)||class="red"|34(6/2)
|-
!xxx.W
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(6/2)
|-
!xxx.L
|class="yellow"|20(5/0)||class="yellow"|20(5/0)||class="orange"|28(5/2)||class="orange"|28(5/2)||class="orange"|28(5/2)
|class="red"|32(6/2)||class="red"|34(6/2)||class="red"|32(6/2)||class="red"|36(7/2)
|-
!d(PC)
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(5/2)
|-
!d(PC,ix)
|class="yellow"|18(4/0)||class="yellow"|18(4/0)||class="orange"|26(4/2)||class="orange"|26(4/2)||class="orange"|26(4/2)
|class="red"|30(5/2)||class="red"|32(5/2)||class="red"|30(5/2)||class="red"|34(6/2)
|-
!#xxx
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|}

The size of the index register (ix) does not affect execution time.

=Standard instructions=

Example: '''add.w d3,a7''' (Word ea Dn + An) takes 8 cycles.

The number of clock periods shown in this table indicates the time required to perform the operations, store the results and read the next instruction. The total number of clock periods must be added respectively to those of the effective address calculation where indicated (+).

{|class="wikitable"
!  || Size || <ea>,An * || <ea>,Dn || Dn,<M>
|-
!rowspan=2|ADD
|B,W
|class="orange"|8(1/0)+||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
|class="yellow"|6(1/0)+**||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|-
!rowspan=2|AND
|B,W
| - ||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
| - ||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|-
!rowspan=2|CMP
|B,W
|class="yellow"|6(1/0)+||class="green"|4(1/0)+|| -
|-
|L
|class="yellow"|6(1/0)+||class="yellow"|6(1/0)+|| -
|-
!DIVS
| - || - ||class="red"|158(1/0)+|| -
|-
!DIVU
| - || - ||class="red"|140(1/0)+|| -
|-
!rowspan=2|EOR
|B,W
| - ||class="green"|4(1/0) ***||class="orange"|8(1/1) +
|-
|L
| - ||class="orange"|8(1/0) ***||class="red"|12(1/2) +
|-
!MULS
| - || - ||class="red"|70(1/0)+*|| -
|-
!MULU
| - || - ||class="red"|70(1/0)+*|| -
|-
!rowspan=2|OR
|B,W
| - ||class="green"|4(1/0) +**||class="orange"|8(1/1) +
|-
|L
| - ||class="yellow"|6(1/0) +**||class="red"|12(1/2) +
|-
!rowspan=2|SUB
|B,W
|class="orange"|8(1/0)+||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
|class="yellow"|6(1/0)+**||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|}

<syntaxhighlight lang="text">
notes: + Add effective address calculation time
^ Word or long only
* Indicates maximum value
** The base time of six clock periods is increased to eight
if the effective address mode is register direct or
immediate (effective address time should also be added)
*** Only available effective address mode is data register direct

DIVS,DIVU - The divide algorithm used by the MC68000 provides less
than 10% difference between the best and the worst case
timings.
MULS,MULU - The multiply algorithm requires 38+2n clocks where
n is defined as:
MULU: n = the number of ones in the <ea>
MULS: n = concatenate the <ea> with a zero as the LSB;
n is the resultant number of 10 or 01 patterns
in the 17-bit source; i.e., worst case happens
when the source is $5555
</syntaxhighlight>

=Immediate instructions=

The number of clock periods periods shown in this table includes the time to fetch immediate operands, perform the operations, store the results and read the next operation. The total number of clock periods must be added respectively to those of the effective address calculation where indicated (+).

{|class="wikitable"
!  || Size || #,Dn || #,An || #,M
|-
!rowspan=2|ADDI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|ADDQ
|B,W
|class="green"|4(1/0)||class="yellow"|8(1/0)*||class="orange"|12(1/2)+
|-
|L
|class="yellow"|8(1/0)||class="yellow"|8(1/0)||class="orange"|12(1/2)+
|-
!rowspan=2|ANDI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(1/2)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/1)+
|-
!rowspan=2|CMPI
|B,W
|class="green"|8(2/0)|| - ||class="green"|8(2/0)+
|-
|L
|class="orange"|14(3/0)|| - ||class="yellow"|12(3/1)+
|-
!rowspan=2|EORI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!MOVEQ
|L
|class="green"|4(1/0)|| - || -
|-
!rowspan=2|ORI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|SUBI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|SUBQ
|B,W
|class="green"|4(1/0)||class="yellow"|8(1/0)*||class="yellow"|8(1/1)+
|-
|L
|class="yellow"|8(1/0)||class="yellow"|8(1/0)||class="orange"|12(1/2)+
|}

<syntaxhighlight lang="text">
+ Add effective address calculation time
* word only
</syntaxhighlight>

=Single operand instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the single operand
instructions. The number of clock periods and the number of read and write cycles
must be added respectively to those of the effective address calculation
where indicated.

instruction size register memory

CLR byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NBCD byte 6(1/0) 8(1/1) +
NEG byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NEGX byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NOT byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
Scc byte,false 4(1/0) 8(1/1) +
byte,true 6(1/0) 8(1/1) +
TAS # byte 4(1/0) 10(1/1) +
TST byte,word 4(1/0) 4(1/0) +
long 4(1/0) 4(1/0) +

+ add effective address calculation time
# This instruction should never be used on the Amiga as its invisiable
read/write cycle can disrupt system DMA.
</syntaxhighlight>

=Shift and rotate instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the shift and rotate
instructions. The number of clock periods and the number of read and write
cycles must be added respectively to those of the effective address
calculation where indicated.

instruction size register memory

ASR,ASL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
LSR,LSL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
ROR,ROL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
ROXR,ROXL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -

+ add effective address calculation time
n is the shift or rotate count
</syntaxhighlight>

=Bit manipulation instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods required for the bit
manipulation instructions. The number of clock periods and the number of read and
write cycles must be added respectively to those of the effective address
calculation where indicated. Dynamic: register, static: immediate.

instruction size dynamic static
register memory register memory
BCHG byte - 8(1/1) + - 12(2/1) +
long 8(1/0) * - 12(2/0) * -
BCLR byte - 8(1/1) + - 12(2/1) +
long 10(1/0) * - 14(2/0) * -
BSET byte - 8(1/1) + - 12(2/1) +
long 8(1/0) * - 12(2/0) * -
BTST byte - 4(1/0) + - 8(2/0) +
long 6(1/0) - 10(2/0) -

+ add effective address calculation time
* indicates maximum value
</syntaxhighlight>

=Conditional instructions=

{|class="wikitable"
!Mnemonic || Displacement || Branch taken || Not taken
|-
|rowspan=2|Bcc
|byte
|class="yellow"|10(2/0)||class="green"|8(1/0)
|-
|word
|class="yellow"|10(2/0)||class="orange"|12(1/0)
|-
|rowspan=2|BRA
|byte
|class="yellow"|10(2/0)
|
|-
|word
|class="yellow"|10(2/0)
|
|-
|rowspan=2|BSR
|byte
|class="red"|18(2/2)
|
|-
|word
|class="red"|18(2/2)
|
|-
|rowspan=2|DBcc
|cc true
|
|class="orange"|12(2/0)
|-
|cc false
|class="yellow"|10(2/0)
|class="orange"|14(3/0)
|}

=JMP, JSR, LEA, PEA and MOVEM instructions=

<syntaxhighlight lang="text">
This Table indicates the number of clock periods required for the jump,
jump-to-subroutine, load effective address, push effective address and
move multiple registers instructions.

instr size (An) (An)+ -(An) d(An)
JMP - 8(2/0) - - 10(2/0)
JSR - 16(2/2) - - 18(2/2)
LEA - 4(1/0) - - 8(2/0)
PEA - 12(1/2) - - 16(2/2)
MOVEM word 12+4n 12+4n - 16+4n
M->R (3+n/0) (3+n/0) - (4+n/0)
long 12+8n 12+8n - 16+8n
(3+2n/0) (3+2n/0) - (4+2n/0)
MOVEM word 8+4n - 8+4n 12+4n
R->M (2/n) - (2/n) (3/n)
long 8+8n - 8+8n 12+8n
(2/2n) - (2/2n) (3/2n)

instr size d(An,ix)+ xxx.W xxx.L d(PC) d(PC,ix)*
JMP - 14(3/0) 10(2/0) 12(3/0) 10(2/0) 14(3/0)
JSR - 22(2/2) 18(2/2) 20(3/2) 18(2/2) 22(2/2)
LEA - 12(2/0) 8(2/0) 12(3/0) 8(2/0) 12(2/0)
PEA - 20(2/2) 16(2/2) 20(3/2) 16(2/2) 20(2/2)
MOVEM word 18+4n 16+4n 20+4n 16+4n 18+4n
M->R (4+n/0) (4+n/0) (5+n/0) (4+n/0) (4+n/0)
long 18+8n 16+8n 20+8n 16+8n 18+8n
(4+2n/0) (4+2n/0) (5+2n/0) (4+2n/0) (4+2n/0)
MOVEM word 14+4n 12+4n 16+4n - -
R->M (3/n) (3/n) (4/n) - -
long 14+8n 12+8n 16+8n - -
(3/2n) (3/2n) (4/2n) - -

n is the number of registers to move
* is the size of the index register (ix) does not affect the instruction's
execution time
</syntaxhighlight>

=Multi-precision instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the multi-precision
instructions. The number of clock periods includes the time to fetch both
operands, perform the operations, store the results and read the next
instructions.

instruction size op Dn,Dn op M,M

ADDX byte,word 4(1/0) 18(3/1)
long 8(1/0) 30(5/2)
CMPM byte,word - 12(3/0)
long - 20(5/0)
SUBX byte,word 4(1/0) 18(3/1)
long 8(1/0) 30(5/2)
ABCD byte 6(1/0) 18(3/1)
SBCD byte 6(1/0) 18(3/1)
</syntaxhighlight>

=Miscellaneous instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the following
miscellaneous instructions. The number of clock periods and plus the number
of read and write cycles must be added to those of the effective address
calculation where indicated.

instruction size register memory

ANDI to CCR byte 20(3/0) -
ANDI to SR word 20(3/0) -
CHK - 10(1/0) + -
EORI to CCR byte 20(3/0) -
EORI to SR word 20(3/0) -
ORI to CCR byte 20(3/0) -
ORI to SR word 20(3/0) -
MOVE from SR - 6(1/0) 8(1/1)+
MOVE to CCR - 12(1/0) 12(1/0)+
MOVE to SR - 12(1/0) 12(1/0)+
EXG - 6(1/0) -
EXT word 4(1/0) -
long 4(1/0) -
LINK - 16(2/2) -
MOVE from USP - 4(1/0) -
MOVE to USP - 4(1/0) -
NOP - 4(1/0) -
RESET - 132(1/0) -
RTE - 20(5/0) -
RTR - 20(5/0) -
RTS - 16(4/0) -
STOP - 4(0/0) -
SWAP - 4(1/0) -
TRAPV (No Trap) - 4(1/0) -
UNLK - 12(3/0) -

+ add effective address calculation time
</syntaxhighlight>

=Move Peripheral instructions=

<syntaxhighlight lang="text">
instruction size register->memory memory->register

MOVEP word 16(2/2) 16(4/0)
long 24(2/4) 24(6/0)
</syntaxhighlight>

=Exception processing=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for exception processing.
The number of clock periods includes the time for all stacking, the vector
fetch and the fetch of the first two instruction words of the handler routine.

exception periods

address error 50(4/7)
bus error 50(4/7)
CHK instruction (trap taken) 44(5/3)+
Divide by Zero 42(5/3)
illegal instruction 34(4/3)
interrupt 44(5/3)*
privilege violation 34(4/3)
_____
RESET ** 40(6/0)
trace 34(4/3)
TRAP instruction 38(4/3)
TRAPV instruction (trap taken) 34(4/3)

+ add effective address calculation time
* the interrupt acknowledge cycle is assumed to take four
clock periods
_____ ____
** indicates the time from when RESET and HALT are first
sampled as negated to when instruction execution starts
</syntaxhighlight>

[[Category:Base system]]
[[Category:Code]]

68k instructions timings

2018-01-20T07:17:08Z

Hpman: /* Exception processing */

Mirrored information from [[http://oldwww.nvg.ntnu.no/amiga/MC680x0_Sections/mc68000timing.HTML oldwww.nvg.ntnu.no]]

The number of bus '''r'''ead and '''w'''rite cycles are shown in parenthesis as (r/w). Any other cycles are internal.

In the following tables, the headings have the following meanings:
* An : Address register operand
* Dn : Data register operand
* ea : Operand specified by an effective address
* M : Memory effective address operand

To get the real execution time, multiply the total cycles count by 83.33ns ([[Clock|1/12MHz]]). An example is given in each section.

The [[68k interrupts|vertical blank]] lasts exactly 40 lines * 384 pixels * 2 cycles per pixel = 30720 cycles (2.56ms).

See [[optimization]].

=Effective address operand calculation=

This table lists the number of clock periods required to compute an instruction's effective address. It includes fetching of any extension words, the address computation, and fetching of the memory operand.

{|class="wikitable"
!Syntax||Adressing mode||B,W||L
|-
|Dn
|Data register direct
|class="green"|0(0/0)
|class="green"|0(0/0)
|-
|An
|Address register direct
|class="green"|0(0/0)
|class="green"|0(0/0)
|-
|(An)
|Address register indirect
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|-
|(An)+
|Address register indirect, post inc.
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|-
| -(An)
|Address register indirect, pre dec.
|class="yellow"|6(1/0)
|class="orange"|10(2/0)
|-
|d(An)
|Address register indirect, displacement
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|d(An,ix)
|Address register indirect, index
|class="orange"|10(2/0)
|class="red"|14(3/0)
|-
|xxx.w
|Absolute short
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|xxx.l
|Absolute long
|class="orange"|12(3/0)
|class="red"|16(4/0)
|-
|d(PC)
|PC with displacement
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|d(PC,ix)
|PC with index
|class="yellow"|10(2/0)
|class="red"|14(3/0)
|-
|#xxx
|Immediate
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|}

Notes:
* Pre-dec is slower than post-inc
* There are no write cycles involved in processing the effective address
* The size of the index register (ix) does not affect execution time

=Move instructions=

These following two tables indicate the number of clock periods for the move instruction. This data includes instruction fetch, operand reads, and operand writes.

==Byte and word==

Example: '''move.b (a0)+,$10201D''' (Byte (An)+ to xxx.L) takes 20 cycles.

{|class="wikitable"
!  || Dn || An || (An) || (An)+ || -(An) || d(An) || d(An,ix) || xxx.W || xxx.L
|-
!Dn
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|8(1/1)||class="green"|8(1/1)
|class="green"|8(1/1)||class="yellow"|12(2/1)||class="yellow"|14(2/1)||class="yellow"|12(2/1)||class="yellow"|16(3/1)
|-
!An
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|8(1/1)||class="green"|8(1/1)
|class="green"|8(1/1)||class="yellow"|12(2/1)||class="yellow"|14(2/1)||class="yellow"|12(2/1)||class="yellow"|16(3/1)
|-
!(An)
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|12(2/1)||class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|-
!(An)+
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|-
!-(An)
|class="green"|10(2/0)||class="green"|10(2/0)||class="yellow"|14(2/1)||class="yellow"|14(2/1)||class="yellow"|14(2/1)
|class="orange"|18(3/1)||class="orange"|20(4/1)||class="orange"|18(3/1)||class="orange"|22(4/1)
|-
!d(An)
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!d(An,ix)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|18(3/1)||class="orange"|18(3/1)||class="orange"|18(3/1)
|class="orange"|22(4/1)||class="red"|24(4/1)||class="orange"|22(4/1)||class="red"|26(5/1)
|-
!xxx.W
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!xxx.L
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|20(4/1)||class="orange"|20(4/1)||class="orange"|20(4/1)
|class="red"|24(5/1)||class="red"|26(5/1)||class="red"|24(5/1)||class="red"|28(6/1)
|-
!d(PC)
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!d(PC,ix)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|18(3/1)||class="orange"|18(3/1)||class="orange"|18(3/1)
|class="orange"|22(4/1)||class="red"|24(4/1)||class="orange"|22(4/1)||class="red"|26(5/1)
|-
!#xxx
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|}

The size of the index register (ix) does not affect execution time.

==Long==

Example: '''move.l $05012C,4(a1,d0)''' (Long xxx.L to d(An,ix)) takes 34 cycles.

{|class="wikitable"
!  || Dn || An || (An) || (An)+ || -(An) || d(An) || d(An,ix) || xxx.W || xxx.L
|-
!Dn
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|12(1/2)||class="green"|12(1/2)||class="green"|12(1/2)
|class="yellow"|16(2/2)||class="yellow"|18(2/2)||class="yellow"|16(2/2)||class="yellow"|20(3/2)
|-
!An
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|12(1/2)||class="green"|12(1/2)||class="green"|12(1/2)
|class="yellow"|16(2/2)||class="yellow"|18(2/2)||class="yellow"|16(2/2)||class="yellow"|20(3/2)
|-
!(An)
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|-
!(An)+
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|-
!-(An)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|22(3/2)||class="orange"|22(3/2)||class="orange"|22(3/2)
|class="orange"|26(4/2)||class="orange"|28(4/2)||class="orange"|26(4/2)||class="red"|30(5/2)
|-
!d(An)
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(6/2)
|-
!d(An,ix)
|class="yellow"|18(4/0)||class="yellow"|18(4/0)||class="orange"|26(4/2)||class="orange"|26(4/2)||class="orange"|26(4/2)
|class="red"|30(5/2)||class="red"|32(5/2)||class="red"|30(5/2)||class="red"|34(6/2)
|-
!xxx.W
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(6/2)
|-
!xxx.L
|class="yellow"|20(5/0)||class="yellow"|20(5/0)||class="orange"|28(5/2)||class="orange"|28(5/2)||class="orange"|28(5/2)
|class="red"|32(6/2)||class="red"|34(6/2)||class="red"|32(6/2)||class="red"|36(7/2)
|-
!d(PC)
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(5/2)
|-
!d(PC,ix)
|class="yellow"|18(4/0)||class="yellow"|18(4/0)||class="orange"|26(4/2)||class="orange"|26(4/2)||class="orange"|26(4/2)
|class="red"|30(5/2)||class="red"|32(5/2)||class="red"|30(5/2)||class="red"|34(6/2)
|-
!#xxx
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|}

The size of the index register (ix) does not affect execution time.

=Standard instructions=

Example: '''add.w d3,a7''' (Word ea Dn + An) takes 8 cycles.

The number of clock periods shown in this table indicates the time required to perform the operations, store the results and read the next instruction. The total number of clock periods must be added respectively to those of the effective address calculation where indicated (+).

{|class="wikitable"
!  || Size || <ea>,An * || <ea>,Dn || Dn,<M>
|-
!rowspan=2|ADD
|B,W
|class="orange"|8(1/0)+||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
|class="yellow"|6(1/0)+**||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|-
!rowspan=2|AND
|B,W
| - ||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
| - ||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|-
!rowspan=2|CMP
|B,W
|class="yellow"|6(1/0)+||class="green"|4(1/0)+|| -
|-
|L
|class="yellow"|6(1/0)+||class="yellow"|6(1/0)+|| -
|-
!DIVS
| - || - ||class="red"|158(1/0)+|| -
|-
!DIVU
| - || - ||class="red"|140(1/0)+|| -
|-
!rowspan=2|EOR
|B,W
| - ||class="green"|4(1/0) ***||class="orange"|8(1/1) +
|-
|L
| - ||class="orange"|8(1/0) ***||class="red"|12(1/2) +
|-
!MULS
| - || - ||class="red"|70(1/0)+*|| -
|-
!MULU
| - || - ||class="red"|70(1/0)+*|| -
|-
!rowspan=2|OR
|B,W
| - ||class="green"|4(1/0) +**||class="orange"|8(1/1) +
|-
|L
| - ||class="yellow"|6(1/0) +**||class="red"|12(1/2) +
|-
!rowspan=2|SUB
|B,W
|class="orange"|8(1/0)+||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
|class="yellow"|6(1/0)+**||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|}

<syntaxhighlight lang="text">
notes: + Add effective address calculation time
^ Word or long only
* Indicates maximum value
** The base time of six clock periods is increased to eight
if the effective address mode is register direct or
immediate (effective address time should also be added)
*** Only available effective address mode is data register direct

DIVS,DIVU - The divide algorithm used by the MC68000 provides less
than 10% difference between the best and the worst case
timings.
MULS,MULU - The multiply algorithm requires 38+2n clocks where
n is defined as:
MULU: n = the number of ones in the <ea>
MULS: n = concatenate the <ea> with a zero as the LSB;
n is the resultant number of 10 or 01 patterns
in the 17-bit source; i.e., worst case happens
when the source is $5555
</syntaxhighlight>

=Immediate instructions=

The number of clock periods periods shown in this table includes the time to fetch immediate operands, perform the operations, store the results and read the next operation. The total number of clock periods must be added respectively to those of the effective address calculation where indicated (+).

{|class="wikitable"
!  || Size || #,Dn || #,An || #,M
|-
!rowspan=2|ADDI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|ADDQ
|B,W
|class="green"|4(1/0)||class="yellow"|8(1/0)*||class="orange"|12(1/2)+
|-
|L
|class="yellow"|8(1/0)||class="yellow"|8(1/0)||class="orange"|12(1/2)+
|-
!rowspan=2|ANDI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(1/2)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/1)+
|-
!rowspan=2|CMPI
|B,W
|class="green"|8(2/0)|| - ||class="green"|8(2/0)+
|-
|L
|class="orange"|14(3/0)|| - ||class="yellow"|12(3/1)+
|-
!rowspan=2|EORI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!MOVEQ
|L
|class="green"|4(1/0)|| - || -
|-
!rowspan=2|ORI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|SUBI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|SUBQ
|B,W
|class="green"|4(1/0)||class="yellow"|8(1/0)*||class="yellow"|8(1/1)+
|-
|L
|class="yellow"|8(1/0)||class="yellow"|8(1/0)||class="orange"|12(1/2)+
|}

<syntaxhighlight lang="text">
+ Add effective address calculation time
* word only
</syntaxhighlight>

=Single operand instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the single operand
instructions. The number of clock periods and the number of read and write cycles
must be added respectively to those of the effective address calculation
where indicated.

instruction size register memory

CLR byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NBCD byte 6(1/0) 8(1/1) +
NEG byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NEGX byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NOT byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
Scc byte,false 4(1/0) 8(1/1) +
byte,true 6(1/0) 8(1/1) +
TAS # byte 4(1/0) 10(1/1) +
TST byte,word 4(1/0) 4(1/0) +
long 4(1/0) 4(1/0) +

+ add effective address calculation time
# This instruction should never be used on the Amiga as its invisiable
read/write cycle can disrupt system DMA.
</syntaxhighlight>

=Shift and rotate instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the shift and rotate
instructions. The number of clock periods and the number of read and write
cycles must be added respectively to those of the effective address
calculation where indicated.

instruction size register memory

ASR,ASL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
LSR,LSL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
ROR,ROL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
ROXR,ROXL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -

+ add effective address calculation time
n is the shift or rotate count
</syntaxhighlight>

=Bit manipulation instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods required for the bit
manipulation instructions. The number of clock periods and the number of read and
write cycles must be added respectively to those of the effective address
calculation where indicated. Dynamic: register, static: immediate.

instruction size dynamic static
register memory register memory
BCHG byte - 8(1/1) + - 12(2/1) +
long 8(1/0) * - 12(2/0) * -
BCLR byte - 8(1/1) + - 12(2/1) +
long 10(1/0) * - 14(2/0) * -
BSET byte - 8(1/1) + - 12(2/1) +
long 8(1/0) * - 12(2/0) * -
BTST byte - 4(1/0) + - 8(2/0) +
long 6(1/0) - 10(2/0) -

+ add effective address calculation time
* indicates maximum value
</syntaxhighlight>

=Conditional instructions=

{|class="wikitable"
!Mnemonic || Displacement || Branch taken || Not taken
|-
|rowspan=2|Bcc
|byte
|class="yellow"|10(2/0)||class="green"|8(1/0)
|-
|word
|class="yellow"|10(2/0)||class="orange"|12(1/0)
|-
|rowspan=2|BRA
|byte
|class="yellow"|10(2/0)
|
|-
|word
|class="yellow"|10(2/0)
|
|-
|rowspan=2|BSR
|byte
|class="red"|18(2/2)
|
|-
|word
|class="red"|18(2/2)
|
|-
|rowspan=2|DBcc
|cc true
|
|class="orange"|12(2/0)
|-
|cc false
|class="yellow"|10(2/0)
|class="orange"|14(3/0)
|}

=JMP, JSR, LEA, PEA and MOVEM instructions=

<syntaxhighlight lang="text">
This Table indicates the number of clock periods required for the jump,
jump-to-subroutine, load effective address, push effective address and
move multiple registers instructions.

instr size (An) (An)+ -(An) d(An)
JMP - 8(2/0) - - 10(2/0)
JSR - 16(2/2) - - 18(2/2)
LEA - 4(1/0) - - 8(2/0)
PEA - 12(1/2) - - 16(2/2)
MOVEM word 12+4n 12+4n - 16+4n
M->R (3+n/0) (3+n/0) - (4+n/0)
long 12+8n 12+8n - 16+8n
(3+2n/0) (3+2n/0) - (4+2n/0)
MOVEM word 8+4n - 8+4n 12+4n
R->M (2/n) - (2/n) (3/n)
long 8+8n - 8+8n 12+8n
(2/2n) - (2/2n) (3/2n)

instr size d(An,ix)+ xxx.W xxx.L d(PC) d(PC,ix)*
JMP - 14(3/0) 10(2/0) 12(3/0) 10(2/0) 14(3/0)
JSR - 22(2/2) 18(2/2) 20(3/2) 18(2/2) 22(2/2)
LEA - 12(2/0) 8(2/0) 12(3/0) 8(2/0) 12(2/0)
PEA - 20(2/2) 16(2/2) 20(3/2) 16(2/2) 20(2/2)
MOVEM word 18+4n 16+4n 20+4n 16+4n 18+4n
M->R (4+n/0) (4+n/0) (5+n/0) (4+n/0) (4+n/0)
long 18+8n 16+8n 20+8n 16+8n 18+8n
(4+2n/0) (4+2n/0) (5+2n/0) (4+2n/0) (4+2n/0)
MOVEM word 14+4n 12+4n 16+4n - -
R->M (3/n) (3/n) (4/n) - -
long 14+8n 12+8n 16+8n - -
(3/2n) (3/2n) (4/2n) - -

n is the number of registers to move
* is the size of the index register (ix) does not affect the instruction's
execution time
</syntaxhighlight>

=Multi-precision instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the multi-precision
instructions. The number of clock periods includes the time to fetch both
operands, perform the operations, store the results and read the next
instructions.

instruction size op Dn,Dn op M,M

ADDX byte,word 4(1/0) 18(3/1)
long 8(1/0) 30(5/2)
CMPM byte,word - 12(3/0)
long - 20(5/0)
SUBX byte,word 4(1/0) 18(3/1)
long 8(1/0) 30(5/2)
ABCD byte 6(1/0) 18(3/1)
SBCD byte 6(1/0) 18(3/1)
</syntaxhighlight>

=Miscellaneous instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the following
miscellaneous instructions. The number of clock periods and plus the number
of read and write cycles must be added to those of the effective address
calculation where indicated.

instruction size register memory

ANDI to CCR byte 20(3/0) -
ANDI to SR word 20(3/0) -
CHK - 10(1/0) + -
EORI to CCR byte 20(3/0) -
EORI to SR word 20(3/0) -
ORI to CCR byte 20(3/0) -
ORI to SR word 20(3/0) -
MOVE from SR - 6(1/0) 8(1/1)+
MOVE to CCR - 12(1/0) 12(1/0)+
MOVE to SR - 12(1/0) 12(1/0)+
EXG - 6(1/0) -
EXT word 4(1/0) -
long 4(1/0) -
LINK - 16(2/2) -
MOVE from USP - 4(1/0) -
MOVE to USP - 4(1/0) -
NOP - 4(1/0) -
RESET - 132(1/0) -
RTE - 20(5/0) -
RTR - 20(5/0) -
RTS - 16(4/0) -
STOP - 4(0/0) -
SWAP - 4(1/0) -
TRAPV (No Trap) - 4(1/0) -
UNLK - 12(3/0) -

+ add effective address calculation time
</syntaxhighlight>

=Move Peripheral instructions=

<syntaxhighlight lang="text">
instruction size register->memory memory->register

MOVEP word 16(2/2) 16(4/0)
long 24(2/4) 24(6/0)
</syntaxhighlight>

=Exception processing=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for exception processing.
The number of clock periods includes the time for all stacking, the vector
fetch and the fetch of the first two instruction words of the handler routine.

exception periods

address error 50(4/7)
bus error 50(4/7)
CHK instruction (trap taken) 44(5/3)+
Divide by Zero 42(5/3)
illegal instruction 34(4/3)
interrupt 44(5/3)*
privilege violation 34(4/3)
_____
RESET ** 40(6/0)
trace 34(4/3)
TRAP instruction 38(4/3)
TRAPV instruction (trap taken) 34(4/3)

+ add effective address calculation time
* the interrupt acknowledge cycle is assumed to take four
clock periods
_____ ____
** indicates the time from when RESET and HALT are first
sampled as negated to when instruction execution starts
</syntaxhighlight>

[[Category:Base system]]
[[Category:Code]]

68k instructions timings

2018-01-20T07:11:53Z

Hpman: /* Single operand instructions */

Mirrored information from [[http://oldwww.nvg.ntnu.no/amiga/MC680x0_Sections/mc68000timing.HTML oldwww.nvg.ntnu.no]]

The number of bus '''r'''ead and '''w'''rite cycles are shown in parenthesis as (r/w). Any other cycles are internal.

In the following tables, the headings have the following meanings:
* An : Address register operand
* Dn : Data register operand
* ea : Operand specified by an effective address
* M : Memory effective address operand

To get the real execution time, multiply the total cycles count by 83.33ns ([[Clock|1/12MHz]]). An example is given in each section.

The [[68k interrupts|vertical blank]] lasts exactly 40 lines * 384 pixels * 2 cycles per pixel = 30720 cycles (2.56ms).

See [[optimization]].

=Effective address operand calculation=

This table lists the number of clock periods required to compute an instruction's effective address. It includes fetching of any extension words, the address computation, and fetching of the memory operand.

{|class="wikitable"
!Syntax||Adressing mode||B,W||L
|-
|Dn
|Data register direct
|class="green"|0(0/0)
|class="green"|0(0/0)
|-
|An
|Address register direct
|class="green"|0(0/0)
|class="green"|0(0/0)
|-
|(An)
|Address register indirect
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|-
|(An)+
|Address register indirect, post inc.
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|-
| -(An)
|Address register indirect, pre dec.
|class="yellow"|6(1/0)
|class="orange"|10(2/0)
|-
|d(An)
|Address register indirect, displacement
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|d(An,ix)
|Address register indirect, index
|class="orange"|10(2/0)
|class="red"|14(3/0)
|-
|xxx.w
|Absolute short
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|xxx.l
|Absolute long
|class="orange"|12(3/0)
|class="red"|16(4/0)
|-
|d(PC)
|PC with displacement
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|d(PC,ix)
|PC with index
|class="yellow"|10(2/0)
|class="red"|14(3/0)
|-
|#xxx
|Immediate
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|}

Notes:
* Pre-dec is slower than post-inc
* There are no write cycles involved in processing the effective address
* The size of the index register (ix) does not affect execution time

=Move instructions=

These following two tables indicate the number of clock periods for the move instruction. This data includes instruction fetch, operand reads, and operand writes.

==Byte and word==

Example: '''move.b (a0)+,$10201D''' (Byte (An)+ to xxx.L) takes 20 cycles.

{|class="wikitable"
!  || Dn || An || (An) || (An)+ || -(An) || d(An) || d(An,ix) || xxx.W || xxx.L
|-
!Dn
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|8(1/1)||class="green"|8(1/1)
|class="green"|8(1/1)||class="yellow"|12(2/1)||class="yellow"|14(2/1)||class="yellow"|12(2/1)||class="yellow"|16(3/1)
|-
!An
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|8(1/1)||class="green"|8(1/1)
|class="green"|8(1/1)||class="yellow"|12(2/1)||class="yellow"|14(2/1)||class="yellow"|12(2/1)||class="yellow"|16(3/1)
|-
!(An)
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|12(2/1)||class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|-
!(An)+
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|-
!-(An)
|class="green"|10(2/0)||class="green"|10(2/0)||class="yellow"|14(2/1)||class="yellow"|14(2/1)||class="yellow"|14(2/1)
|class="orange"|18(3/1)||class="orange"|20(4/1)||class="orange"|18(3/1)||class="orange"|22(4/1)
|-
!d(An)
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!d(An,ix)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|18(3/1)||class="orange"|18(3/1)||class="orange"|18(3/1)
|class="orange"|22(4/1)||class="red"|24(4/1)||class="orange"|22(4/1)||class="red"|26(5/1)
|-
!xxx.W
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!xxx.L
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|20(4/1)||class="orange"|20(4/1)||class="orange"|20(4/1)
|class="red"|24(5/1)||class="red"|26(5/1)||class="red"|24(5/1)||class="red"|28(6/1)
|-
!d(PC)
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!d(PC,ix)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|18(3/1)||class="orange"|18(3/1)||class="orange"|18(3/1)
|class="orange"|22(4/1)||class="red"|24(4/1)||class="orange"|22(4/1)||class="red"|26(5/1)
|-
!#xxx
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|}

The size of the index register (ix) does not affect execution time.

==Long==

Example: '''move.l $05012C,4(a1,d0)''' (Long xxx.L to d(An,ix)) takes 34 cycles.

{|class="wikitable"
!  || Dn || An || (An) || (An)+ || -(An) || d(An) || d(An,ix) || xxx.W || xxx.L
|-
!Dn
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|12(1/2)||class="green"|12(1/2)||class="green"|12(1/2)
|class="yellow"|16(2/2)||class="yellow"|18(2/2)||class="yellow"|16(2/2)||class="yellow"|20(3/2)
|-
!An
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|12(1/2)||class="green"|12(1/2)||class="green"|12(1/2)
|class="yellow"|16(2/2)||class="yellow"|18(2/2)||class="yellow"|16(2/2)||class="yellow"|20(3/2)
|-
!(An)
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|-
!(An)+
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|-
!-(An)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|22(3/2)||class="orange"|22(3/2)||class="orange"|22(3/2)
|class="orange"|26(4/2)||class="orange"|28(4/2)||class="orange"|26(4/2)||class="red"|30(5/2)
|-
!d(An)
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(6/2)
|-
!d(An,ix)
|class="yellow"|18(4/0)||class="yellow"|18(4/0)||class="orange"|26(4/2)||class="orange"|26(4/2)||class="orange"|26(4/2)
|class="red"|30(5/2)||class="red"|32(5/2)||class="red"|30(5/2)||class="red"|34(6/2)
|-
!xxx.W
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(6/2)
|-
!xxx.L
|class="yellow"|20(5/0)||class="yellow"|20(5/0)||class="orange"|28(5/2)||class="orange"|28(5/2)||class="orange"|28(5/2)
|class="red"|32(6/2)||class="red"|34(6/2)||class="red"|32(6/2)||class="red"|36(7/2)
|-
!d(PC)
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(5/2)
|-
!d(PC,ix)
|class="yellow"|18(4/0)||class="yellow"|18(4/0)||class="orange"|26(4/2)||class="orange"|26(4/2)||class="orange"|26(4/2)
|class="red"|30(5/2)||class="red"|32(5/2)||class="red"|30(5/2)||class="red"|34(6/2)
|-
!#xxx
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|}

The size of the index register (ix) does not affect execution time.

=Standard instructions=

Example: '''add.w d3,a7''' (Word ea Dn + An) takes 8 cycles.

The number of clock periods shown in this table indicates the time required to perform the operations, store the results and read the next instruction. The total number of clock periods must be added respectively to those of the effective address calculation where indicated (+).

{|class="wikitable"
!  || Size || <ea>,An * || <ea>,Dn || Dn,<M>
|-
!rowspan=2|ADD
|B,W
|class="orange"|8(1/0)+||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
|class="yellow"|6(1/0)+**||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|-
!rowspan=2|AND
|B,W
| - ||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
| - ||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|-
!rowspan=2|CMP
|B,W
|class="yellow"|6(1/0)+||class="green"|4(1/0)+|| -
|-
|L
|class="yellow"|6(1/0)+||class="yellow"|6(1/0)+|| -
|-
!DIVS
| - || - ||class="red"|158(1/0)+|| -
|-
!DIVU
| - || - ||class="red"|140(1/0)+|| -
|-
!rowspan=2|EOR
|B,W
| - ||class="green"|4(1/0) ***||class="orange"|8(1/1) +
|-
|L
| - ||class="orange"|8(1/0) ***||class="red"|12(1/2) +
|-
!MULS
| - || - ||class="red"|70(1/0)+*|| -
|-
!MULU
| - || - ||class="red"|70(1/0)+*|| -
|-
!rowspan=2|OR
|B,W
| - ||class="green"|4(1/0) +**||class="orange"|8(1/1) +
|-
|L
| - ||class="yellow"|6(1/0) +**||class="red"|12(1/2) +
|-
!rowspan=2|SUB
|B,W
|class="orange"|8(1/0)+||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
|class="yellow"|6(1/0)+**||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|}

<syntaxhighlight lang="text">
notes: + Add effective address calculation time
^ Word or long only
* Indicates maximum value
** The base time of six clock periods is increased to eight
if the effective address mode is register direct or
immediate (effective address time should also be added)
*** Only available effective address mode is data register direct

DIVS,DIVU - The divide algorithm used by the MC68000 provides less
than 10% difference between the best and the worst case
timings.
MULS,MULU - The multiply algorithm requires 38+2n clocks where
n is defined as:
MULU: n = the number of ones in the <ea>
MULS: n = concatenate the <ea> with a zero as the LSB;
n is the resultant number of 10 or 01 patterns
in the 17-bit source; i.e., worst case happens
when the source is $5555
</syntaxhighlight>

=Immediate instructions=

The number of clock periods periods shown in this table includes the time to fetch immediate operands, perform the operations, store the results and read the next operation. The total number of clock periods must be added respectively to those of the effective address calculation where indicated (+).

{|class="wikitable"
!  || Size || #,Dn || #,An || #,M
|-
!rowspan=2|ADDI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|ADDQ
|B,W
|class="green"|4(1/0)||class="yellow"|8(1/0)*||class="orange"|12(1/2)+
|-
|L
|class="yellow"|8(1/0)||class="yellow"|8(1/0)||class="orange"|12(1/2)+
|-
!rowspan=2|ANDI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(1/2)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/1)+
|-
!rowspan=2|CMPI
|B,W
|class="green"|8(2/0)|| - ||class="green"|8(2/0)+
|-
|L
|class="orange"|14(3/0)|| - ||class="yellow"|12(3/1)+
|-
!rowspan=2|EORI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!MOVEQ
|L
|class="green"|4(1/0)|| - || -
|-
!rowspan=2|ORI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|SUBI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|SUBQ
|B,W
|class="green"|4(1/0)||class="yellow"|8(1/0)*||class="yellow"|8(1/1)+
|-
|L
|class="yellow"|8(1/0)||class="yellow"|8(1/0)||class="orange"|12(1/2)+
|}

<syntaxhighlight lang="text">
+ Add effective address calculation time
* word only
</syntaxhighlight>

=Single operand instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the single operand
instructions. The number of clock periods and the number of read and write cycles
must be added respectively to those of the effective address calculation
where indicated.

instruction size register memory

CLR byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NBCD byte 6(1/0) 8(1/1) +
NEG byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NEGX byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NOT byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
Scc byte,false 4(1/0) 8(1/1) +
byte,true 6(1/0) 8(1/1) +
TAS # byte 4(1/0) 10(1/1) +
TST byte,word 4(1/0) 4(1/0) +
long 4(1/0) 4(1/0) +

+ add effective address calculation time
# This instruction should never be used on the Amiga as its invisiable
read/write cycle can disrupt system DMA.
</syntaxhighlight>

=Shift and rotate instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the shift and rotate
instructions. The number of clock periods and the number of read and write
cycles must be added respectively to those of the effective address
calculation where indicated.

instruction size register memory

ASR,ASL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
LSR,LSL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
ROR,ROL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
ROXR,ROXL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -

+ add effective address calculation time
n is the shift or rotate count
</syntaxhighlight>

=Bit manipulation instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods required for the bit
manipulation instructions. The number of clock periods and the number of read and
write cycles must be added respectively to those of the effective address
calculation where indicated. Dynamic: register, static: immediate.

instruction size dynamic static
register memory register memory
BCHG byte - 8(1/1) + - 12(2/1) +
long 8(1/0) * - 12(2/0) * -
BCLR byte - 8(1/1) + - 12(2/1) +
long 10(1/0) * - 14(2/0) * -
BSET byte - 8(1/1) + - 12(2/1) +
long 8(1/0) * - 12(2/0) * -
BTST byte - 4(1/0) + - 8(2/0) +
long 6(1/0) - 10(2/0) -

+ add effective address calculation time
* indicates maximum value
</syntaxhighlight>

=Conditional instructions=

{|class="wikitable"
!Mnemonic || Displacement || Branch taken || Not taken
|-
|rowspan=2|Bcc
|byte
|class="yellow"|10(2/0)||class="green"|8(1/0)
|-
|word
|class="yellow"|10(2/0)||class="orange"|12(1/0)
|-
|rowspan=2|BRA
|byte
|class="yellow"|10(2/0)
|
|-
|word
|class="yellow"|10(2/0)
|
|-
|rowspan=2|BSR
|byte
|class="red"|18(2/2)
|
|-
|word
|class="red"|18(2/2)
|
|-
|rowspan=2|DBcc
|cc true
|
|class="orange"|12(2/0)
|-
|cc false
|class="yellow"|10(2/0)
|class="orange"|14(3/0)
|}

=JMP, JSR, LEA, PEA and MOVEM instructions=

<syntaxhighlight lang="text">
This Table indicates the number of clock periods required for the jump,
jump-to-subroutine, load effective address, push effective address and
move multiple registers instructions.

instr size (An) (An)+ -(An) d(An)
JMP - 8(2/0) - - 10(2/0)
JSR - 16(2/2) - - 18(2/2)
LEA - 4(1/0) - - 8(2/0)
PEA - 12(1/2) - - 16(2/2)
MOVEM word 12+4n 12+4n - 16+4n
M->R (3+n/0) (3+n/0) - (4+n/0)
long 12+8n 12+8n - 16+8n
(3+2n/0) (3+2n/0) - (4+2n/0)
MOVEM word 8+4n - 8+4n 12+4n
R->M (2/n) - (2/n) (3/n)
long 8+8n - 8+8n 12+8n
(2/2n) - (2/2n) (3/2n)

instr size d(An,ix)+ xxx.W xxx.L d(PC) d(PC,ix)*
JMP - 14(3/0) 10(2/0) 12(3/0) 10(2/0) 14(3/0)
JSR - 22(2/2) 18(2/2) 20(3/2) 18(2/2) 22(2/2)
LEA - 12(2/0) 8(2/0) 12(3/0) 8(2/0) 12(2/0)
PEA - 20(2/2) 16(2/2) 20(3/2) 16(2/2) 20(2/2)
MOVEM word 18+4n 16+4n 20+4n 16+4n 18+4n
M->R (4+n/0) (4+n/0) (5+n/0) (4+n/0) (4+n/0)
long 18+8n 16+8n 20+8n 16+8n 18+8n
(4+2n/0) (4+2n/0) (5+2n/0) (4+2n/0) (4+2n/0)
MOVEM word 14+4n 12+4n 16+4n - -
R->M (3/n) (3/n) (4/n) - -
long 14+8n 12+8n 16+8n - -
(3/2n) (3/2n) (4/2n) - -

n is the number of registers to move
* is the size of the index register (ix) does not affect the instruction's
execution time
</syntaxhighlight>

=Multi-precision instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the multi-precision
instructions. The number of clock periods includes the time to fetch both
operands, perform the operations, store the results and read the next
instructions.

instruction size op Dn,Dn op M,M

ADDX byte,word 4(1/0) 18(3/1)
long 8(1/0) 30(5/2)
CMPM byte,word - 12(3/0)
long - 20(5/0)
SUBX byte,word 4(1/0) 18(3/1)
long 8(1/0) 30(5/2)
ABCD byte 6(1/0) 18(3/1)
SBCD byte 6(1/0) 18(3/1)
</syntaxhighlight>

=Miscellaneous instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the following
miscellaneous instructions. The number of clock periods and plus the number
of read and write cycles must be added to those of the effective address
calculation where indicated.

instruction size register memory

ANDI to CCR byte 20(3/0) -
ANDI to SR word 20(3/0) -
CHK - 10(1/0) + -
EORI to CCR byte 20(3/0) -
EORI to SR word 20(3/0) -
ORI to CCR byte 20(3/0) -
ORI to SR word 20(3/0) -
MOVE from SR - 6(1/0) 8(1/1)+
MOVE to CCR - 12(1/0) 12(1/0)+
MOVE to SR - 12(1/0) 12(1/0)+
EXG - 6(1/0) -
EXT word 4(1/0) -
long 4(1/0) -
LINK - 16(2/2) -
MOVE from USP - 4(1/0) -
MOVE to USP - 4(1/0) -
NOP - 4(1/0) -
RESET - 132(1/0) -
RTE - 20(5/0) -
RTR - 20(5/0) -
RTS - 16(4/0) -
STOP - 4(0/0) -
SWAP - 4(1/0) -
TRAPV (No Trap) - 4(1/0) -
UNLK - 12(3/0) -

+ add effective address calculation time
</syntaxhighlight>

=Move Peripheral instructions=

<syntaxhighlight lang="text">
instruction size register->memory memory->register

MOVEP word 16(2/2) 16(4/0)
long 24(2/4) 24(6/0)
</syntaxhighlight>

=Exception processing=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for exception processing.
The number of clock periods includes the time for all stacking, the vector
fetch and the fetch of the first two instruction words of the handler routine.

exception periods

address error 50(4/7)
bus error 50(4/7)
CHK instruction (trap taken) 44(5/3)+
Divide by Zero 42(5/3)
illegal instruction 34(4/3)
interrupt 44(5/3)*
privilege violation 34(4/3)
_____
RESET ** 40(6/0)
trace 34(4/3)
TRAP instruction 38(4/3)
TRAPV instruction (trap taken) 34(4/3)

+ add effective address calculation time
* the interrupt acknowledge cycle is assumed to take four
clock periods
_____ ____
** indicates the time from when RESET and HALT are first
sampled as negated to when instruction execution starts
</syntaxhighlight>

[[Category:Base system]]
[[Category:Code]]

68k instructions timings

2018-01-19T08:45:41Z

Hpman: /* Multi-precision instructions */

Mirrored information from [[http://oldwww.nvg.ntnu.no/amiga/MC680x0_Sections/mc68000timing.HTML oldwww.nvg.ntnu.no]]

The number of bus '''r'''ead and '''w'''rite cycles are shown in parenthesis as (r/w). Any other cycles are internal.

In the following tables, the headings have the following meanings:
* An : Address register operand
* Dn : Data register operand
* ea : Operand specified by an effective address
* M : Memory effective address operand

To get the real execution time, multiply the total cycles count by 83.33ns ([[Clock|1/12MHz]]). An example is given in each section.

The [[68k interrupts|vertical blank]] lasts exactly 40 lines * 384 pixels * 2 cycles per pixel = 30720 cycles (2.56ms).

See [[optimization]].

=Effective address operand calculation=

This table lists the number of clock periods required to compute an instruction's effective address. It includes fetching of any extension words, the address computation, and fetching of the memory operand.

{|class="wikitable"
!Syntax||Adressing mode||B,W||L
|-
|Dn
|Data register direct
|class="green"|0(0/0)
|class="green"|0(0/0)
|-
|An
|Address register direct
|class="green"|0(0/0)
|class="green"|0(0/0)
|-
|(An)
|Address register indirect
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|-
|(An)+
|Address register indirect, post inc.
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|-
| -(An)
|Address register indirect, pre dec.
|class="yellow"|6(1/0)
|class="orange"|10(2/0)
|-
|d(An)
|Address register indirect, displacement
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|d(An,ix)
|Address register indirect, index
|class="orange"|10(2/0)
|class="red"|14(3/0)
|-
|xxx.w
|Absolute short
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|xxx.l
|Absolute long
|class="orange"|12(3/0)
|class="red"|16(4/0)
|-
|d(PC)
|PC with displacement
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|d(PC,ix)
|PC with index
|class="yellow"|10(2/0)
|class="red"|14(3/0)
|-
|#xxx
|Immediate
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|}

Notes:
* Pre-dec is slower than post-inc
* There are no write cycles involved in processing the effective address
* The size of the index register (ix) does not affect execution time

=Move instructions=

These following two tables indicate the number of clock periods for the move instruction. This data includes instruction fetch, operand reads, and operand writes.

==Byte and word==

Example: '''move.b (a0)+,$10201D''' (Byte (An)+ to xxx.L) takes 20 cycles.

{|class="wikitable"
!  || Dn || An || (An) || (An)+ || -(An) || d(An) || d(An,ix) || xxx.W || xxx.L
|-
!Dn
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|8(1/1)||class="green"|8(1/1)
|class="green"|8(1/1)||class="yellow"|12(2/1)||class="yellow"|14(2/1)||class="yellow"|12(2/1)||class="yellow"|16(3/1)
|-
!An
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|8(1/1)||class="green"|8(1/1)
|class="green"|8(1/1)||class="yellow"|12(2/1)||class="yellow"|14(2/1)||class="yellow"|12(2/1)||class="yellow"|16(3/1)
|-
!(An)
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|12(2/1)||class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|-
!(An)+
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|-
!-(An)
|class="green"|10(2/0)||class="green"|10(2/0)||class="yellow"|14(2/1)||class="yellow"|14(2/1)||class="yellow"|14(2/1)
|class="orange"|18(3/1)||class="orange"|20(4/1)||class="orange"|18(3/1)||class="orange"|22(4/1)
|-
!d(An)
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!d(An,ix)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|18(3/1)||class="orange"|18(3/1)||class="orange"|18(3/1)
|class="orange"|22(4/1)||class="red"|24(4/1)||class="orange"|22(4/1)||class="red"|26(5/1)
|-
!xxx.W
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!xxx.L
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|20(4/1)||class="orange"|20(4/1)||class="orange"|20(4/1)
|class="red"|24(5/1)||class="red"|26(5/1)||class="red"|24(5/1)||class="red"|28(6/1)
|-
!d(PC)
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!d(PC,ix)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|18(3/1)||class="orange"|18(3/1)||class="orange"|18(3/1)
|class="orange"|22(4/1)||class="red"|24(4/1)||class="orange"|22(4/1)||class="red"|26(5/1)
|-
!#xxx
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|}

The size of the index register (ix) does not affect execution time.

==Long==

Example: '''move.l $05012C,4(a1,d0)''' (Long xxx.L to d(An,ix)) takes 34 cycles.

{|class="wikitable"
!  || Dn || An || (An) || (An)+ || -(An) || d(An) || d(An,ix) || xxx.W || xxx.L
|-
!Dn
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|12(1/2)||class="green"|12(1/2)||class="green"|12(1/2)
|class="yellow"|16(2/2)||class="yellow"|18(2/2)||class="yellow"|16(2/2)||class="yellow"|20(3/2)
|-
!An
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|12(1/2)||class="green"|12(1/2)||class="green"|12(1/2)
|class="yellow"|16(2/2)||class="yellow"|18(2/2)||class="yellow"|16(2/2)||class="yellow"|20(3/2)
|-
!(An)
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|-
!(An)+
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|-
!-(An)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|22(3/2)||class="orange"|22(3/2)||class="orange"|22(3/2)
|class="orange"|26(4/2)||class="orange"|28(4/2)||class="orange"|26(4/2)||class="red"|30(5/2)
|-
!d(An)
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(6/2)
|-
!d(An,ix)
|class="yellow"|18(4/0)||class="yellow"|18(4/0)||class="orange"|26(4/2)||class="orange"|26(4/2)||class="orange"|26(4/2)
|class="red"|30(5/2)||class="red"|32(5/2)||class="red"|30(5/2)||class="red"|34(6/2)
|-
!xxx.W
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(6/2)
|-
!xxx.L
|class="yellow"|20(5/0)||class="yellow"|20(5/0)||class="orange"|28(5/2)||class="orange"|28(5/2)||class="orange"|28(5/2)
|class="red"|32(6/2)||class="red"|34(6/2)||class="red"|32(6/2)||class="red"|36(7/2)
|-
!d(PC)
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(5/2)
|-
!d(PC,ix)
|class="yellow"|18(4/0)||class="yellow"|18(4/0)||class="orange"|26(4/2)||class="orange"|26(4/2)||class="orange"|26(4/2)
|class="red"|30(5/2)||class="red"|32(5/2)||class="red"|30(5/2)||class="red"|34(6/2)
|-
!#xxx
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|}

The size of the index register (ix) does not affect execution time.

=Standard instructions=

Example: '''add.w d3,a7''' (Word ea Dn + An) takes 8 cycles.

The number of clock periods shown in this table indicates the time required to perform the operations, store the results and read the next instruction. The total number of clock periods must be added respectively to those of the effective address calculation where indicated (+).

{|class="wikitable"
!  || Size || <ea>,An * || <ea>,Dn || Dn,<M>
|-
!rowspan=2|ADD
|B,W
|class="orange"|8(1/0)+||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
|class="yellow"|6(1/0)+**||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|-
!rowspan=2|AND
|B,W
| - ||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
| - ||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|-
!rowspan=2|CMP
|B,W
|class="yellow"|6(1/0)+||class="green"|4(1/0)+|| -
|-
|L
|class="yellow"|6(1/0)+||class="yellow"|6(1/0)+|| -
|-
!DIVS
| - || - ||class="red"|158(1/0)+|| -
|-
!DIVU
| - || - ||class="red"|140(1/0)+|| -
|-
!rowspan=2|EOR
|B,W
| - ||class="green"|4(1/0) ***||class="orange"|8(1/1) +
|-
|L
| - ||class="orange"|8(1/0) ***||class="red"|12(1/2) +
|-
!MULS
| - || - ||class="red"|70(1/0)+*|| -
|-
!MULU
| - || - ||class="red"|70(1/0)+*|| -
|-
!rowspan=2|OR
|B,W
| - ||class="green"|4(1/0) +**||class="orange"|8(1/1) +
|-
|L
| - ||class="yellow"|6(1/0) +**||class="red"|12(1/2) +
|-
!rowspan=2|SUB
|B,W
|class="orange"|8(1/0)+||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
|class="yellow"|6(1/0)+**||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|}

<syntaxhighlight lang="text">
notes: + Add effective address calculation time
^ Word or long only
* Indicates maximum value
** The base time of six clock periods is increased to eight
if the effective address mode is register direct or
immediate (effective address time should also be added)
*** Only available effective address mode is data register direct

DIVS,DIVU - The divide algorithm used by the MC68000 provides less
than 10% difference between the best and the worst case
timings.
MULS,MULU - The multiply algorithm requires 38+2n clocks where
n is defined as:
MULU: n = the number of ones in the <ea>
MULS: n = concatenate the <ea> with a zero as the LSB;
n is the resultant number of 10 or 01 patterns
in the 17-bit source; i.e., worst case happens
when the source is $5555
</syntaxhighlight>

=Immediate instructions=

The number of clock periods periods shown in this table includes the time to fetch immediate operands, perform the operations, store the results and read the next operation. The total number of clock periods must be added respectively to those of the effective address calculation where indicated (+).

{|class="wikitable"
!  || Size || #,Dn || #,An || #,M
|-
!rowspan=2|ADDI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|ADDQ
|B,W
|class="green"|4(1/0)||class="yellow"|8(1/0)*||class="orange"|12(1/2)+
|-
|L
|class="yellow"|8(1/0)||class="yellow"|8(1/0)||class="orange"|12(1/2)+
|-
!rowspan=2|ANDI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(1/2)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/1)+
|-
!rowspan=2|CMPI
|B,W
|class="green"|8(2/0)|| - ||class="green"|8(2/0)+
|-
|L
|class="orange"|14(3/0)|| - ||class="yellow"|12(3/1)+
|-
!rowspan=2|EORI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!MOVEQ
|L
|class="green"|4(1/0)|| - || -
|-
!rowspan=2|ORI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|SUBI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|SUBQ
|B,W
|class="green"|4(1/0)||class="yellow"|8(1/0)*||class="yellow"|8(1/1)+
|-
|L
|class="yellow"|8(1/0)||class="yellow"|8(1/0)||class="orange"|12(1/2)+
|}

<syntaxhighlight lang="text">
+ Add effective address calculation time
* word only
</syntaxhighlight>

=Single operand instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the single operand
instructions. The number of clock periods and the number of read and write cycles
must be added respectively to those of the effective address calculation
where indicated.

instruction size register memory

CLR byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NBCD byte 6(1/0) 8(1/1) +
NEG byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NEGX byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NOT byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
Scc byte,false 4(1/0) 8(1/1) +
byte,true 6(1/0) 8(1/1) +
TAS # byte 4(1/0) 10(1/1) +
TST byte,word 4(1/0) 4(1/0) +
long 4(1/0) 4(1/0) +

+ add effective address calculation time
# This instruction should never be used on the Amiga as its invisiable
read/write cycle can disrupt system DMA.
</syntaxhighlight>

=Shift and rotate instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the shift and rotate
instructions. The number of clock periods and the number of read and write
cycles must be added respectively to those of the effective address
calculation where indicated.

instruction size register memory

ASR,ASL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
LSR,LSL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
ROR,ROL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
ROXR,ROXL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -

+ add effective address calculation time
n is the shift or rotate count
</syntaxhighlight>

=Bit manipulation instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods required for the bit
manipulation instructions. The number of clock periods and the number of read and
write cycles must be added respectively to those of the effective address
calculation where indicated. Dynamic: register, static: immediate.

instruction size dynamic static
register memory register memory
BCHG byte - 8(1/1) + - 12(2/1) +
long 8(1/0) * - 12(2/0) * -
BCLR byte - 8(1/1) + - 12(2/1) +
long 10(1/0) * - 14(2/0) * -
BSET byte - 8(1/1) + - 12(2/1) +
long 8(1/0) * - 12(2/0) * -
BTST byte - 4(1/0) + - 8(2/0) +
long 6(1/0) - 10(2/0) -

+ add effective address calculation time
* indicates maximum value
</syntaxhighlight>

=Conditional instructions=

{|class="wikitable"
!Mnemonic || Displacement || Branch taken || Not taken
|-
|rowspan=2|Bcc
|byte
|class="yellow"|10(2/0)||class="green"|8(1/0)
|-
|word
|class="yellow"|10(2/0)||class="orange"|12(1/0)
|-
|rowspan=2|BRA
|byte
|class="yellow"|10(2/0)
|
|-
|word
|class="yellow"|10(2/0)
|
|-
|rowspan=2|BSR
|byte
|class="red"|18(2/2)
|
|-
|word
|class="red"|18(2/2)
|
|-
|rowspan=2|DBcc
|cc true
|
|class="orange"|12(2/0)
|-
|cc false
|class="yellow"|10(2/0)
|class="orange"|14(3/0)
|}

=JMP, JSR, LEA, PEA and MOVEM instructions=

<syntaxhighlight lang="text">
This Table indicates the number of clock periods required for the jump,
jump-to-subroutine, load effective address, push effective address and
move multiple registers instructions.

instr size (An) (An)+ -(An) d(An)
JMP - 8(2/0) - - 10(2/0)
JSR - 16(2/2) - - 18(2/2)
LEA - 4(1/0) - - 8(2/0)
PEA - 12(1/2) - - 16(2/2)
MOVEM word 12+4n 12+4n - 16+4n
M->R (3+n/0) (3+n/0) - (4+n/0)
long 12+8n 12+8n - 16+8n
(3+2n/0) (3+2n/0) - (4+2n/0)
MOVEM word 8+4n - 8+4n 12+4n
R->M (2/n) - (2/n) (3/n)
long 8+8n - 8+8n 12+8n
(2/2n) - (2/2n) (3/2n)

instr size d(An,ix)+ xxx.W xxx.L d(PC) d(PC,ix)*
JMP - 14(3/0) 10(2/0) 12(3/0) 10(2/0) 14(3/0)
JSR - 22(2/2) 18(2/2) 20(3/2) 18(2/2) 22(2/2)
LEA - 12(2/0) 8(2/0) 12(3/0) 8(2/0) 12(2/0)
PEA - 20(2/2) 16(2/2) 20(3/2) 16(2/2) 20(2/2)
MOVEM word 18+4n 16+4n 20+4n 16+4n 18+4n
M->R (4+n/0) (4+n/0) (5+n/0) (4+n/0) (4+n/0)
long 18+8n 16+8n 20+8n 16+8n 18+8n
(4+2n/0) (4+2n/0) (5+2n/0) (4+2n/0) (4+2n/0)
MOVEM word 14+4n 12+4n 16+4n - -
R->M (3/n) (3/n) (4/n) - -
long 14+8n 12+8n 16+8n - -
(3/2n) (3/2n) (4/2n) - -

n is the number of registers to move
* is the size of the index register (ix) does not affect the instruction's
execution time
</syntaxhighlight>

=Multi-precision instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the multi-precision
instructions. The number of clock periods includes the time to fetch both
operands, perform the operations, store the results and read the next
instructions.

instruction size op Dn,Dn op M,M

ADDX byte,word 4(1/0) 18(3/1)
long 8(1/0) 30(5/2)
CMPM byte,word - 12(3/0)
long - 20(5/0)
SUBX byte,word 4(1/0) 18(3/1)
long 8(1/0) 30(5/2)
ABCD byte 6(1/0) 18(3/1)
SBCD byte 6(1/0) 18(3/1)
</syntaxhighlight>

=Miscellaneous instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the following
miscellaneous instructions. The number of clock periods and plus the number
of read and write cycles must be added to those of the effective address
calculation where indicated.

instruction size register memory

ANDI to CCR byte 20(3/0) -
ANDI to SR word 20(3/0) -
CHK - 10(1/0) + -
EORI to CCR byte 20(3/0) -
EORI to SR word 20(3/0) -
ORI to CCR byte 20(3/0) -
ORI to SR word 20(3/0) -
MOVE from SR - 6(1/0) 8(1/1)+
MOVE to CCR - 12(1/0) 12(1/0)+
MOVE to SR - 12(1/0) 12(1/0)+
EXG - 6(1/0) -
EXT word 4(1/0) -
long 4(1/0) -
LINK - 16(2/2) -
MOVE from USP - 4(1/0) -
MOVE to USP - 4(1/0) -
NOP - 4(1/0) -
RESET - 132(1/0) -
RTE - 20(5/0) -
RTR - 20(5/0) -
RTS - 16(4/0) -
STOP - 4(0/0) -
SWAP - 4(1/0) -
TRAPV (No Trap) - 4(1/0) -
UNLK - 12(3/0) -

+ add effective address calculation time
</syntaxhighlight>

=Move Peripheral instructions=

<syntaxhighlight lang="text">
instruction size register->memory memory->register

MOVEP word 16(2/2) 16(4/0)
long 24(2/4) 24(6/0)
</syntaxhighlight>

=Exception processing=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for exception processing.
The number of clock periods includes the time for all stacking, the vector
fetch and the fetch of the first two instruction words of the handler routine.

exception periods

address error 50(4/7)
bus error 50(4/7)
CHK instruction (trap taken) 44(5/3)+
Divide by Zero 42(5/3)
illegal instruction 34(4/3)
interrupt 44(5/3)*
privilege violation 34(4/3)
_____
RESET ** 40(6/0)
trace 34(4/3)
TRAP instruction 38(4/3)
TRAPV instruction (trap taken) 34(4/3)

+ add effective address calculation time
* the interrupt acknowledge cycle is assumed to take four
clock periods
_____ ____
** indicates the time from when RESET and HALT are first
sampled as negated to when instruction execution starts
</syntaxhighlight>

[[Category:Base system]]
[[Category:Code]]

68k instructions timings

2018-01-19T08:06:51Z

Hpman: /* Shift and rotate instructions */

Mirrored information from [[http://oldwww.nvg.ntnu.no/amiga/MC680x0_Sections/mc68000timing.HTML oldwww.nvg.ntnu.no]]

The number of bus '''r'''ead and '''w'''rite cycles are shown in parenthesis as (r/w). Any other cycles are internal.

In the following tables, the headings have the following meanings:
* An : Address register operand
* Dn : Data register operand
* ea : Operand specified by an effective address
* M : Memory effective address operand

To get the real execution time, multiply the total cycles count by 83.33ns ([[Clock|1/12MHz]]). An example is given in each section.

The [[68k interrupts|vertical blank]] lasts exactly 40 lines * 384 pixels * 2 cycles per pixel = 30720 cycles (2.56ms).

See [[optimization]].

=Effective address operand calculation=

This table lists the number of clock periods required to compute an instruction's effective address. It includes fetching of any extension words, the address computation, and fetching of the memory operand.

{|class="wikitable"
!Syntax||Adressing mode||B,W||L
|-
|Dn
|Data register direct
|class="green"|0(0/0)
|class="green"|0(0/0)
|-
|An
|Address register direct
|class="green"|0(0/0)
|class="green"|0(0/0)
|-
|(An)
|Address register indirect
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|-
|(An)+
|Address register indirect, post inc.
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|-
| -(An)
|Address register indirect, pre dec.
|class="yellow"|6(1/0)
|class="orange"|10(2/0)
|-
|d(An)
|Address register indirect, displacement
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|d(An,ix)
|Address register indirect, index
|class="orange"|10(2/0)
|class="red"|14(3/0)
|-
|xxx.w
|Absolute short
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|xxx.l
|Absolute long
|class="orange"|12(3/0)
|class="red"|16(4/0)
|-
|d(PC)
|PC with displacement
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|d(PC,ix)
|PC with index
|class="yellow"|10(2/0)
|class="red"|14(3/0)
|-
|#xxx
|Immediate
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|}

Notes:
* Pre-dec is slower than post-inc
* There are no write cycles involved in processing the effective address
* The size of the index register (ix) does not affect execution time

=Move instructions=

These following two tables indicate the number of clock periods for the move instruction. This data includes instruction fetch, operand reads, and operand writes.

==Byte and word==

Example: '''move.b (a0)+,$10201D''' (Byte (An)+ to xxx.L) takes 20 cycles.

{|class="wikitable"
!  || Dn || An || (An) || (An)+ || -(An) || d(An) || d(An,ix) || xxx.W || xxx.L
|-
!Dn
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|8(1/1)||class="green"|8(1/1)
|class="green"|8(1/1)||class="yellow"|12(2/1)||class="yellow"|14(2/1)||class="yellow"|12(2/1)||class="yellow"|16(3/1)
|-
!An
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|8(1/1)||class="green"|8(1/1)
|class="green"|8(1/1)||class="yellow"|12(2/1)||class="yellow"|14(2/1)||class="yellow"|12(2/1)||class="yellow"|16(3/1)
|-
!(An)
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|12(2/1)||class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|-
!(An)+
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|-
!-(An)
|class="green"|10(2/0)||class="green"|10(2/0)||class="yellow"|14(2/1)||class="yellow"|14(2/1)||class="yellow"|14(2/1)
|class="orange"|18(3/1)||class="orange"|20(4/1)||class="orange"|18(3/1)||class="orange"|22(4/1)
|-
!d(An)
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!d(An,ix)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|18(3/1)||class="orange"|18(3/1)||class="orange"|18(3/1)
|class="orange"|22(4/1)||class="red"|24(4/1)||class="orange"|22(4/1)||class="red"|26(5/1)
|-
!xxx.W
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!xxx.L
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|20(4/1)||class="orange"|20(4/1)||class="orange"|20(4/1)
|class="red"|24(5/1)||class="red"|26(5/1)||class="red"|24(5/1)||class="red"|28(6/1)
|-
!d(PC)
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!d(PC,ix)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|18(3/1)||class="orange"|18(3/1)||class="orange"|18(3/1)
|class="orange"|22(4/1)||class="red"|24(4/1)||class="orange"|22(4/1)||class="red"|26(5/1)
|-
!#xxx
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|}

The size of the index register (ix) does not affect execution time.

==Long==

Example: '''move.l $05012C,4(a1,d0)''' (Long xxx.L to d(An,ix)) takes 34 cycles.

{|class="wikitable"
!  || Dn || An || (An) || (An)+ || -(An) || d(An) || d(An,ix) || xxx.W || xxx.L
|-
!Dn
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|12(1/2)||class="green"|12(1/2)||class="green"|12(1/2)
|class="yellow"|16(2/2)||class="yellow"|18(2/2)||class="yellow"|16(2/2)||class="yellow"|20(3/2)
|-
!An
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|12(1/2)||class="green"|12(1/2)||class="green"|12(1/2)
|class="yellow"|16(2/2)||class="yellow"|18(2/2)||class="yellow"|16(2/2)||class="yellow"|20(3/2)
|-
!(An)
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|-
!(An)+
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|-
!-(An)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|22(3/2)||class="orange"|22(3/2)||class="orange"|22(3/2)
|class="orange"|26(4/2)||class="orange"|28(4/2)||class="orange"|26(4/2)||class="red"|30(5/2)
|-
!d(An)
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(6/2)
|-
!d(An,ix)
|class="yellow"|18(4/0)||class="yellow"|18(4/0)||class="orange"|26(4/2)||class="orange"|26(4/2)||class="orange"|26(4/2)
|class="red"|30(5/2)||class="red"|32(5/2)||class="red"|30(5/2)||class="red"|34(6/2)
|-
!xxx.W
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(6/2)
|-
!xxx.L
|class="yellow"|20(5/0)||class="yellow"|20(5/0)||class="orange"|28(5/2)||class="orange"|28(5/2)||class="orange"|28(5/2)
|class="red"|32(6/2)||class="red"|34(6/2)||class="red"|32(6/2)||class="red"|36(7/2)
|-
!d(PC)
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(5/2)
|-
!d(PC,ix)
|class="yellow"|18(4/0)||class="yellow"|18(4/0)||class="orange"|26(4/2)||class="orange"|26(4/2)||class="orange"|26(4/2)
|class="red"|30(5/2)||class="red"|32(5/2)||class="red"|30(5/2)||class="red"|34(6/2)
|-
!#xxx
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|}

The size of the index register (ix) does not affect execution time.

=Standard instructions=

Example: '''add.w d3,a7''' (Word ea Dn + An) takes 8 cycles.

The number of clock periods shown in this table indicates the time required to perform the operations, store the results and read the next instruction. The total number of clock periods must be added respectively to those of the effective address calculation where indicated (+).

{|class="wikitable"
!  || Size || <ea>,An * || <ea>,Dn || Dn,<M>
|-
!rowspan=2|ADD
|B,W
|class="orange"|8(1/0)+||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
|class="yellow"|6(1/0)+**||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|-
!rowspan=2|AND
|B,W
| - ||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
| - ||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|-
!rowspan=2|CMP
|B,W
|class="yellow"|6(1/0)+||class="green"|4(1/0)+|| -
|-
|L
|class="yellow"|6(1/0)+||class="yellow"|6(1/0)+|| -
|-
!DIVS
| - || - ||class="red"|158(1/0)+|| -
|-
!DIVU
| - || - ||class="red"|140(1/0)+|| -
|-
!rowspan=2|EOR
|B,W
| - ||class="green"|4(1/0) ***||class="orange"|8(1/1) +
|-
|L
| - ||class="orange"|8(1/0) ***||class="red"|12(1/2) +
|-
!MULS
| - || - ||class="red"|70(1/0)+*|| -
|-
!MULU
| - || - ||class="red"|70(1/0)+*|| -
|-
!rowspan=2|OR
|B,W
| - ||class="green"|4(1/0) +**||class="orange"|8(1/1) +
|-
|L
| - ||class="yellow"|6(1/0) +**||class="red"|12(1/2) +
|-
!rowspan=2|SUB
|B,W
|class="orange"|8(1/0)+||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
|class="yellow"|6(1/0)+**||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|}

<syntaxhighlight lang="text">
notes: + Add effective address calculation time
^ Word or long only
* Indicates maximum value
** The base time of six clock periods is increased to eight
if the effective address mode is register direct or
immediate (effective address time should also be added)
*** Only available effective address mode is data register direct

DIVS,DIVU - The divide algorithm used by the MC68000 provides less
than 10% difference between the best and the worst case
timings.
MULS,MULU - The multiply algorithm requires 38+2n clocks where
n is defined as:
MULU: n = the number of ones in the <ea>
MULS: n = concatenate the <ea> with a zero as the LSB;
n is the resultant number of 10 or 01 patterns
in the 17-bit source; i.e., worst case happens
when the source is $5555
</syntaxhighlight>

=Immediate instructions=

The number of clock periods periods shown in this table includes the time to fetch immediate operands, perform the operations, store the results and read the next operation. The total number of clock periods must be added respectively to those of the effective address calculation where indicated (+).

{|class="wikitable"
!  || Size || #,Dn || #,An || #,M
|-
!rowspan=2|ADDI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|ADDQ
|B,W
|class="green"|4(1/0)||class="yellow"|8(1/0)*||class="orange"|12(1/2)+
|-
|L
|class="yellow"|8(1/0)||class="yellow"|8(1/0)||class="orange"|12(1/2)+
|-
!rowspan=2|ANDI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(1/2)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/1)+
|-
!rowspan=2|CMPI
|B,W
|class="green"|8(2/0)|| - ||class="green"|8(2/0)+
|-
|L
|class="orange"|14(3/0)|| - ||class="yellow"|12(3/1)+
|-
!rowspan=2|EORI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!MOVEQ
|L
|class="green"|4(1/0)|| - || -
|-
!rowspan=2|ORI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|SUBI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|SUBQ
|B,W
|class="green"|4(1/0)||class="yellow"|8(1/0)*||class="yellow"|8(1/1)+
|-
|L
|class="yellow"|8(1/0)||class="yellow"|8(1/0)||class="orange"|12(1/2)+
|}

<syntaxhighlight lang="text">
+ Add effective address calculation time
* word only
</syntaxhighlight>

=Single operand instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the single operand
instructions. The number of clock periods and the number of read and write cycles
must be added respectively to those of the effective address calculation
where indicated.

instruction size register memory

CLR byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NBCD byte 6(1/0) 8(1/1) +
NEG byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NEGX byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NOT byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
Scc byte,false 4(1/0) 8(1/1) +
byte,true 6(1/0) 8(1/1) +
TAS # byte 4(1/0) 10(1/1) +
TST byte,word 4(1/0) 4(1/0) +
long 4(1/0) 4(1/0) +

+ add effective address calculation time
# This instruction should never be used on the Amiga as its invisiable
read/write cycle can disrupt system DMA.
</syntaxhighlight>

=Shift and rotate instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the shift and rotate
instructions. The number of clock periods and the number of read and write
cycles must be added respectively to those of the effective address
calculation where indicated.

instruction size register memory

ASR,ASL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
LSR,LSL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
ROR,ROL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
ROXR,ROXL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -

+ add effective address calculation time
n is the shift or rotate count
</syntaxhighlight>

=Bit manipulation instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods required for the bit
manipulation instructions. The number of clock periods and the number of read and
write cycles must be added respectively to those of the effective address
calculation where indicated. Dynamic: register, static: immediate.

instruction size dynamic static
register memory register memory
BCHG byte - 8(1/1) + - 12(2/1) +
long 8(1/0) * - 12(2/0) * -
BCLR byte - 8(1/1) + - 12(2/1) +
long 10(1/0) * - 14(2/0) * -
BSET byte - 8(1/1) + - 12(2/1) +
long 8(1/0) * - 12(2/0) * -
BTST byte - 4(1/0) + - 8(2/0) +
long 6(1/0) - 10(2/0) -

+ add effective address calculation time
* indicates maximum value
</syntaxhighlight>

=Conditional instructions=

{|class="wikitable"
!Mnemonic || Displacement || Branch taken || Not taken
|-
|rowspan=2|Bcc
|byte
|class="yellow"|10(2/0)||class="green"|8(1/0)
|-
|word
|class="yellow"|10(2/0)||class="orange"|12(1/0)
|-
|rowspan=2|BRA
|byte
|class="yellow"|10(2/0)
|
|-
|word
|class="yellow"|10(2/0)
|
|-
|rowspan=2|BSR
|byte
|class="red"|18(2/2)
|
|-
|word
|class="red"|18(2/2)
|
|-
|rowspan=2|DBcc
|cc true
|
|class="orange"|12(2/0)
|-
|cc false
|class="yellow"|10(2/0)
|class="orange"|14(3/0)
|}

=JMP, JSR, LEA, PEA and MOVEM instructions=

<syntaxhighlight lang="text">
This Table indicates the number of clock periods required for the jump,
jump-to-subroutine, load effective address, push effective address and
move multiple registers instructions.

instr size (An) (An)+ -(An) d(An)
JMP - 8(2/0) - - 10(2/0)
JSR - 16(2/2) - - 18(2/2)
LEA - 4(1/0) - - 8(2/0)
PEA - 12(1/2) - - 16(2/2)
MOVEM word 12+4n 12+4n - 16+4n
M->R (3+n/0) (3+n/0) - (4+n/0)
long 12+8n 12+8n - 16+8n
(3+2n/0) (3+2n/0) - (4+2n/0)
MOVEM word 8+4n - 8+4n 12+4n
R->M (2/n) - (2/n) (3/n)
long 8+8n - 8+8n 12+8n
(2/2n) - (2/2n) (3/2n)

instr size d(An,ix)+ xxx.W xxx.L d(PC) d(PC,ix)*
JMP - 14(3/0) 10(2/0) 12(3/0) 10(2/0) 14(3/0)
JSR - 22(2/2) 18(2/2) 20(3/2) 18(2/2) 22(2/2)
LEA - 12(2/0) 8(2/0) 12(3/0) 8(2/0) 12(2/0)
PEA - 20(2/2) 16(2/2) 20(3/2) 16(2/2) 20(2/2)
MOVEM word 18+4n 16+4n 20+4n 16+4n 18+4n
M->R (4+n/0) (4+n/0) (5+n/0) (4+n/0) (4+n/0)
long 18+8n 16+8n 20+8n 16+8n 18+8n
(4+2n/0) (4+2n/0) (5+2n/0) (4+2n/0) (4+2n/0)
MOVEM word 14+4n 12+4n 16+4n - -
R->M (3/n) (3/n) (4/n) - -
long 14+8n 12+8n 16+8n - -
(3/2n) (3/2n) (4/2n) - -

n is the number of registers to move
* is the size of the index register (ix) does not affect the instruction's
execution time
</syntaxhighlight>

=Multi-precision instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the multi-precision
instructions. The number of clock periods includes the time to fetch both
operands, perform the operations, store the results and read the next
instructions.

instruction size op Dn,Dn op M,M

ADDX byte,word 4(1/0) 18(3/1)
long 8(1/0) 30(5/2)
CMPM byte,word - 12(3/0)
long - 20(5/0)
SUBX byte,word 4(1/0) 18(3/1)
long 8(1/0) 30(5/2)
ABCD byte 6(1/0) 18(3/1)
SBCD byte 6(1/0) 18(3/1)
</syntaxhighlight>

=Miscellaneous instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the following
miscellaneous instructions. The number of clock periods and plus the number
of read and write cycles must be added to those of the effective address
calculation where indicated.

instruction size register memory

ANDI to CCR byte 20(3/0) -
ANDI to SR word 20(3/0) -
CHK - 10(1/0) + -
EORI to CCR byte 20(3/0) -
EORI to SR word 20(3/0) -
ORI to CCR byte 20(3/0) -
ORI to SR word 20(3/0) -
MOVE from SR - 6(1/0) 8(1/1)+
MOVE to CCR - 12(1/0) 12(1/0)+
MOVE to SR - 12(1/0) 12(1/0)+
EXG - 6(1/0) -
EXT word 4(1/0) -
long 4(1/0) -
LINK - 16(2/2) -
MOVE from USP - 4(1/0) -
MOVE to USP - 4(1/0) -
NOP - 4(1/0) -
RESET - 132(1/0) -
RTE - 20(5/0) -
RTR - 20(5/0) -
RTS - 16(4/0) -
STOP - 4(0/0) -
SWAP - 4(1/0) -
TRAPV (No Trap) - 4(1/0) -
UNLK - 12(3/0) -

+ add effective address calculation time
</syntaxhighlight>

=Move Peripheral instructions=

<syntaxhighlight lang="text">
instruction size register->memory memory->register

MOVEP word 16(2/2) 16(4/0)
long 24(2/4) 24(6/0)
</syntaxhighlight>

=Exception processing=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for exception processing.
The number of clock periods includes the time for all stacking, the vector
fetch and the fetch of the first two instruction words of the handler routine.

exception periods

address error 50(4/7)
bus error 50(4/7)
CHK instruction (trap taken) 44(5/3)+
Divide by Zero 42(5/3)
illegal instruction 34(4/3)
interrupt 44(5/3)*
privilege violation 34(4/3)
_____
RESET ** 40(6/0)
trace 34(4/3)
TRAP instruction 38(4/3)
TRAPV instruction (trap taken) 34(4/3)

+ add effective address calculation time
* the interrupt acknowledge cycle is assumed to take four
clock periods
_____ ____
** indicates the time from when RESET and HALT are first
sampled as negated to when instruction execution starts
</syntaxhighlight>

[[Category:Base system]]
[[Category:Code]]

68k instructions timings

2018-01-19T07:55:52Z

Hpman: /* Miscellaneous instructions */

Mirrored information from [[http://oldwww.nvg.ntnu.no/amiga/MC680x0_Sections/mc68000timing.HTML oldwww.nvg.ntnu.no]]

The number of bus '''r'''ead and '''w'''rite cycles are shown in parenthesis as (r/w). Any other cycles are internal.

In the following tables, the headings have the following meanings:
* An : Address register operand
* Dn : Data register operand
* ea : Operand specified by an effective address
* M : Memory effective address operand

To get the real execution time, multiply the total cycles count by 83.33ns ([[Clock|1/12MHz]]). An example is given in each section.

The [[68k interrupts|vertical blank]] lasts exactly 40 lines * 384 pixels * 2 cycles per pixel = 30720 cycles (2.56ms).

See [[optimization]].

=Effective address operand calculation=

This table lists the number of clock periods required to compute an instruction's effective address. It includes fetching of any extension words, the address computation, and fetching of the memory operand.

{|class="wikitable"
!Syntax||Adressing mode||B,W||L
|-
|Dn
|Data register direct
|class="green"|0(0/0)
|class="green"|0(0/0)
|-
|An
|Address register direct
|class="green"|0(0/0)
|class="green"|0(0/0)
|-
|(An)
|Address register indirect
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|-
|(An)+
|Address register indirect, post inc.
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|-
| -(An)
|Address register indirect, pre dec.
|class="yellow"|6(1/0)
|class="orange"|10(2/0)
|-
|d(An)
|Address register indirect, displacement
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|d(An,ix)
|Address register indirect, index
|class="orange"|10(2/0)
|class="red"|14(3/0)
|-
|xxx.w
|Absolute short
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|xxx.l
|Absolute long
|class="orange"|12(3/0)
|class="red"|16(4/0)
|-
|d(PC)
|PC with displacement
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|d(PC,ix)
|PC with index
|class="yellow"|10(2/0)
|class="red"|14(3/0)
|-
|#xxx
|Immediate
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|}

Notes:
* Pre-dec is slower than post-inc
* There are no write cycles involved in processing the effective address
* The size of the index register (ix) does not affect execution time

=Move instructions=

These following two tables indicate the number of clock periods for the move instruction. This data includes instruction fetch, operand reads, and operand writes.

==Byte and word==

Example: '''move.b (a0)+,$10201D''' (Byte (An)+ to xxx.L) takes 20 cycles.

{|class="wikitable"
!  || Dn || An || (An) || (An)+ || -(An) || d(An) || d(An,ix) || xxx.W || xxx.L
|-
!Dn
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|8(1/1)||class="green"|8(1/1)
|class="green"|8(1/1)||class="yellow"|12(2/1)||class="yellow"|14(2/1)||class="yellow"|12(2/1)||class="yellow"|16(3/1)
|-
!An
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|8(1/1)||class="green"|8(1/1)
|class="green"|8(1/1)||class="yellow"|12(2/1)||class="yellow"|14(2/1)||class="yellow"|12(2/1)||class="yellow"|16(3/1)
|-
!(An)
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|12(2/1)||class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|-
!(An)+
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|-
!-(An)
|class="green"|10(2/0)||class="green"|10(2/0)||class="yellow"|14(2/1)||class="yellow"|14(2/1)||class="yellow"|14(2/1)
|class="orange"|18(3/1)||class="orange"|20(4/1)||class="orange"|18(3/1)||class="orange"|22(4/1)
|-
!d(An)
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!d(An,ix)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|18(3/1)||class="orange"|18(3/1)||class="orange"|18(3/1)
|class="orange"|22(4/1)||class="red"|24(4/1)||class="orange"|22(4/1)||class="red"|26(5/1)
|-
!xxx.W
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!xxx.L
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|20(4/1)||class="orange"|20(4/1)||class="orange"|20(4/1)
|class="red"|24(5/1)||class="red"|26(5/1)||class="red"|24(5/1)||class="red"|28(6/1)
|-
!d(PC)
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!d(PC,ix)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|18(3/1)||class="orange"|18(3/1)||class="orange"|18(3/1)
|class="orange"|22(4/1)||class="red"|24(4/1)||class="orange"|22(4/1)||class="red"|26(5/1)
|-
!#xxx
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|}

The size of the index register (ix) does not affect execution time.

==Long==

Example: '''move.l $05012C,4(a1,d0)''' (Long xxx.L to d(An,ix)) takes 34 cycles.

{|class="wikitable"
!  || Dn || An || (An) || (An)+ || -(An) || d(An) || d(An,ix) || xxx.W || xxx.L
|-
!Dn
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|12(1/2)||class="green"|12(1/2)||class="green"|12(1/2)
|class="yellow"|16(2/2)||class="yellow"|18(2/2)||class="yellow"|16(2/2)||class="yellow"|20(3/2)
|-
!An
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|12(1/2)||class="green"|12(1/2)||class="green"|12(1/2)
|class="yellow"|16(2/2)||class="yellow"|18(2/2)||class="yellow"|16(2/2)||class="yellow"|20(3/2)
|-
!(An)
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|-
!(An)+
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|-
!-(An)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|22(3/2)||class="orange"|22(3/2)||class="orange"|22(3/2)
|class="orange"|26(4/2)||class="orange"|28(4/2)||class="orange"|26(4/2)||class="red"|30(5/2)
|-
!d(An)
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(6/2)
|-
!d(An,ix)
|class="yellow"|18(4/0)||class="yellow"|18(4/0)||class="orange"|26(4/2)||class="orange"|26(4/2)||class="orange"|26(4/2)
|class="red"|30(5/2)||class="red"|32(5/2)||class="red"|30(5/2)||class="red"|34(6/2)
|-
!xxx.W
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(6/2)
|-
!xxx.L
|class="yellow"|20(5/0)||class="yellow"|20(5/0)||class="orange"|28(5/2)||class="orange"|28(5/2)||class="orange"|28(5/2)
|class="red"|32(6/2)||class="red"|34(6/2)||class="red"|32(6/2)||class="red"|36(7/2)
|-
!d(PC)
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(5/2)
|-
!d(PC,ix)
|class="yellow"|18(4/0)||class="yellow"|18(4/0)||class="orange"|26(4/2)||class="orange"|26(4/2)||class="orange"|26(4/2)
|class="red"|30(5/2)||class="red"|32(5/2)||class="red"|30(5/2)||class="red"|34(6/2)
|-
!#xxx
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|}

The size of the index register (ix) does not affect execution time.

=Standard instructions=

Example: '''add.w d3,a7''' (Word ea Dn + An) takes 8 cycles.

The number of clock periods shown in this table indicates the time required to perform the operations, store the results and read the next instruction. The total number of clock periods must be added respectively to those of the effective address calculation where indicated (+).

{|class="wikitable"
!  || Size || <ea>,An * || <ea>,Dn || Dn,<M>
|-
!rowspan=2|ADD
|B,W
|class="orange"|8(1/0)+||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
|class="yellow"|6(1/0)+**||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|-
!rowspan=2|AND
|B,W
| - ||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
| - ||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|-
!rowspan=2|CMP
|B,W
|class="yellow"|6(1/0)+||class="green"|4(1/0)+|| -
|-
|L
|class="yellow"|6(1/0)+||class="yellow"|6(1/0)+|| -
|-
!DIVS
| - || - ||class="red"|158(1/0)+|| -
|-
!DIVU
| - || - ||class="red"|140(1/0)+|| -
|-
!rowspan=2|EOR
|B,W
| - ||class="green"|4(1/0) ***||class="orange"|8(1/1) +
|-
|L
| - ||class="orange"|8(1/0) ***||class="red"|12(1/2) +
|-
!MULS
| - || - ||class="red"|70(1/0)+*|| -
|-
!MULU
| - || - ||class="red"|70(1/0)+*|| -
|-
!rowspan=2|OR
|B,W
| - ||class="green"|4(1/0) +**||class="orange"|8(1/1) +
|-
|L
| - ||class="yellow"|6(1/0) +**||class="red"|12(1/2) +
|-
!rowspan=2|SUB
|B,W
|class="orange"|8(1/0)+||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
|class="yellow"|6(1/0)+**||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|}

<syntaxhighlight lang="text">
notes: + Add effective address calculation time
^ Word or long only
* Indicates maximum value
** The base time of six clock periods is increased to eight
if the effective address mode is register direct or
immediate (effective address time should also be added)
*** Only available effective address mode is data register direct

DIVS,DIVU - The divide algorithm used by the MC68000 provides less
than 10% difference between the best and the worst case
timings.
MULS,MULU - The multiply algorithm requires 38+2n clocks where
n is defined as:
MULU: n = the number of ones in the <ea>
MULS: n = concatenate the <ea> with a zero as the LSB;
n is the resultant number of 10 or 01 patterns
in the 17-bit source; i.e., worst case happens
when the source is $5555
</syntaxhighlight>

=Immediate instructions=

The number of clock periods periods shown in this table includes the time to fetch immediate operands, perform the operations, store the results and read the next operation. The total number of clock periods must be added respectively to those of the effective address calculation where indicated (+).

{|class="wikitable"
!  || Size || #,Dn || #,An || #,M
|-
!rowspan=2|ADDI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|ADDQ
|B,W
|class="green"|4(1/0)||class="yellow"|8(1/0)*||class="orange"|12(1/2)+
|-
|L
|class="yellow"|8(1/0)||class="yellow"|8(1/0)||class="orange"|12(1/2)+
|-
!rowspan=2|ANDI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(1/2)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/1)+
|-
!rowspan=2|CMPI
|B,W
|class="green"|8(2/0)|| - ||class="green"|8(2/0)+
|-
|L
|class="orange"|14(3/0)|| - ||class="yellow"|12(3/1)+
|-
!rowspan=2|EORI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!MOVEQ
|L
|class="green"|4(1/0)|| - || -
|-
!rowspan=2|ORI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|SUBI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|SUBQ
|B,W
|class="green"|4(1/0)||class="yellow"|8(1/0)*||class="yellow"|8(1/1)+
|-
|L
|class="yellow"|8(1/0)||class="yellow"|8(1/0)||class="orange"|12(1/2)+
|}

<syntaxhighlight lang="text">
+ Add effective address calculation time
* word only
</syntaxhighlight>

=Single operand instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the single operand
instructions. The number of clock periods and the number of read and write cycles
must be added respectively to those of the effective address calculation
where indicated.

instruction size register memory

CLR byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NBCD byte 6(1/0) 8(1/1) +
NEG byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NEGX byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NOT byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
Scc byte,false 4(1/0) 8(1/1) +
byte,true 6(1/0) 8(1/1) +
TAS # byte 4(1/0) 10(1/1) +
TST byte,word 4(1/0) 4(1/0) +
long 4(1/0) 4(1/0) +

+ add effective address calculation time
# This instruction should never be used on the Amiga as its invisiable
read/write cycle can disrupt system DMA.
</syntaxhighlight>

=Shift and rotate instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the shift and rotate
instructions. The number of clock periods and the number of read and write
cycles must be added respectively to those of the effective address
calculation where indicated.

instruction size register memory

ASR,ASL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
LSR,LSL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
ROR,ROL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
ROXR,ROXL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -

+ add effective address calculation time
n is the shift or rotate count
</syntaxhighlight>

=Bit manipulation instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods required for the bit
manipulation instructions. The number of clock periods and the number of read and
write cycles must be added respectively to those of the effective address
calculation where indicated. Dynamic: register, static: immediate.

instruction size dynamic static
register memory register memory
BCHG byte - 8(1/1) + - 12(2/1) +
long 8(1/0) * - 12(2/0) * -
BCLR byte - 8(1/1) + - 12(2/1) +
long 10(1/0) * - 14(2/0) * -
BSET byte - 8(1/1) + - 12(2/1) +
long 8(1/0) * - 12(2/0) * -
BTST byte - 4(1/0) + - 8(2/0) +
long 6(1/0) - 10(2/0) -

+ add effective address calculation time
* indicates maximum value
</syntaxhighlight>

=Conditional instructions=

{|class="wikitable"
!Mnemonic || Displacement || Branch taken || Not taken
|-
|rowspan=2|Bcc
|byte
|class="yellow"|10(2/0)||class="green"|8(1/0)
|-
|word
|class="yellow"|10(2/0)||class="orange"|12(1/0)
|-
|rowspan=2|BRA
|byte
|class="yellow"|10(2/0)
|
|-
|word
|class="yellow"|10(2/0)
|
|-
|rowspan=2|BSR
|byte
|class="red"|18(2/2)
|
|-
|word
|class="red"|18(2/2)
|
|-
|rowspan=2|DBcc
|cc true
|
|class="orange"|12(2/0)
|-
|cc false
|class="yellow"|10(2/0)
|class="orange"|14(3/0)
|}

=JMP, JSR, LEA, PEA and MOVEM instructions=

<syntaxhighlight lang="text">
This Table indicates the number of clock periods required for the jump,
jump-to-subroutine, load effective address, push effective address and
move multiple registers instructions.

instr size (An) (An)+ -(An) d(An)
JMP - 8(2/0) - - 10(2/0)
JSR - 16(2/2) - - 18(2/2)
LEA - 4(1/0) - - 8(2/0)
PEA - 12(1/2) - - 16(2/2)
MOVEM word 12+4n 12+4n - 16+4n
M->R (3+n/0) (3+n/0) - (4+n/0)
long 12+8n 12+8n - 16+8n
(3+2n/0) (3+2n/0) - (4+2n/0)
MOVEM word 8+4n - 8+4n 12+4n
R->M (2/n) - (2/n) (3/n)
long 8+8n - 8+8n 12+8n
(2/2n) - (2/2n) (3/2n)

instr size d(An,ix)+ xxx.W xxx.L d(PC) d(PC,ix)*
JMP - 14(3/0) 10(2/0) 12(3/0) 10(2/0) 14(3/0)
JSR - 22(2/2) 18(2/2) 20(3/2) 18(2/2) 22(2/2)
LEA - 12(2/0) 8(2/0) 12(3/0) 8(2/0) 12(2/0)
PEA - 20(2/2) 16(2/2) 20(3/2) 16(2/2) 20(2/2)
MOVEM word 18+4n 16+4n 20+4n 16+4n 18+4n
M->R (4+n/0) (4+n/0) (5+n/0) (4+n/0) (4+n/0)
long 18+8n 16+8n 20+8n 16+8n 18+8n
(4+2n/0) (4+2n/0) (5+2n/0) (4+2n/0) (4+2n/0)
MOVEM word 14+4n 12+4n 16+4n - -
R->M (3/n) (3/n) (4/n) - -
long 14+8n 12+8n 16+8n - -
(3/2n) (3/2n) (4/2n) - -

n is the number of registers to move
* is the size of the index register (ix) does not affect the instruction's
execution time
</syntaxhighlight>

=Multi-precision instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the multi-precision
instructions. The number of clock periods includes the time to fetch both
operands, perform the operations, store the results and read the next
instructions.

instruction size op Dn,Dn op M,M

ADDX byte,word 4(1/0) 18(3/1)
long 8(1/0) 30(5/2)
CMPM byte,word - 12(3/0)
long - 20(5/0)
SUBX byte,word 4(1/0) 18(3/1)
long 8(1/0) 30(5/2)
ABCD byte 6(1/0) 18(3/1)
SBCD byte 6(1/0) 18(3/1)
</syntaxhighlight>

=Miscellaneous instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the following
miscellaneous instructions. The number of clock periods and plus the number
of read and write cycles must be added to those of the effective address
calculation where indicated.

instruction size register memory

ANDI to CCR byte 20(3/0) -
ANDI to SR word 20(3/0) -
CHK - 10(1/0) + -
EORI to CCR byte 20(3/0) -
EORI to SR word 20(3/0) -
ORI to CCR byte 20(3/0) -
ORI to SR word 20(3/0) -
MOVE from SR - 6(1/0) 8(1/1)+
MOVE to CCR - 12(1/0) 12(1/0)+
MOVE to SR - 12(1/0) 12(1/0)+
EXG - 6(1/0) -
EXT word 4(1/0) -
long 4(1/0) -
LINK - 16(2/2) -
MOVE from USP - 4(1/0) -
MOVE to USP - 4(1/0) -
NOP - 4(1/0) -
RESET - 132(1/0) -
RTE - 20(5/0) -
RTR - 20(5/0) -
RTS - 16(4/0) -
STOP - 4(0/0) -
SWAP - 4(1/0) -
TRAPV (No Trap) - 4(1/0) -
UNLK - 12(3/0) -

+ add effective address calculation time
</syntaxhighlight>

=Move Peripheral instructions=

<syntaxhighlight lang="text">
instruction size register->memory memory->register

MOVEP word 16(2/2) 16(4/0)
long 24(2/4) 24(6/0)
</syntaxhighlight>

=Exception processing=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for exception processing.
The number of clock periods includes the time for all stacking, the vector
fetch and the fetch of the first two instruction words of the handler routine.

exception periods

address error 50(4/7)
bus error 50(4/7)
CHK instruction (trap taken) 44(5/3)+
Divide by Zero 42(5/3)
illegal instruction 34(4/3)
interrupt 44(5/3)*
privilege violation 34(4/3)
_____
RESET ** 40(6/0)
trace 34(4/3)
TRAP instruction 38(4/3)
TRAPV instruction (trap taken) 34(4/3)

+ add effective address calculation time
* the interrupt acknowledge cycle is assumed to take four
clock periods
_____ ____
** indicates the time from when RESET and HALT are first
sampled as negated to when instruction execution starts
</syntaxhighlight>

[[Category:Base system]]
[[Category:Code]]

68k instructions timings

2018-01-19T07:46:44Z

Hpman: /* Move Peripheral instructions */

Mirrored information from [[http://oldwww.nvg.ntnu.no/amiga/MC680x0_Sections/mc68000timing.HTML oldwww.nvg.ntnu.no]]

The number of bus '''r'''ead and '''w'''rite cycles are shown in parenthesis as (r/w). Any other cycles are internal.

In the following tables, the headings have the following meanings:
* An : Address register operand
* Dn : Data register operand
* ea : Operand specified by an effective address
* M : Memory effective address operand

To get the real execution time, multiply the total cycles count by 83.33ns ([[Clock|1/12MHz]]). An example is given in each section.

The [[68k interrupts|vertical blank]] lasts exactly 40 lines * 384 pixels * 2 cycles per pixel = 30720 cycles (2.56ms).

See [[optimization]].

=Effective address operand calculation=

This table lists the number of clock periods required to compute an instruction's effective address. It includes fetching of any extension words, the address computation, and fetching of the memory operand.

{|class="wikitable"
!Syntax||Adressing mode||B,W||L
|-
|Dn
|Data register direct
|class="green"|0(0/0)
|class="green"|0(0/0)
|-
|An
|Address register direct
|class="green"|0(0/0)
|class="green"|0(0/0)
|-
|(An)
|Address register indirect
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|-
|(An)+
|Address register indirect, post inc.
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|-
| -(An)
|Address register indirect, pre dec.
|class="yellow"|6(1/0)
|class="orange"|10(2/0)
|-
|d(An)
|Address register indirect, displacement
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|d(An,ix)
|Address register indirect, index
|class="orange"|10(2/0)
|class="red"|14(3/0)
|-
|xxx.w
|Absolute short
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|xxx.l
|Absolute long
|class="orange"|12(3/0)
|class="red"|16(4/0)
|-
|d(PC)
|PC with displacement
|class="yellow"|8(2/0)
|class="orange"|12(3/0)
|-
|d(PC,ix)
|PC with index
|class="yellow"|10(2/0)
|class="red"|14(3/0)
|-
|#xxx
|Immediate
|class="green"|4(1/0)
|class="yellow"|8(2/0)
|}

Notes:
* Pre-dec is slower than post-inc
* There are no write cycles involved in processing the effective address
* The size of the index register (ix) does not affect execution time

=Move instructions=

These following two tables indicate the number of clock periods for the move instruction. This data includes instruction fetch, operand reads, and operand writes.

==Byte and word==

Example: '''move.b (a0)+,$10201D''' (Byte (An)+ to xxx.L) takes 20 cycles.

{|class="wikitable"
!  || Dn || An || (An) || (An)+ || -(An) || d(An) || d(An,ix) || xxx.W || xxx.L
|-
!Dn
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|8(1/1)||class="green"|8(1/1)
|class="green"|8(1/1)||class="yellow"|12(2/1)||class="yellow"|14(2/1)||class="yellow"|12(2/1)||class="yellow"|16(3/1)
|-
!An
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|8(1/1)||class="green"|8(1/1)
|class="green"|8(1/1)||class="yellow"|12(2/1)||class="yellow"|14(2/1)||class="yellow"|12(2/1)||class="yellow"|16(3/1)
|-
!(An)
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|12(2/1)||class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|-
!(An)+
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|-
!-(An)
|class="green"|10(2/0)||class="green"|10(2/0)||class="yellow"|14(2/1)||class="yellow"|14(2/1)||class="yellow"|14(2/1)
|class="orange"|18(3/1)||class="orange"|20(4/1)||class="orange"|18(3/1)||class="orange"|22(4/1)
|-
!d(An)
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!d(An,ix)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|18(3/1)||class="orange"|18(3/1)||class="orange"|18(3/1)
|class="orange"|22(4/1)||class="red"|24(4/1)||class="orange"|22(4/1)||class="red"|26(5/1)
|-
!xxx.W
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!xxx.L
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|20(4/1)||class="orange"|20(4/1)||class="orange"|20(4/1)
|class="red"|24(5/1)||class="red"|26(5/1)||class="red"|24(5/1)||class="red"|28(6/1)
|-
!d(PC)
|class="yellow"|12(3/0)||class="yellow"|12(3/0)||class="yellow"|16(3/1)||class="yellow"|16(3/1)||class="yellow"|16(3/1)
|class="orange"|20(4/1)||class="orange"|22(4/1)||class="orange"|20(4/1)||class="red"|24(5/1)
|-
!d(PC,ix)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|18(3/1)||class="orange"|18(3/1)||class="orange"|18(3/1)
|class="orange"|22(4/1)||class="red"|24(4/1)||class="orange"|22(4/1)||class="red"|26(5/1)
|-
!#xxx
|class="green"|8(2/0)||class="green"|8(2/0)||class="yellow"|12(2/1)||class="yellow"|12(2/1)||class="yellow"|12(2/1)
|class="yellow"|16(3/1)||class="orange"|18(3/1)||class="yellow"|16(3/1)||class="orange"|20(4/1)
|}

The size of the index register (ix) does not affect execution time.

==Long==

Example: '''move.l $05012C,4(a1,d0)''' (Long xxx.L to d(An,ix)) takes 34 cycles.

{|class="wikitable"
!  || Dn || An || (An) || (An)+ || -(An) || d(An) || d(An,ix) || xxx.W || xxx.L
|-
!Dn
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|12(1/2)||class="green"|12(1/2)||class="green"|12(1/2)
|class="yellow"|16(2/2)||class="yellow"|18(2/2)||class="yellow"|16(2/2)||class="yellow"|20(3/2)
|-
!An
|class="green"|4(1/0)||class="green"|4(1/0)||class="green"|12(1/2)||class="green"|12(1/2)||class="green"|12(1/2)
|class="yellow"|16(2/2)||class="yellow"|18(2/2)||class="yellow"|16(2/2)||class="yellow"|20(3/2)
|-
!(An)
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|-
!(An)+
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|-
!-(An)
|class="yellow"|14(3/0)||class="yellow"|14(3/0)||class="orange"|22(3/2)||class="orange"|22(3/2)||class="orange"|22(3/2)
|class="orange"|26(4/2)||class="orange"|28(4/2)||class="orange"|26(4/2)||class="red"|30(5/2)
|-
!d(An)
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(6/2)
|-
!d(An,ix)
|class="yellow"|18(4/0)||class="yellow"|18(4/0)||class="orange"|26(4/2)||class="orange"|26(4/2)||class="orange"|26(4/2)
|class="red"|30(5/2)||class="red"|32(5/2)||class="red"|30(5/2)||class="red"|34(6/2)
|-
!xxx.W
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(6/2)
|-
!xxx.L
|class="yellow"|20(5/0)||class="yellow"|20(5/0)||class="orange"|28(5/2)||class="orange"|28(5/2)||class="orange"|28(5/2)
|class="red"|32(6/2)||class="red"|34(6/2)||class="red"|32(6/2)||class="red"|36(7/2)
|-
!d(PC)
|class="yellow"|16(4/0)||class="yellow"|16(4/0)||class="orange"|24(4/2)||class="orange"|24(4/2)||class="orange"|24(4/2)
|class="orange"|28(5/2)||class="red"|30(5/2)||class="orange"|28(5/2)||class="red"|32(5/2)
|-
!d(PC,ix)
|class="yellow"|18(4/0)||class="yellow"|18(4/0)||class="orange"|26(4/2)||class="orange"|26(4/2)||class="orange"|26(4/2)
|class="red"|30(5/2)||class="red"|32(5/2)||class="red"|30(5/2)||class="red"|34(6/2)
|-
!#xxx
|class="green"|12(3/0)||class="green"|12(3/0)||class="yellow"|20(3/2)||class="yellow"|20(3/2)||class="yellow"|20(3/2)
|class="orange"|24(4/2)||class="orange"|26(4/2)||class="orange"|24(4/2)||class="orange"|28(5/2)
|}

The size of the index register (ix) does not affect execution time.

=Standard instructions=

Example: '''add.w d3,a7''' (Word ea Dn + An) takes 8 cycles.

The number of clock periods shown in this table indicates the time required to perform the operations, store the results and read the next instruction. The total number of clock periods must be added respectively to those of the effective address calculation where indicated (+).

{|class="wikitable"
!  || Size || <ea>,An * || <ea>,Dn || Dn,<M>
|-
!rowspan=2|ADD
|B,W
|class="orange"|8(1/0)+||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
|class="yellow"|6(1/0)+**||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|-
!rowspan=2|AND
|B,W
| - ||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
| - ||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|-
!rowspan=2|CMP
|B,W
|class="yellow"|6(1/0)+||class="green"|4(1/0)+|| -
|-
|L
|class="yellow"|6(1/0)+||class="yellow"|6(1/0)+|| -
|-
!DIVS
| - || - ||class="red"|158(1/0)+|| -
|-
!DIVU
| - || - ||class="red"|140(1/0)+|| -
|-
!rowspan=2|EOR
|B,W
| - ||class="green"|4(1/0) ***||class="orange"|8(1/1) +
|-
|L
| - ||class="orange"|8(1/0) ***||class="red"|12(1/2) +
|-
!MULS
| - || - ||class="red"|70(1/0)+*|| -
|-
!MULU
| - || - ||class="red"|70(1/0)+*|| -
|-
!rowspan=2|OR
|B,W
| - ||class="green"|4(1/0) +**||class="orange"|8(1/1) +
|-
|L
| - ||class="yellow"|6(1/0) +**||class="red"|12(1/2) +
|-
!rowspan=2|SUB
|B,W
|class="orange"|8(1/0)+||class="green"|4(1/0)+||class="orange"|8(1/1)+
|-
|L
|class="yellow"|6(1/0)+**||class="yellow"|6(1/0)+**||class="red"|12(1/2)+
|}

<syntaxhighlight lang="text">
notes: + Add effective address calculation time
^ Word or long only
* Indicates maximum value
** The base time of six clock periods is increased to eight
if the effective address mode is register direct or
immediate (effective address time should also be added)
*** Only available effective address mode is data register direct

DIVS,DIVU - The divide algorithm used by the MC68000 provides less
than 10% difference between the best and the worst case
timings.
MULS,MULU - The multiply algorithm requires 38+2n clocks where
n is defined as:
MULU: n = the number of ones in the <ea>
MULS: n = concatenate the <ea> with a zero as the LSB;
n is the resultant number of 10 or 01 patterns
in the 17-bit source; i.e., worst case happens
when the source is $5555
</syntaxhighlight>

=Immediate instructions=

The number of clock periods periods shown in this table includes the time to fetch immediate operands, perform the operations, store the results and read the next operation. The total number of clock periods must be added respectively to those of the effective address calculation where indicated (+).

{|class="wikitable"
!  || Size || #,Dn || #,An || #,M
|-
!rowspan=2|ADDI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|ADDQ
|B,W
|class="green"|4(1/0)||class="yellow"|8(1/0)*||class="orange"|12(1/2)+
|-
|L
|class="yellow"|8(1/0)||class="yellow"|8(1/0)||class="orange"|12(1/2)+
|-
!rowspan=2|ANDI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(1/2)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/1)+
|-
!rowspan=2|CMPI
|B,W
|class="green"|8(2/0)|| - ||class="green"|8(2/0)+
|-
|L
|class="orange"|14(3/0)|| - ||class="yellow"|12(3/1)+
|-
!rowspan=2|EORI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!MOVEQ
|L
|class="green"|4(1/0)|| - || -
|-
!rowspan=2|ORI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|SUBI
|B,W
|class="green"|8(2/0)|| - ||class="yellow"|12(2/1)+
|-
|L
|class="orange"|16(3/0)|| - ||class="red"|20(3/2)+
|-
!rowspan=2|SUBQ
|B,W
|class="green"|4(1/0)||class="yellow"|8(1/0)*||class="yellow"|8(1/1)+
|-
|L
|class="yellow"|8(1/0)||class="yellow"|8(1/0)||class="orange"|12(1/2)+
|}

<syntaxhighlight lang="text">
+ Add effective address calculation time
* word only
</syntaxhighlight>

=Single operand instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the single operand
instructions. The number of clock periods and the number of read and write cycles
must be added respectively to those of the effective address calculation
where indicated.

instruction size register memory

CLR byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NBCD byte 6(1/0) 8(1/1) +
NEG byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NEGX byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NOT byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
Scc byte,false 4(1/0) 8(1/1) +
byte,true 6(1/0) 8(1/1) +
TAS # byte 4(1/0) 10(1/1) +
TST byte,word 4(1/0) 4(1/0) +
long 4(1/0) 4(1/0) +

+ add effective address calculation time
# This instruction should never be used on the Amiga as its invisiable
read/write cycle can disrupt system DMA.
</syntaxhighlight>

=Shift and rotate instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the shift and rotate
instructions. The number of clock periods and the number of read and write
cycles must be added respectively to those of the effective address
calculation where indicated.

instruction size register memory

ASR,ASL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
LSR,LSL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
ROR,ROL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
ROXR,ROXL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -

+ add effective address calculation time
n is the shift or rotate count
</syntaxhighlight>

=Bit manipulation instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods required for the bit
manipulation instructions. The number of clock periods and the number of read and
write cycles must be added respectively to those of the effective address
calculation where indicated. Dynamic: register, static: immediate.

instruction size dynamic static
register memory register memory
BCHG byte - 8(1/1) + - 12(2/1) +
long 8(1/0) * - 12(2/0) * -
BCLR byte - 8(1/1) + - 12(2/1) +
long 10(1/0) * - 14(2/0) * -
BSET byte - 8(1/1) + - 12(2/1) +
long 8(1/0) * - 12(2/0) * -
BTST byte - 4(1/0) + - 8(2/0) +
long 6(1/0) - 10(2/0) -

+ add effective address calculation time
* indicates maximum value
</syntaxhighlight>

=Conditional instructions=

{|class="wikitable"
!Mnemonic || Displacement || Branch taken || Not taken
|-
|rowspan=2|Bcc
|byte
|class="yellow"|10(2/0)||class="green"|8(1/0)
|-
|word
|class="yellow"|10(2/0)||class="orange"|12(1/0)
|-
|rowspan=2|BRA
|byte
|class="yellow"|10(2/0)
|
|-
|word
|class="yellow"|10(2/0)
|
|-
|rowspan=2|BSR
|byte
|class="red"|18(2/2)
|
|-
|word
|class="red"|18(2/2)
|
|-
|rowspan=2|DBcc
|cc true
|
|class="orange"|12(2/0)
|-
|cc false
|class="yellow"|10(2/0)
|class="orange"|14(3/0)
|}

=JMP, JSR, LEA, PEA and MOVEM instructions=

<syntaxhighlight lang="text">
This Table indicates the number of clock periods required for the jump,
jump-to-subroutine, load effective address, push effective address and
move multiple registers instructions.

instr size (An) (An)+ -(An) d(An)
JMP - 8(2/0) - - 10(2/0)
JSR - 16(2/2) - - 18(2/2)
LEA - 4(1/0) - - 8(2/0)
PEA - 12(1/2) - - 16(2/2)
MOVEM word 12+4n 12+4n - 16+4n
M->R (3+n/0) (3+n/0) - (4+n/0)
long 12+8n 12+8n - 16+8n
(3+2n/0) (3+2n/0) - (4+2n/0)
MOVEM word 8+4n - 8+4n 12+4n
R->M (2/n) - (2/n) (3/n)
long 8+8n - 8+8n 12+8n
(2/2n) - (2/2n) (3/2n)

instr size d(An,ix)+ xxx.W xxx.L d(PC) d(PC,ix)*
JMP - 14(3/0) 10(2/0) 12(3/0) 10(2/0) 14(3/0)
JSR - 22(2/2) 18(2/2) 20(3/2) 18(2/2) 22(2/2)
LEA - 12(2/0) 8(2/0) 12(3/0) 8(2/0) 12(2/0)
PEA - 20(2/2) 16(2/2) 20(3/2) 16(2/2) 20(2/2)
MOVEM word 18+4n 16+4n 20+4n 16+4n 18+4n
M->R (4+n/0) (4+n/0) (5+n/0) (4+n/0) (4+n/0)
long 18+8n 16+8n 20+8n 16+8n 18+8n
(4+2n/0) (4+2n/0) (5+2n/0) (4+2n/0) (4+2n/0)
MOVEM word 14+4n 12+4n 16+4n - -
R->M (3/n) (3/n) (4/n) - -
long 14+8n 12+8n 16+8n - -
(3/2n) (3/2n) (4/2n) - -

n is the number of registers to move
* is the size of the index register (ix) does not affect the instruction's
execution time
</syntaxhighlight>

=Multi-precision instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the multi-precision
instructions. The number of clock periods includes the time to fetch both
operands, perform the operations, store the results and read the next
instructions.

instruction size op Dn,Dn op M,M

ADDX byte,word 4(1/0) 18(3/1)
long 8(1/0) 30(5/2)
CMPM byte,word - 12(3/0)
long - 20(5/0)
SUBX byte,word 4(1/0) 18(3/1)
long 8(1/0) 30(5/2)
ABCD byte 6(1/0) 18(3/1)
SBCD byte 6(1/0) 18(3/1)
</syntaxhighlight>

=Miscellaneous instructions=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for the following
miscellaneous instructions. The number of clock periods and plus the number
of read and write cycles must be added to those of the effective address
calculation where indicated.

instruction size register memory

ANDI to CCR byte 20(3/0) -
ANDI to SR word 20(3/0) -
CHK - 10(1/0) + -
EORI to CCR byte 20(3/0) -
EORI to SR word 20(3/0) -
ORI to CCR byte 20(3/0) -
ORI to SR word 20(3/0) -
MOVE from SR - 6(1/0) 8(1/1)+
MOVE to CCR - 12(1/0) 12(1/0)+
MOVE to SR - 12(1/0) 12(1/0)+
EXG - 6(1/0) -
EXT word 4(1/0) -
long 4(1/0) -
LINK - 16(2/2) -
MOVE from USP - 4(1/0) -
MOVE to USP - 4(1/0) -
NOP - 4(1/0) -
RESET - 132(1/0) -
RTE - 20(5/0) -
RTR - 20(5/0) -
RTS - 16(4/0) -
STOP - 4(0/0) -
SWAP - 4(1/0) -
TRAPV (No Trap) - 4(1/0) -
UNLK - 12(3/0) -

+ add effective address calculation time
</syntaxhighlight>

=Move Peripheral instructions=

<syntaxhighlight lang="text">
instruction size register->memory memory->register

MOVEP word 16(2/2) 16(4/0)
long 24(2/4) 24(6/0)
</syntaxhighlight>

=Exception processing=

<syntaxhighlight lang="text">
This table indicates the number of clock periods for exception processing.
The number of clock periods includes the time for all stacking, the vector
fetch and the fetch of the first two instruction words of the handler routine.

exception periods

address error 50(4/7)
bus error 50(4/7)
CHK instruction (trap taken) 44(5/3)+
Divide by Zero 42(5/3)
illegal instruction 34(4/3)
interrupt 44(5/3)*
privilege violation 34(4/3)
_____
RESET ** 40(6/0)
trace 34(4/3)
TRAP instruction 38(4/3)
TRAPV instruction (trap taken) 34(4/3)

+ add effective address calculation time
* the interrupt acknowledge cycle is assumed to take four
clock periods
_____ ____
** indicates the time from when RESET and HALT are first
sampled as negated to when instruction execution starts
</syntaxhighlight>

[[Category:Base system]]
[[Category:Code]]

Todo/Mysteries

2017-06-26T15:17:35Z

Hpman:

==Housekeeping==
* Merge Sprite_scaling with Sprite_shrinking
* Rename GPU to VDC everywhere ? Or VDP ? LSPC isn't really a processor. Sorry :/
* Rename BIOS to system ROM everywhere (done ?)
* Use 3rd parameter of Sig template (signal polarity)
* Use Chipname, Reg, Sig, BR templates

==Useful==
* Tooltip extension for registers ?
* Check everything in [[Meg count]]. Add links to game pages.
* Add pin numbers on [[AES cartridge pinout]]
* Add on to [[How to start]] page
* Tutorials
* Change DEFINE names (and register names ?) to the ones used in the AoF source code
* Memory chip pinouts
* Finish PRO chipset pinouts !
* M1 and S1 ROM speeds
* CD I/O ERROR 0001 0002 0003 ?
* CRC32 of all known ROMs/ISOs from MAME's neogeo.inc
* Add more jumper configs
* Memory card stuff (format, banks...)
* neo-mga on mv1a + PALs info
* Chip functions for each kind of board (even discrete logic)

==Trivia==
* Add links to TCRF pages for the debug DIPs of each game
* CMC fix bankswitching: how/when is vram bank info sent to the cartridge?
* Recent security chips info (SMA, PVC...)
* Neo cd chip pinouts (not very useful)
* Are the two missing FM channels from the YM2610 actually off the die or just disabled?

==Analysis / mysteries==
* Why does the L0 ROM need an output buffer ?
* Loading time graphs for all CD games, is MESS reliable enough ? (no)
* Details on CD registers
* CDDA playback (needs more research in CD system rom)
* Dump LC98000 version Neo CD system rom
* [[LC8953]]/98000 microcode (note: Sanyo tech support has nothing left except publicly available brief sheet)

==Verify==
* Check [[Clock]] distribution diagram, especially on cart edge

FM

2017-06-26T15:12:54Z

Hpman:

The FM ('''F'''requency '''M'''odulation) is part of the {{Chipname|YM2610}} sound chip. It provides '''4 channels''', each having their own set of 4 operators, panning and amplitude values. It's the most used way of producing music in games.

=Common registers=

{|class="wikitable"
!Address (Z80 port 4)
!Data (Z80 port 5)
|
|-
|$21
|{{8BitRegister|?|8}}
| Test register. Ignore or set to $00 for normal operation.
|-
|$22
|{{8BitRegister|-|4|On|1|Control|3}}
| LFO control and frequency (see below).
|-
|$28
|{{8BitRegister|Slot|4|-|1|Channel|3|}}
| Key On/Off for each channel.
|}

LFO frequency values are as follows:
*0 – 3.98Hz
*1 – 5.56Hz
*2 – 6.02Hz
*3 – 6.37Hz
*4 – 6.88Hz
*5 – 9.63Hz
*6 – 48.1Hz
*7 – 72.2Hz

Channel numbering:
{|class="wikitable"
!FM Channel
!Binary Code
|-
| CH1
| 001
|-
| CH2
| 010
|-
| CH3
| 101
|-
| CH4
| 110
|}
This strange numbering seems to be due to the fact YM2610 is a YM2610B with 2 removed FM channels (000 and 100).

=Channel registers=

Depending on which channel you want to write to, the {{Chipname|Z80}} ports used are different:
* Channels 1 & 2: Ports 4/5
* Channels 3 & 4: Ports 6/7

{|class="wikitable"
!colspan=4|Address||colspan=4|Data||rowspan=3|
|-
|CH1||CH2||CH3||CH4||CH1||CH2||CH3||CH4
|-
|colspan=2|Port 4||colspan=2|Port 6||colspan=2|Port 5||colspan=2|Port 7
|-
|$A1||$A2||$A1||$A2
|colspan=4|{{8BitRegister|F-Num 1|8}}
|F-Numbers and Block (1/2)
|-
|$A5||$A6||$A5||$A6
|colspan=4|{{8BitRegister|-|2|Block|3|F-Num 2|3}}
|F-Numbers and Block (2/2) (must set this first)
|-
|$B1||$B2||$B1||$B2
|colspan=4|{{8BitRegister|-|2|FB|3|ALGO|3}}
|Feedback (FB) and Algorithm (ALGO)
|-
|$B5||$B6||$B5||$B6
|colspan=4|{{8BitRegister|L|1|R|1|AMS|2|-|1|PMS|3}}
|Left (L)/Right (R) output, AM Sense (AMS), and PM Sense (PMS)
|}

2CH mode additional operator frequencies:
* OP1 frequency is stored in the usual CH2 frequency registers ($A2/$A6)
* write to Z80 ports 4/5

{|class="wikitable"
!colspan=3|Address||colspan=4|Data||rowspan=2|
|-
|OP2||OP3||OP4||colspan="4"|
|-
|$A8||$A9||$AA
|colspan=4|{{8BitRegister|2CH * F-Num 1|8}}
|2CH mode F-Num LSB
|-
|$AC||$AD||$AE
|colspan=4|{{8BitRegister|-|2|2CH * Block|3|2CH * F-Num 2|3}}
|2CH mode F-Num MSB & Block (must set this first)
|}

=Operator registers=
The ranges given for the address represent all of the parameter values. Each channel's operators are laid out as follows:

{|class="wikitable"
! Operator || 1 || 2 || 3 || 4
|-
! Channels 1, 3
| $x1 || $x5 || $x9 || $xD
|-
! Channels 2, 4
| $x2 || $x6 || $xA || $xE
|}

{|class="wikitable"
!colspan=4|Address||colspan=4|Data||rowspan=3|
|-
|CH1||CH2||CH3||CH4||CH1||CH2||CH3||CH4
|-
|colspan=2|Port 4||colspan=2|Port 6||colspan=2|Port 5||colspan=2|Port 7
|-
|colspan=4|$31-$3E
|colspan=4|{{8BitRegister|-|1|DT|3|MUL|4}}
|Detune (DT) and Multiple (MUL)
|-
|colspan=4|$41-$4E
|colspan=4|{{8BitRegister|-|1|Total Level|7|}}
|Total Level (Volume)
|-
|colspan=4|$51-$5E
|colspan=4|{{8BitRegister|KS|2|-|1|AR|5}}
|Key Scale (KS) and Attack Rate (AR)
|-
|colspan=4|$61-$6E
|colspan=4|{{8BitRegister|AM|1|-|2|DR|5}}
|AM On (AM) and Decay Rate (DR)
|-
|colspan=4|$71-$7E
|colspan=4|{{8BitRegister|-|3|SR|5}}
|Sustain Rate (SR)
|-
|colspan=4|$81-$8E
|colspan=4|{{8BitRegister|SL|4|RR|4}}
|Sustain Level (SL) and Release Rate (RR)
|-
|colspan=4|$91-$9E
|colspan=4|{{8BitRegister|-|4|SSG-EG|4}}
|Envelope generator (not to be confused with the [[SSG]] one)
|}

[[Category:Audio system]]

ADPCM

2017-06-26T15:11:05Z

Hpman: lolno

'''A'''daptive '''D'''ifferential '''P'''ulse '''C'''ode '''M'''odulation is a lossy audio compression algorithm. It is essentially PCM with dynamic quantizing step adaptation. See [[https://en.wikipedia.org/wiki/Adaptive_differential_pulse-code_modulation Wikipedia article]] for more general informations.

The NeoGeo's {{Chipname|YM2610}} uses this format for samples stored in the [[V ROM]]s or [[PCM file]]s. Each sample is coded in 4 bits and approximately reconstituted as 12 or 16 bits during playback.

Note that the Yamaha ADPCM format is different from the common IMA and Microsoft ADPCM formats. See [[ADPCM codecs]] for encoding and decoding tools.

The NeoGeo CD can't use ADPCM-B.

=Status register=

{| class="regdef"
|'''Address (Z80 port 4)'''
|'''Data (Z80 port 5)'''
|Value on [[reset]]
|-
|$1C
|{{8BitRegister|B|1|-|1|A6|1|A5|1|A4|1|A3|1|A2|1|A1|1|}}
|$00
|}

Each bit corresponds to an ADPCM channel.

* Write 1 to reset and mask selected flag
* Write 0 to unmask selected flag

Masking a flag will prevent it from being raised when a channel reaches its end address. This means it is required to write 1 to clear the flag, then 0 to keep it active.

Flags must be manually cleared, playing a new sample on the channel won't clear it and the channel will stay silent.

=ADPCM-A=
The ADPCM-A part has '''6 channels''' with a '''fixed''' playback frequency of: 8MHz ({{Sig|8M|8M}}) / 12 (prescaler) / 6 clocks per access / 6 channels = ~'''18.5185kHz'''.

Audio is compressed as 4bit per sample and played back as '''12bit'''.

==Registers==

{| class="regdef"
|'''Address (Z80 port 6)'''
|'''Data (Z80 port 7)'''
|Value on [[reset]]
|
|-
|$00
|{{8BitRegister|Dump|1|-|1|CH6 ON|1|CH5 ON|1|CH4 ON|1|CH3 ON|1|CH2 ON |1|CH1 ON|1}}
|$00
|'Dump' is the key on/off bit. Write 0 to start playing specified channels and 1 to stop playing.
|-
|$01
|{{8BitRegister|-|2|Master volume|6}}
|$00
|Actually an attenuator, $3F is the loudest.
|-
|$02
|{{8BitRegister|?|8}}
|$00 ?
|Test register. Ignore or set to $00 for normal operation.
|-
|$08~$0D (one for each channel)
|{{8BitRegister|L|1|R|1|-|1|Channel volume|5}}
|$00
|Actually an attenuator, $1F is the loudest. L/R routes the output to the left and/or right channels.
|-
|$10~$15 (one for each channel)
|{{8BitRegister|Sample's start address/256 LSB|8}}
|$00
|rowspan="4"|All ADPCM addresses must match a 256-byte boundary (bits 0~7 = 0)
|-
|$18~$1D (one for each channel)
|{{8BitRegister|Sample's start address/256 MSB|8}}
|$00
|-
|$20~$25 (one for each channel)
|{{8BitRegister|Sample's stop address/256 LSB|8}}
|$00
|-
|$28~$2D (one for each channel)
|{{8BitRegister|Sample's stop address/256 MSB|8}}
|$00
|}

=ADPCM-B=
The ADPCM-B part only has '''1 channel''', but the playback frequency can be set from '''1.85kHz''' to: 8MHz ({{Sig|8M|8M}}) / 2 / 12 (prescaler) / 6 clocks per access = ~'''55.555kHz'''.

Audio is compressed as 4bit per sample and played back as '''16bit'''.

==Registers==

See [[ADPCM]] for details on this part's operation.

{| class="regdef"
|'''Address (Z80 port 4)'''
|'''Data (Z80 port 5)'''
|Value on [[reset]]
|
|-
|$10
|{{8BitRegister|Start|1|-|2|Repeat|1|-|3|Reset|1|}}
|$00
|Repeat: loop when end address is reached. Reset: clears Start and Repeat.
|-
|$11
|{{8BitRegister|L|1|R|1|-|6|}}
|$00
|Left/Right channel output
|-
|$12
|{{8BitRegister|Sample's start address/256 LSB|8}}
|?
|rowspan="4"|All ADPCM addresses must match a 256-byte boundary (bits 0~7 = 0)
|-
|$13
|{{8BitRegister|Sample's start address/256 MSB|8}}
|?
|-
|$14
|{{8BitRegister|Sample's stop address/256 LSB|8}}
|?
|-
|$15
|{{8BitRegister|Sample's stop address/256 MSB|8}}
|?
|-
|$19
|{{8BitRegister|Delta-N (L)|8}}
|?
|rowspan="2"|Playback rate is f = 8M / 12 / 12 / (65535 / Delta-N) = 55555 * (Delta-N / 65535) Hz
|-
|$1A
|{{8BitRegister|Delta-N (H)|8}}
|?
|-
|$1B
|{{8BitRegister|ADPCM-B channel volume|8}}
|?
|Loudest is $FF
|}

=Format=

Requirements:
* ADPCM-A Samples can be any size from '''256 bytes to 1MiB, in 256 bytes steps'''. They must be padded with silence.
* ADPCM-A Samples '''cannot cross 1MB pages''' (the 4 MSBs of the end address must be equal those of the start address). Be sure to organize/map your data correctly.
* ADPCM-B Samples can be any size from '''256 bytes to 16MiB, in 256 bytes steps'''. They must be padded with silence.

=Drifting=

[[File:Adpcm_drift.png|thumb|Decoded ADPCM audio slowly drifting upwards and hitting a chunk of garbage data.]]

Since the codec is based on the difference between samples, it is prone to drifting if buggy codecs or bad data are used.

Clean data should always produce a zero-centered signal when decoded.

If a cartridge has contact issues for example, the YM2610 will read corrupt data and the decoder will make the output value randomly "jump" everywhere, resulting in a horrendous screeching sound even if only one data line is disconnected.

Many V ROMs contain garbage data between valid samples. Consequently, if the dump is decoded from start to end, the decoder will take the garbage data into account and the decoded audio output will either drift slowly or become brutally offset. This isn't an issue when the game is running because the YM2610 resets the decoder each time a sample is played (also, the [[sound driver]] shouldn't be playing garbage data).

[[Category:Audio system]]

YM2610 registers

2017-06-24T18:23:29Z

Hpman:

=Timers=

See [[YM2610 timers]].

=SSG part=

See [[SSG]] for details on this part's operation.

=FM part=

See [[FM]] for details on this part's operation.

=ADPCM part=

See [[ADPCM]] for details on this part's operation.

=Reading=

The only writable registers that can also be read are the SSG ones.
To read register X, write X to Z80 port 4, then read Z80 port 5.

{| class="regdef"
|'''Z80 port'''
|'''Data'''
|Notes
|-
|$04
|{{8BitRegister|Busy|1|-|5|Timer B flag|1|Timer A flag|1}}
|When a timer expires and IRQ is enabled for the timer, the respective flag is set.
|-
|$05
|{{8BitRegister|SSG register data|8}}
|Attempting to read non-SSG registers will return 0.
|-
|$06
|{{8BitRegister|ADPCM-B end|1|-|1|CH6 end|1|CH5 end|1|CH4 end|1|CH3 end|1|CH2 end|1|CH1 end|1}}
|When a channel has reached the end address and stops, the respective bit is set (unless masked).
|-
|$07
|Not implemented
|Always returns $00
|-
|}

[[Category:Code]]
[[Category:Audio system]]

YM2610

2017-06-24T02:30:25Z

Hpman: Noise can be mixed with SSG A/B/C but isn't a channel

{{ChipInfo
|picture=Cd2_ym2610.jpg
|pkg=SDIP64
|manu=yamaha
|date=1990 ?
|gates=
|used_on=All systems
}}

The YM2610 is a sound synthesis and playback chip made by Yamaha, found in all versions of the NeoGeo hardware.
It was later merged with other chips in {{Chipname|NEO-YSA}} and {{Chipname|NEO-YSA2}}, which are used on some versions of the NeoGeo CD, the [[CDZ]], the {{PCB|MV1C}} and on [[ROM-Only boards]].

The YM2610 requires a {{Chipname|YM3016}} external DAC (Digital to Analog Converter) chip for the [[FM]] and [[ADPCM]] sounds. The only direct analog output is for the [[SSG]] sounds. Both analog outputs are then mixed together before amplification.

The original YM2610 chip gets quite warm during normal operation.

=Parts=
Sound can come from 3 different generators, each having their own channels:

* [[SSG]] (Software Sound Generator): 3 channels
* [[FM]] (Frequency Modulation): 4 channels
* [[ADPCM]] (Sample playback): 7 channels

Providing 14 channels in total.

=Programming=

See [[Z80/YM2610 interface]] and [[YM2610 registers]].

=Pinout=

[[File:Ym2610_pinout.png|right|width=400px]]

* {{Sig|SDD|SDD*}}: {{Chipname|Z80}} data bus
* {{Sig|RAD|RAD*}}: ADPCM-A multiplexed address/data
* {{Sig|RMPX|RMPX}}: ADPCM-A address/data select
* {{Sig|ROE|ROE}}: APDCM-A data output enable
* {{Sig|RA|RA*}}: ADPCM-A address
* {{Sig|ANA|ANA}}: SSG analog output
* {{Sig|SH1|SH1}}: {{Chipname|YM3016}} latch 1
* {{Sig|SH2|SH2}}: YM3016 latch 2
* {{Sig|OP0|OP0}}: YM3016 serial data
* {{Sig|IC|IC}}: Reset
* {{Sig|PA|PA*}}: ADPCM-B address
* {{Sig|POE|POE}}: ADPCM-B data output enable
* {{Sig|PMPX|PMPX}}: ADPCM-B address/data select
* {{Sig|PAD|PAD*}}: ADPCM-B multiplexed address/data
* {{Sig|IRQ|IRQ}}: Interrupt request output
* {{Sig|CS|CS}}: Chip select
* {{Sig|WR|WR}}: Write
* {{Sig|RD|RD}}: Read
* {{Sig|SDA|A*}}: Z80 address bus
* {{Sig|PHI M|PHI M}}: [[Clock]] input
* {{Sig|PHI S|PHI S}}: YM3016 clock output

 

=Multiplexed PCM bus=

Access to the [[V ROM]]s are made via partly multiplexed buses. See [[YM2610 bus timing]] for more details about the access sequences.

The {{Sig|SDRMPX|SDRMPX}} and {{Sig|SDPMPX|SDPMPX}} signals are used to drive latches or the {{Chipname|PCM}} chip in [[cartridges]] to demultiplex address and data. When {{Sig|SDROE|SDROE}} or {{Sig|SDPOE|SDPOE}} goes low, SDRAD* and SDPAD* are tristated so that the V ROMs can output data.

* SDRA* for ADPCM-A

{|class="wikitable"
!SDRMPX
!colspan="8"|SDRAD*
!colspan="6"|SDRA*
|-
|
!0
!1
!2
!3
!4
!5
!6
!7
!8
!9
!20
!21
!22
!23
|-
|Low to high
|0
|1
|2
|3
|4
|5
|6
|7
|8
|9
|?
|?
|?
|?
|-
|High to low
|10
|11
|12
|13
|14
|15
|16
|17
|18
|19
|20
|21
|22
|23
|}

* SDPA* for ADPCM-B

{|class="wikitable"
!SDPMPX
!colspan="8"|SDPAD*
!colspan="6"|SDPA*
|-
|
!0
!1
!2
!3
!4
!5
!6
!7
!8
!9
!10
!11
|-
|Low to high
|0
|1
|2
|3
|4
|5
|6
|7
|8
|9
|10
|11
|-
|High to low
|12
|13
|14
|15
|16
|17
|18
|19
|20
|21
|22
|23
|}

24 address bits allow for 16MiB max V ROMs (without bankswitching).

=Trivia=

* A lot of games have several recordings of the same instrument playing different notes, rather than having only one sample and change the ADPCM-B playback frequency to vary its pitch. (Trumpet in [[Viewpoint]], electric guitar in [[Super Sidekicks]]). Why ?
* Nazca's [[sound driver]]s are able to use the SSG channels for music playback. (Maybe all can ?)

=Datasheet=

Japanese datasheet: [[http://www.ajworld.net/neogeodev/ym2610am_en.html ajworld.net]]

Incomplete/translated datasheet: [[http://furrtek.free.fr/noclass/neogeo/YM2610.pdf YM2610.pdf]]

[[Category:Chips]]
[[Category:Audio system]]