NeoGeo Development Wiki - User contributions [en]

User:Kyuusaku

2017-03-15T01:06:02Z

Kyuusaku: Blanked the page

Supergun

2017-03-15T01:05:14Z

Kyuusaku:

'''Supergun''' ("Control Box" in Japan) is a strange name for devices that allows using arcade boards (not only MVS) as consoles. Many different models can be bought as finished products or kits. (Flawed) schematics can also be found.

=Power supply=

Most often, the supergun doesn't supply [[power supply|power]] to the board itself but provides a standard socket to plug an off-the-shelf computer power supply.

=A/V signal adaptation=

Video output (RGBS) from the JAMMA edge is high-level and non-uniform impedance. Very-high impedance, video-bandwidth amplifiers/buffers are necessary to prevent distortion and provide a steady impedance match for 75 ohm TV inputs. Wiring JAMMA video outputs directly to a SCART cable will produce a very dark (attenuated RGB voltage) picture. The picture will also have non-linear distortion because the [[video DAC]] cannot source enough current into the TV's load for most colors.

Audio output is low-impedance and (relatively) high-level for direct connection to 8 ohm speakers. An attenuation circuit ("line-out converter") should be used to drive line-level TV audio inputs. Otherwise the signal's large swing will fall outside the amplifier's linear range and could potentially damage an unprotected input stage.

The Neo Geo, amongst most arcade systems, outputs a malformed sync signal without proper serration or equalization pulses. This will not noticeably affect operation most TVs as the horizontal and vertical oscillator aberrations will typically fall within blanked video. Like video, JAMMA sync outputs are high-level and high-impedance. To drive a TV or broadcast monitor's sync input, the JAMMA signal should be buffered, attenuated and impedance-matched. Because the signal is bi-level, a biased logic gate buffer is sufficient. The attenuation/impedance match circuit should have a bandwidth >500 kHz to preserve sync's edges; a typical single-resistor solution forming a voltage divider with the 75 ohm terminator may not be acceptable.

=Video output conversion=

RGBS can be converted to Y/C or CVBS. Conversion to HDMI is way more complex and is often done by a separate device.

PAL/NTSC CVBS burst generators ? Component output ?

=Joypad signals translation=

A supergun may accept different kinds of joypads (Genesis, SNES, ...) and translate the serial signals to straight parallel signals.

=I/O breakout=

Special I/O for arcade cabs can be broken out to solderable pads, screw terminals... Coin-in inputs are often connected to momentary switches.

=Voltage control=

Voltmeters and ammeters can be hooked up between the PSU and board to measure voltage and current.

[[Category:Cartridge systems]]

Supergun

2017-03-15T01:03:31Z

Kyuusaku: /* Impedance adaptation */

'''Supergun''' is a strange name for devices that allows using arcade boards (not only MVS) as consoles. Many different models can be bought as finished products or kits. (Flawed) schematics can also be found.

=Power supply=

Most often, the supergun doesn't supply [[power supply|power]] to the board itself but provides a standard socket to plug an off-the-shelf computer power supply.

=A/V signal adaptation=

Video output (RGBS) from the JAMMA edge is high-level and non-uniform impedance. Very-high impedance, video-bandwidth amplifiers/buffers are necessary to prevent distortion and provide a steady impedance match for 75 ohm TV inputs. Wiring JAMMA video outputs directly to a SCART cable will produce a very dark (attenuated RGB voltage) picture. The picture will also have non-linear distortion because the [[video DAC]] cannot source enough current into the TV's load for most colors.

Audio output is low-impedance and (relatively) high-level for direct connection to 8 ohm speakers. An attenuation circuit ("line-out converter") should be used to drive line-level TV audio inputs. Otherwise the signal's large swing will fall outside the amplifier's linear range and could potentially damage an unprotected input stage.

The Neo Geo, amongst most arcade systems, outputs a malformed sync signal without proper serration or equalization pulses. This will not noticeably affect operation most TVs as the horizontal and vertical oscillator aberrations will typically fall within blanked video. Like video, JAMMA sync outputs are high-level and high-impedance. To drive a TV or broadcast monitor's sync input, the JAMMA signal should be buffered, attenuated and impedance-matched. Because the signal is bi-level, a biased logic gate buffer is sufficient. The attenuation/impedance match circuit should have a bandwidth >500 kHz to preserve sync's edges; a typical single-resistor solution forming a voltage divider with the 75 ohm terminator may not be acceptable.

=Video output conversion=

RGBS can be converted to Y/C or CVBS. Conversion to HDMI is way more complex and is often done by a separate device.

PAL/NTSC CVBS burst generators ? Component output ?

=Joypad signals translation=

A supergun may accept different kinds of joypads (Genesis, SNES, ...) and translate the serial signals to straight parallel signals.

=I/O breakout=

Special I/O for arcade cabs can be broken out to solderable pads, screw terminals... Coin-in inputs are often connected to momentary switches.

=Voltage control=

Voltmeters and ammeters can be hooked up between the PSU and board to measure voltage and current.

[[Category:Cartridge systems]]

File:NEO-AES analog audio (2 of 2).png

2012-08-05T08:11:07Z

Kyuusaku:

File:NEO-AES analog audio (1 of 2).png

2012-08-05T08:11:07Z

Kyuusaku:

File:Ct0.zip

2012-06-29T10:01:06Z

Kyuusaku: CT0 logic

CT0 logic

User:Kyuusaku

2012-06-28T02:30:06Z

Kyuusaku:

June '12 update: I haven't worked on Neo stuff for a very long time :/
----
<nowiki>Projects:

MVS converter (done, needs PCB)
AES schematics (~75%)
MV4 schematics (~30%)
original ASIC RE (~50%)
PCMify discrete V ROM titles (0%)
crack SNK-9201, weird mirroring, protected games (0%)
LLE emulator

aim: calpis0
</nowiki>

Talk:Bootleg MVS boards

2012-06-28T00:59:47Z

Kyuusaku:

These are the only clones I've seen, but if any more exist I doubt they will entirely use 74 series for the ZMC2/CT0 logic, at ~16 chips (some uncommon) it would be too expensive and difficult to initially design.

It looks like the "Goldstar" version has the logic in the 4x 22V10, 1x 16V8, 4x '153 and maybe the neighboring '32. It's not very efficient because they aren't using the 22V10 to its potential, they could have eliminated the '153 and also eliminated the 16V8 with minimal 74 series.

The "Gobit" must have it in the "ECW" chip which appears to be a mask clone of the CT0.
--[[User:Kyuusaku|Kyuusaku]] 19:10, 26 June 2012 (CEST)

Curious to see your ZMC2 logic, even though I know releasing it can be an issue as it would be the key to make AES boards. My (tested) schematic has: 2 inverters, one AND, 4*8 bit latches, 3 XORs, a 74163 counter clocked by 12M, 4 74153 4-to-1 data selectors, 2 74157 2-to-1 selectors to handle EVEN and 2 4-input OR gates for DOTA/DOTB. I know there's something made a bit too complicated with the polarity of the clocking edge but... I works about right.
Tried it on a EPM420 CPLD, works on the LSPC/B1 AES but glitches on PRO-C0/B0 AESes.

Wonder where's the YM2610 on that "Gobit" board then, was there a SOIC/TQFP version of it made maybe slapped on the back side ? --[[User:Furrtek|Furrtek]] 01:14, 28 June 2012 (CEST)

Yeah you're right, I'm not sure about the YM2610, it could be in the PLCC package and the CT0 could be integrated into the C0, though it would be difficult to find so many free inputs for a CT0. I also don't see the DAC chip. It seems unlikely they'd be able to integrate the YM2610 as easily however.

I'll share the logic soon, I haven't done anything with it in 2 years so it's time.--[[User:Kyuusaku|Kyuusaku]] 02:59, 28 June 2012 (CEST)

User:Kyuusaku

2012-06-26T17:38:24Z

Kyuusaku:

June '12 update: I haven't worked on Neo stuff for a very long time :/
----
<nowiki>Projects:

MVS converter (done, needs PCB)
AES schematics (~75%)
MV4 schematics (~30%)
original ASIC RE (~50%)
PCMify discrete V ROM titles (0%)
crack SNK-9201, weird mirroring games (0%)
LLE emulator

aim: calpis0
msn: calpis0(at)hotmail
</nowiki>

Talk:Bootleg MVS boards

2012-06-26T17:11:58Z

Kyuusaku:

Talk:Bootleg MVS boards

2012-06-26T17:10:51Z

Kyuusaku: Created page with "These are the only clones I've seen, but if any more exist I doubt they will entirely use 74 series for the ZMC2/CT0 logic, at ~16 chips (some uncommon) it would be too expens..."

These are the only clones I've seen, but if any more exist I doubt they will entirely use 74 series for the ZMC2/CT0 logic, at ~16 chips (some uncommon) it would be too expensive.

It looks like the "Goldstar" version has the logic in the 4x 22V10, 1x 16V8, 4x '153 and maybe the neighboring '32. It's not very efficient because they aren't using the 22V10 to its potential, they could have eliminated the '153 and also eliminated the 16V8 with minimal 74 series.

The "Gobit" must have it in the "ECW" chip which appears to be a mask clone of the CT0.
--[[User:Kyuusaku|Kyuusaku]] 19:10, 26 June 2012 (CEST)

User:Kyuusaku

2012-03-17T06:47:00Z

Kyuusaku:

<nowiki>Projects:

MVS converter (done)
AES schematics (~75%)
MV4 schematics
ASIC RE (~50%)
PCMify discrete V ROM titles
crack SNK-9201, weird mirroring games
LLE emulator

aim: calpis0
</nowiki>

General specifications

2012-03-17T03:36:21Z

Kyuusaku:

*CPU: '''68HC000''' at 12 MHz and '''Z80A''' at 4 MHz
*BIOS ROM: '''128 KiB'''
*Max. cart ROM: '''2 MiB''' (without bankswitching)
*Work RAM: '''64 KiB'''
*Max FIX tileset: '''128 KiB''' (without bankswitching)
*Max ADPCM-A ROM: '''16 MiB'''
*Max ADPCM-B ROM: '''16 MiB'''
*Max usable Z80 ROM: '''62 KiB''' (without bankswitching)
*Max sprite tileset: '''128 MiB'''
*Max sprites: '''380'''
*Max sprites per line: '''96'''
*VRAM: '''64 KiB + 4 KiB'''
*Colors: '''Max 3841 simultaneous''' colors out of '''65536''' (15 colors * 256 palettes + background color)
*Sound: '''4 FM, 7 ADPCM, 3 PSG channels'''

[[Category:Base system]]

General specifications

2012-03-17T03:34:54Z

Kyuusaku:

*CPU: '''68HC000''' at 12 MHz and '''Z80A''' at 4 MHz
*BIOS ROM: '''128 KiB'''
*Max. cart ROM: '''2 MiB''' (without bankswitching)
*Work RAM: '''64 KiB'''
*Max FIX tileset: '''128 KiB''' (without bankswitching)
*Max V1 ROM: '''16 MiB'''
*Max V2 ROM: '''16 MiB'''
*Max usable Z80 ROM: '''62 KiB''' (without bankswitching)
*Max sprite tileset: '''128 MiB'''
*Max sprites: '''380'''
*Max sprites per line: '''96'''
*VRAM: '''64 KiB + 4 KiB'''
*Colors: '''Max 3841 simultaneous''' colors out of '''65536''' (15 colors * 256 palettes + background color)
*Sound: '''4 FM, 7 ADPCM, 3 PSG channels'''

[[Category:Base system]]

Category:Chips

2012-03-15T21:49:44Z

Kyuusaku:

=Needed=
*[[NEO-257]],[[NEO-I0]] (pictures)
*[[LC98000]],[[LSPC-A0]],[[PRO-C0]],[[PRO-B0]],[[NEO-DCR-T]],[[NEO-SDR-T]] (pages)
*RAMs (VRAM, 68k, Z80)
*All SNK CD chips

=SNK chips, both cart and CD systems=

{| align=center class="regdef"
|rowspan="2"|'''Picture'''
|rowspan="2"|'''Reference'''
|rowspan="2"|'''Description'''
|colspan="5"|'''Found in'''
|- style="background-color:AllEEE;"
|'''CD1'''
|'''CD2'''
|'''CDZ'''
|'''Pinout'''
|-
|[[File:cd2_buf.jpg|x128px|center]]
|[[NEO-BUF]]
|Dual 8-bit bidirectional buffer
|All
|All
|?
|[[File:neo-buf_pinout.png|x128px|center]]
|-
|[[File:brd_grz.jpg|x128px|center]]
|[[NEO-GRZ]]
|Graphics chip
|
|
|?
|
|-
|[[File:brd_ysa2.jpg|x128px|center]]
|[[NEO-YSA2]]
|Audio subsystem chip
|
|
|All
|
|}

=SNK chips, AES/MVS=

{| align=center class="regdef"
|rowspan="2"|'''Picture'''
|rowspan="2"|'''Reference'''
|rowspan="2"|'''Description'''
|colspan="5"|'''Found in'''
|- style="background-color:AllEEE;"
|'''AES'''
|'''MVS'''
|Pinout
|-
|[[File:mvs_lspc-a0.jpg|x128px|center]]
|[[LSPC-A0]] (QFP160)
|First generation graphics chip
|Some
|Early
|
|-
|[[File:aes_lspc2a2.jpg|x128px|center]]
|[[LSPC2-A2]]
|Second generation graphics chip
|Some
|Some
|[[File:Lspc2-a2_pinout.png|x128px|center]]
|-
|[[File:mvs_257.jpg|x128px|center]]
|[[NEO-257]] (QFP64R)
|Quad 74HC257
|
|Some
|[[File:neo-257_pinout.png|x128px|center]]
|-
|[[File:aes_b1.jpg|x128px|center]]
|[[NEO-B1]]
|Second generation graphics chip
*Sprite and FIX multiplexer
*Line buffers
*Palette arbiter
|Some
|Some
|[[File:neo-b1_pinout.png|x128px|center]]
|-
|[[File:aes_c1.jpg|x128px|center]]
|[[NEO-C1]]
|
*Address decoder
*Joystick inputs
|Some
|Some
|[[File:neo-c1_pinout.png|x128px|center]]
|-
|[[File:aes_d0.jpg|x128px|center]]
|[[NEO-D0]] (QFP64R)
|Audio subsystem controller
|Some
|Some
|[[File:neo-d0_pinout.png|x128px|center]]
|-
|[[File:brd_dcr-t.jpg|x128px|center]]
|[[NEO-DCR-T]]
|?
|
|Some
|
|-
|[[File:mvs_sdr-t.jpg|x128px|center]]
|[[NEO-SDR-T]]
|?
|
|Some
|
|-
|[[File:aes_e0.jpg|x128px|center]]
|[[NEO-E0]] (QFP64R)
|
*Vector table swapping
*Memory card address translation
|Some
|Some
|[[File:neo-e0_pinout.png|x128px|center]]
|-
|[[File:mvs_f0.jpg|x128px|center]]
|[[NEO-F0]] (QFP64R)
|
*Calendar access
*Dip/cab switches, coin counters
*LED marquee outputs
*Slot selection
|
|Some
|[[File:neo-f0_pinout.png|x128px|center]]
|-
|[[File:aes_g0.jpg|x128px|center]]
|[[NEO-G0]] (QFP64R)
|
AES specific ?
*Palette data buffer
*Memory card data buffer
|Some
|Some
|[[File:neo-g0_pinout.png|x128px|center]]
|-
|[[File:mvs_zmc2.jpg|x128px|center]]
|[[NEO-ZMC2]] (QFP80R)
|
*Z80 Memory Controller
*Tile serializer
|Carts
|Some
|[[File:neo-zmc2_pinout.png|x128px|center]]
|-
|[[File:mvs_pro-b0.jpg|x128px|center]]
|[[PRO-B0]] (QFP136)
|First generation
*Palette arbiter
*Z80 latch
|Some
|Early
|
|-
|[[File:mvs_pro-c0.jpg|x128px|center]]
|[[PRO-C0]] (QFP136)
|First generation
*Address decoder
*Glue
*Line buffer
*Palette arbiter
|Some
|Early
|
|-
|[[File:mvs_pro-ct0.jpg|x128px|center]]
|[[PRO-CT0]] (SDIP64)
|[[C ROM]] character serializer and multiplexer
|Early carts
|Early
|
|}

=Cartridge chips=

{| align=center class="regdef"
|'''Picture'''
|'''Reference'''
|'''Description'''
|'''Pinout'''
|-
|[[File:crt_hd6301.jpg|x128px|center]]
|[[HD6301]] (DIP40)
|Microcontroller
|
|-
|[[File:crt_273.jpg|x128px|center]]
|[[NEO-273]] (QFP64R)
|C and [[S ROM]] address latch
|[[File:neo-273_pinout.png|x128px|center]]
|-
|[[File:crt_cmc.jpg|x128px|center]]
|[[NEO-CMC]]
|
*NEO-273 logic
*NEO-ZMC logic
*C ROM decryption
*C/S ROM multiplexer
*S ROM bankswitching
*M ROM decryption (NEOCMC50 only)
*M ROM bankswitching

|[[File:Neocmc_7050_7042_pinout.png|x200px|center]]
|-
|[[File:crt_pcm.jpg|x128px|center]]
|[[PCM]] (QFP80R)
|
*ADPCM bus latches
*[[V ROM]] multiplexer
|[[File:pcm_pinout.png|x128px|center]]
|-
|[[File:brd_pcm2.jpg|x128px|center]]
|[[NEO-PCM2]]
|
*[[NEO-PCM]]
*[[P ROM]] decoding, bankswitching and decryption
|
|-
|[[File:brd_pvc.jpg|x128px|center]]
|[[NEO-PVC]]
|[[P ROM]] decryption chip
|
|-
|[[File:crt_sma.jpg|x128px|center]]
|[[NEO-SMA]]
|[[P ROM]] decryption chip
|
|-
|[[File:crt_zmc.jpg|x128px|center]]
|[[NEO-ZMC]] (SOIC24)
|Z80 Memory Controller
|[[File:neo-zmc_pinout.png|x128px|center]]
|-
|[[File:crt_snk-9201.jpg|x128px|center]]
|[[SNK-9201]] (DIP64)
|[[P ROM]] protection chip
|
|}

=SNK chips, CD only=

{| align=center class="regdef"
|rowspan="2"|'''Picture'''
|rowspan="2"|'''Reference'''
|rowspan="2"|'''Description'''
|colspan="5"|'''Found in'''
|- style="background-color:AllEEE;"
|'''CD1'''
|'''CD2'''
|'''CDZ'''
|'''Pinout'''
|-
|[[File:cd2_grc.jpg|x128px|center]]
|[[NEO-GRC]]
|Graphics chip
|All
|All
|?
|
|-
|[[File:cd2_mga.jpg|x128px|center]]
|[[NEO-MGA]]<br>NEO-MGA-T<br>NEO-MGA-T2
|CD unit interface
|All
|All
|All
|
|-
|[[File:cd2_ofc.jpg|x128px|center]]
|[[NEO-OFC]]
|Graphics chip
|All
|All
|?
|
|-
|[[File:cd2_sft.jpg|x128px|center]]
|[[NEO-SFT]]
|Graphics related
|All
|All
|?
|
|-
|[[File:cd2_sud.jpg|x128px|center]]
|[[NEO-SUD]]
|Z80 subsystem controler
|All
|All
|?
|[[File:neo-sud_pinout.png|x128px|center]]
|-
|[[File:cd2_voc.jpg|x128px|center]]
|[[NEO-VOC]]
|PCM memory handler
|All
|All
|?
|[[File:neo-voc_pinout.png|x128px|center]]
|-
|[[File:cd2_ysa.jpg|x128px|center]]
|[[NEO-YSA]]
|Audio subsystem chip
|
|Some
|
|
|}

=Other chips=

{| align=center class="regdef"
|rowspan="2"|'''Picture'''
|rowspan="2"|'''Reference'''
|rowspan="2"|'''Description'''
|colspan="5"|'''Found in'''
|- style="background-color:AllEEE;"
|'''AES'''
|'''MVS'''
|'''CD1'''
|'''CD2'''
|'''CDZ'''
|-
|[[File:aes_68k.jpg|x128px|center]]
|[[68k|68HC000]] (DIP64)
|rowspan="2"|16bit CPU
|All
|Some
|
|
|
|-
|[[File:cd2_68k.jpg|x128px|center]]
|[[68k|68HC000]] (PLCC68)
|
|Some
|All
|All
|All
|-
|[[File:aes_cxa1145.jpg|x128px|center]]
|Sony [[CXA1145]]
|rowspan="2"|RGB encoder
|All
|
|
|
|
|-
|[[File:cd2_cxa1645.jpg|x128px|center]]
|Sony [[CXA1645]]
|
|
|?
|All
|?
|-
|[[File:cd2_lc78815.jpg|x128px|center]]
|Sanyo [[LC78815]]
|Stereo DAC
|
|
|?
|All
|
|-
|[[File:cd2_lc89515.jpg|x128px|center]]
|Sanyo [[LC89515]]
|CD host and error corrector
|
|
|All
|All
|?
|-
|[[File:cd2_lc8953.jpg|x128px|center]]
|Sanyo [[LC8953]]
|PUPPET
|
|
|All
|Some
|?
|-
|[[File:cd2_lc98000.jpg|x128px|center]]
|Sanyo [[LC8953|LC98000]]
|PUPPET replacement
|
|
|
|Some
|?
|-
|[[File:mvs_upd4990.jpg|x128px|center]]
|Nec [[UPD4990]]
|Real Time Clock
|
|All
|
|
|
|-
|[[File:cd2_ym2610.jpg|x128px|center]]
|Yamaha [[YM2610]]
|Sound synthesizer
|All
|All
|All
|Some
|
|-
|[[File:aes_ym3016.jpg|x128px|center]]
|Yamaha [[YM3016]]
|Audio DAC
|All
|All
|All
|Some
|
|-
|[[File:aes_z80.jpg|x128px|center]]
|[[z80]] (DIP40)
|rowspan="2"|8bit CPU
|All
|Some
|
|
|
|-
|[[File:cd2_z80.jpg|x128px|center]]
|[[z80]] (SOIC)
|
|Some
|All
|All
|All
|}

=Memory chips=

{| align=center class="regdef"
|'''Picture'''
|'''Reference'''
|'''Description'''
|'''Found in'''
|-
|[[File:aes_lo.jpg|x128px|center]]
|[[LO|LO]]
|Shrink lookup ROM
|All systems
|-
|[[File:mvs_sp-s2.jpg|x128px|center]]
|SP-S2
|MVS [[BIOSes|BIOS]]
|rowspan="3"|MVS systems
|-
|[[File:mvs_sm1.jpg|x128px|center]]
|[[SM1]]
|Embedded [[sound driver]] ROM
|-
|[[File:mvs_sfix.jpg|x128px|center]]
|[[SFIX]]
|Embedded [[Fix layer|Fix]] ROM
|-
|[[File:aes_biosep0.jpg|x128px|center]]
|[[NEO-EP0]]
|AES BIOS
|AES systems
|-
|[[File:cd2_top-sp1-1.jpg|x128px|center]]
|TOP-SP1-1
|CD2 BIOS
|Top loading CD systems (LC8953 versions)
|-
|[[File:cd2_top-sp1-2.jpg|128px|center]]
|TOP-SP1-2
|CD2 BIOS
|Top loading CD systems (LC98000 versions)
|-
|[[File:cd1_front-sp1.jpg|128px|center]]
|FRONT-SP1
|CD1 BIOS
|Front loading CD systems
|}

Talk:SNK-9201

2012-03-15T21:10:58Z

Kyuusaku: Created page with "SNK-9201 don't have 3-state outputs because they weren't configured that way for the CT0 logic, the actual gate arrays are certainly capable of it. ZMC2 seems to have brought ..."

SNK-9201 don't have 3-state outputs because they weren't configured that way for the CT0 logic, the actual gate arrays are certainly capable of it. ZMC2 seems to have brought the buffer inside (see "CS" and "CSDOT") but no games use the ZMC2 for protection. --[[User:Kyuusaku|Kyuusaku]] 22:10, 15 March 2012 (CET)

User:Kyuusaku

2012-03-15T20:05:12Z

Kyuusaku: Created page with " <nowiki>Projects: MVS converter (done) AES schematics MV4 schematics ASIC RE (~50%) PCMify discrete V ROM titles crack SNK-9201, weird mirroring games aim: calpis0 </nowiki>"

<nowiki>Projects:

MVS converter (done)
AES schematics
MV4 schematics
ASIC RE (~50%)
PCMify discrete V ROM titles
crack SNK-9201, weird mirroring games

aim: calpis0
</nowiki>

Talk:PRO-CT0

2012-03-15T19:54:13Z

Kyuusaku:

The SNK-9201 could have been misprinted, but I'm thinking the SNK-9201 *IS* a PRO-CT0 character multiplexer. The GAL acronym typically stands for "generic array logic", the SPLD. This would be either a "gate array", "uncommitted logic array" or "semi-custom ASIC --[[User:Kyuusaku|Kyuusaku]] 20:54, 15 March 2012 (CET)

PRO-CT0

2012-03-15T18:53:53Z

Kyuusaku:

[[File:mvs_pro-ct0.jpg|right|thumb|PRO-CT0 9020KX032 on an MV-4 [[MVS system]], as a graphics serializer]]

[[File:proct0prog.jpg|thumb|PRO-CT0 9042KX023 on an AES cart [[PROG board]] as a security chip]]

PRO-CT0 are early SDIP64 gate array chips used as:
*Sprite graphics multiplexers on AES carts and MVS boards, sometimes named ALPHA-8921, later replaced by [[NEO-ZMC2]] and then [[NEO-CMC]].
*Security devices in AES and MVS cartridges like [[Super Sidekicks]] and [[Fatal Fury 2]], later renamed [[SNK-9201]].

==Internal designs==

Known PRO-CT0 markings to be of the '''graphics chip''' type: 9020KX032, ...

Marking of '''SNK-9201's''': 9246EX020, 9247EX010, 9247EX007, 2947EX029

Marking of PRO-CT0's on '''AES PROG PCBs''': 9042KX023

==Pinout==

<nowiki>ALPHA-8921 / PRO-CT0

D1 odd.15 1 64 VCC
D3 odd.19 2 63 VCC
D5 odd.24 3 62 odd.26 D6
D7 odd.28 4 61 odd.22 D4
D8 odd.14 5 60 odd.17 D2
D10 odd.18 6 59 odd.13 D0
D12 odd.23 7 58 A8 H
D14 odd.27 8 57 A7 even
D9 odd.16 9 56 A5 12 MHz clk
D11 odd.20 10 55 A9 load
D13 odd.25 11 54 nc
D15 odd.29 12 53 nc
D0 even.13 13 52 nc
D2 even.17 14 51 nc
D4 even.22 15 50 GND
D6 even.26 16 49 GND
D1 even.15 17 48 B39 gbd3
D3 even.19 18 47 B38 gbd2
D5 even.24 19 46 B37 gbd1
D7 even.28 20 45 B36 gbd0
D8 even.14 21 44 GND
D10 even.18 22 43 GND
D12 even.23 23 42 B35 gad3
D14 even.27 24 41 B34 gad2
D9 even.16 25 40 B33 gad1
D11 even.20 26 39 B32 gad0
D13 even.25 27 38 nc
D15 even.29 28 37 nc
dota B30 29 36 nc
dotb B31 30 35 nc
GND 31 34 nc
GND 32 33 nc</nowiki>

[[Category:Chips]]

Talk:PRO-CT0

2012-03-15T18:46:05Z

Kyuusaku: Created page with "The SNK-9201 could have been misprinted. The GAL acronym typically stands for "generic array logic", the SPLD. This would be either a "gate array", "uncommitted logic array" o..."

The SNK-9201 could have been misprinted. The GAL acronym typically stands for "generic array logic", the SPLD. This would be either a "gate array", "uncommitted logic array" or "semi-custom ASIC --[[User:Kyuusaku|Kyuusaku]] 19:46, 15 March 2012 (CET)

Talk:Pinouts

2012-03-09T06:25:55Z

Kyuusaku:

For both AES PROG and CHA A24 is left audio in, A23 is left audio out, B24 is right in, B23 is right out

Thanks for the info. Can you tell me on which board you got this from ?
On a NEO-AES3-4 all those pins are NC (100% sure).
--[[User:Furrtek|Furrtek]] 07:10, 9 March 2012 (CET)

NEO-AES, it's the only revision with the audio loops
--[[User:Kyuusaku|Kyuusaku]] 07:25, 9 March 2012 (CET)

S ROM

2012-03-08T21:04:13Z

Kyuusaku: NEO-273 doesn't bankswitch

[[File:s_rom.jpg|thumb|right|128KiB S1 ROM]]
Graphics ROM containing tiles for the [[Fix layer]]. Bankswitch for ROMs >128KiB handled by [[NEO-CMC]].

Also found embedded in [[MVS systems]] with the [[SFIX]] name (default fix tileset).

[[Category:Chips]]
[[Category:Cartridge systems]]

Talk:Pinouts

2012-03-08T20:27:52Z

Kyuusaku: Created page with "For both AES PROG and CHA A24 is left audio in, A23 is left audio out, B24 is right in, B23 is right out"

For both AES PROG and CHA A24 is left audio in, A23 is left audio out, B24 is right in, B23 is right out

HD6301V1

2011-04-24T23:12:26Z

Kyuusaku:

[[File:crt_hd6301.jpg|right|thumb|HD6301 chip. Picture courtesy of [[http://www.mvs-scans.com MVS-Scans]].]]

8bit microcontroller used for [[multiplayer]] communication in [[cartridges]] like [[League Bowling]].

==Datasheet==

Official datasheet: [[http://www.datasheetcatalog.org/datasheets2/15/1588588_1.pdf]]

[[Category:Chips]]
[[Category:Cartridge systems]]

HD6301V1

2011-04-24T23:11:51Z

Kyuusaku:

[[File:crt_hd6301.jpg|right|thumb|NEO-PCM2 chip. Picture courtesy of [[http://www.mvs-scans.com MVS-Scans]].]]

8bit microcontroller used for [[multiplayer]] communication in [[cartridges]] like [[League Bowling]].

==Datasheet==

Official datasheet: [[http://www.datasheetcatalog.org/datasheets2/15/1588588_1.pdf]]

[[Category:Chips]]
[[Category:Cartridge systems]]

NEO-G0

2011-04-24T23:01:16Z

Kyuusaku:

[[File:Aes_g0.jpg|right|thumb|NEO-G0 chip found on an AES board.]]

Gates the [[68k]] data bus to the memory card slot and palette RAM. Only found in AES systems ?

PROG B22 (AES cart ROMOE ?) = ROMOEU AND ROMOEL like in [[NEO-E0]] ?

PALWE = PAL OR R/W.

=Pinout=

[[File:Neo-g0_pinout.png]]

*D0~D15: 68k data bus
*PALD0~PALD7: lower byte of palette data
*PAUD0~PAUD7: upper byte of palette data
*MCD0~MCD15: memory card data bus

[[Category:Chips]]

S ROM

2011-03-26T18:02:21Z

Kyuusaku:

[[File:s_rom.jpg|thumb|right|128KiB S1 ROM]]
Graphics ROM containing tiles for the [[Fix layer]]. Bankswitch for ROMs >128KiB handled by [[NEO-CMC]].

Also found embedded in [[MVS]] systems with the [[SFIX]] name (default fix tileset).

[[Category:Chips]]
[[Category:Emulation]]

NEO-ZMC2

2011-02-08T05:26:35Z

Kyuusaku:

[[File:mvs_zmc2.jpg|right|thumb|NEO-ZMC2 chip found on a 1FZS MVS board.]]

[[NEO-ZMC]] and [[PRO-CT0]] in one package. The PRO-CT0 is a network of shift registers and multiplexers (32-bit [[C ROM]] bus to two [[Graphics formats|4 bpp]] pixel outputs).

Found in second revision MVS boards (for the PRO-CT0 logic only) and AES carts.

== Pinout ==

[[File:Neo-zmc2 pinout.png]]

*A0,A1,A8~A15: [[Z80]] address bus (NEO-ZMC part)
*MA11~M21: M ROM address outputs
*12M: 12MHz clock (from [[NEO-D0]])
*GAD0~GAD3: Pixel A color data
*GBD0~GBD3: Pixel B color data
*C0~C31: Cartridge connections to C ROMs

[[Category:Chips]]

NEO-ZMC

2011-02-08T00:29:57Z

Kyuusaku:

[[File:crt_zmc.jpg|right|thumb|NEO-ZMC chip on a MVS [[cartridges|cartridge]]. Picture courtesy of [[http://www.mvs-scans.com MVS-Scans]].]]

Z80 memory controller. Has a hardwired 32KiB bank and switchable 16/8/4/2KiB banks arranged as a register file. To save pins the high address lines (A15-A8) are used for data input. The chip's write strobe is (port) address decoded inside the console.

[[Category:Chips]]

NEO-ZMC2

2011-02-08T00:28:10Z

Kyuusaku:

NEO-ZMC2

2011-02-08T00:26:14Z

Kyuusaku:

[[File:mvs_zmc2.jpg|right|thumb|NEO-ZMC2 chip found on a 1FZS MVS board.]]

NEO-ZMC and PRO-CT0 in one package. The PRO-CT0 is a network of shift registers and multiplexers (32-bit C ROM to two 4 bpp pixel outputs).

Found in second revision MVS boards (for the serializer only) and AES carts.

[[Category:Chips]]

NEO-ZMC

2011-02-08T00:08:35Z

Kyuusaku:

[[File:crt_zmc.jpg|right|thumb|NEO-ZMC chip on a MVS [[cartridges|cartridge]]. Picture courtesy of [[http://www.mvs-scans.com MVS-Scans]].]]

Z80 memory controller. Has a hardwired 32KiB bank and switchable 16/8/4/2KiB banks arranged as a register file. To save pins the high address lines are used as the data input. The chip's write strobe is (port) address decoded inside the console.

[[Category:Chips]]

NEO-ZMC

2011-02-08T00:04:56Z

Kyuusaku:

NEO-273

2011-02-07T23:59:18Z

Kyuusaku:

[[File:crt_273.jpg|right|thumb|NEO-273 chip in a MVS [[cartridges|cartridge]]. Picture courtesy of [[http://www.mvs-scans.com MVS-Scans]].]]

One 16-bit D-FF (to address 1M S ROM) and one 20-bit D-FF (to address 64M C ROM) in one package. Pinout unknown.

[[Category:Chips]]