NeoGeo Development Wiki - User contributions [en]

NEO-E0

2019-07-03T21:17:51Z

Pnauts: /* MV2B & MV2-01 @ H7 pinout */

{{ChipInfo
|picture=aes_e0.jpg
|pkg=QFP64R
|manu=fujitsu
|date=1991 ?
|gates=
|used_on={{PCB|NEO-AES3-3}} ...
}}

Just a 24-bit buffer and logic for [[68k vector table]] swapping.

=68k vector table swapping=
The 68k vector table is selected between the one from the game, or the on from the [[system ROM]] by writing to {{Reg|REG_SWPROM}} or {{Reg|REG_SWPBIOS}}.

A22Z and A23Z are used in place of A22 and A23 to make the address appear to address decoding chips as a system ROM access instead of a [[P ROM]] access.

The {{Sig|VEC|VEC}} signal comes from the 74H259 system latch.

{|class="wikitable"
!rowspan=2|Address||colspan=2|Maps to
|-
!VEC = 0||VEC = 1
|-
|$000000~$00007F||$C00000~$C0007F||$000000~$00007F
|-
|$000080~$BFFFFF||colspan=2|$000080~$BFFFFF
|-
|$C00000~$C0007F||$000000~$00007F||$C00000~$C0007F
|-
|$C00080~$FFFFFF||colspan=2|$C00080~$FFFFFF
|}

Verilog from [[User:Kyuusaku]]:
<pre>{A23Z,A22Z} = A[23:22] ^ 2{~|{A[21:7],^A[23:22],VEC}}</pre>

=Pinouts=

==Input to output map=

* 64 -> 5
* 1 -> 6
* 2 -> 7
* 3 -> 8
* 4 -> 9
* 15 -> 11
* 16 -> 12
* 17 -> 13
* 18 -> 14
* 19 -> 22
* 20 -> 23
* 21 -> 24
* 31 -> 27
* 32 -> 28
* 33 -> 29
* 34 -> 30
* 36 -> 39
* 37 -> 40
* 38 -> 41
* 48 -> 43
* 49 -> 44
* 50 -> 45
* 51 -> 46
* 52 -> 47
* 53 -> 55 if VEC is high
* 54 -> 56 if VEC is high

==Console==

On the AES, the AND gate is used to make /SROMOE from (/SROMOEL AND /SROMOEU).

==MV2B & MV2-01 @ H7 pinout==

* 55 = sPCK1B
* 56 = sPCK2B
[[P_bus]] buffer

==MV2B @ G2 pinout==

{|
|
[[File:Neo-e0_G2_pinout.png|512px]]

OpenOffice Draw file: [[File:Neo-e0_mv2b_G2.odg]]
|
*A1~A23: [[68k]] address bus
*MCA0~MCA23: [[memory card]] address bus
*BNK0~BNK2: memory card banking from [[NEO-D0]]
*VEC: [[System ROM]] vector table swapping enable
|}

==MV2B @ F7 pinout==

{|
|
[[File:Neo-e0_F7_pinout.png|512px]]

OpenOffice Draw file: [[File:Neo-e0_mv2b_F7.odg]]
|
Acts just as a buffer.

*s*: signals to both slots
|}

==MV2F @ E1 pinout (to be confirmed)==

{|
|
[[File:Neo-e0_pinout.png|512px]]

OpenOffice Draw file: [[File:neo-e0.odg]]
|
*A1~A23: 68k address bus
*Y0~Y23: memory card address bus
*BNK0~BNK2: comes from [[NEO-D0]], [[memory card]] bank
*VEC: System ROM vector table swapping
*ANI0, ANI1, AND0: AND gate used to generate ROMOE from (ROMOEU and ROMOEL)
|}

[[Category:Chips]]

Repair help

2019-07-03T21:13:14Z

Pnauts: /* Z80 error */

=Damaged chips=

==Smoke and other visible clues==

[[File:Friedchip.jpg|thumb|If a chip looks like the moon's surface, it can only be bad news. Here [[NEO-GRC2-F]] on a [[MV1B]], which fried under 12V.]]

Visual inspection can reveal physically damaged chips. Burnt, deformed or cracked chips are definitely dead.

On NeoGeo systems, burnt chips are often a sign that the 5V rail went way higher than 5V, probably because of a cab or [[supergun]] power supply failure, 12V short, or a reverse connection of the [[JAMMA_connector_pinout|JAMMA connector]]. Several chips are usually killed in that case, but all may not show visible damage.

Some chips may have survived on the board. '''May have'''.

==Internal damage==

Internal chip damage is more common, and can't be detected visually. Voltage spikes or shorts may cause microscopic, irreversible damage, resulting in floating or "stuck" pins.

That's why some pins of multi-purpose SNK chips like [[NEO-I0]] may still function, but others may be dead. Some custom chips can be saved if they're mostly functioning: the dead pins can be cut off and replaced with discrete logic chips with a bit of courage.

[[RAM_chip|RAM]] having unexplainable behavior are certainly internally damaged and need to be replaced. Multiple RAM chips may have been killed by a "long" voltage spike. RAM chips also tend to die one after the other on cabs which have their PSU's voltage set too high or drifting up with time.

=MVS=

==Backup/Work/Video RAM error==
Typical message looks like: ''Backup RAM error: Address 00D00000; Written 5555; Read 0000.''

The last part is the most usefull: ''Written XXXX Read YYZZ'' 
The YYZZ represent upper and lower bytes - each one handled by different SRAM IC: YY is upper RAM, ZZ is lower RAM.

The value can help you to know which line/trace cause problem. 
For example writting AAAA and reading AAA2 means the 4th data line of lower RAM causes problem. 
[[File:Calc-hexa.jpg|200px|]]

==Video RAM error==
*Address between $0000 and $7FFF: Check [[CXK58257]] [[VRAM]] chips next to [[GPU]]s (see [[RAM_chip]]).
*Address between $8000 and $86FF: Check [[CXK5814]] VRAM chips (see [[RAM_chip]]).
*Read high byte is different: check RAM chip with highest number.
*Read low byte is different: check RAM chip with lowest number.
*Read byte stuck to $FF (bad /OE ?), only a few bits different (traces cut ?), random address (floating /OE, /CE ?)

==No [[fix layer]]==
*Signal 1MB doesn't reach [[NEO-B1]].
*Signal PCK2B doesn't reach the cartridge slot.

==No sound==
*Backup RAM corrupt, '''SOUND_STOP''' ($D00046) is non-zero. Clear [[backup RAM]].
*[[YM2610]] has no clock, bad control signals (/CS mainly), or dead.
*[[YM3016]] has cut traces to YM2610, or dead.
*Low sound level: broken sliders/pots, bad caps.
*[[Power amp]] is fried.
*Unplugged or faulty [[NEO-CDD boards|NEO-CDD board]].
*Dead op-amps.

==Z80 error==
Can be caused by bad components / continuity with the following:
*Z80 <-> SM1
*Z80 <-> RAM
*Z80 <-> NEO-B0 (Z80 SD0-SD7)
*Z80 <-> NEO-257 (Z80 SD0-SD7) / if output of mux of a multi slot is shorted

Second generation specific (todo: get pin numbers in a nice table)
*Z80 <-> NEO-D0 (NMI,A2-A4,IORQ) 1st generation is also concerned.
*Z80 <-> NEO-C1 (Z80 SD0-SD7)
*NEO-D0 <-> NEO-C1 (Z80R,Z80W,Z80CLR,SDW)

[[Category:Repairs]]

NEO-E0

2019-06-29T13:31:17Z

Pnauts: /* MV2B @ H7 pinout */

{{ChipInfo
|picture=aes_e0.jpg
|pkg=QFP64R
|manu=fujitsu
|date=1991 ?
|gates=
|used_on={{PCB|NEO-AES3-3}} ...
}}

Just a 24-bit buffer and logic for [[68k vector table]] swapping.

=68k vector table swapping=
The 68k vector table is selected between the one from the game, or the on from the [[system ROM]] by writing to {{Reg|REG_SWPROM}} or {{Reg|REG_SWPBIOS}}.

A22Z and A23Z are used in place of A22 and A23 to make the address appear to address decoding chips as a system ROM access instead of a [[P ROM]] access.

The {{Sig|VEC|VEC}} signal comes from the 74H259 system latch.

{|class="wikitable"
!rowspan=2|Address||colspan=2|Maps to
|-
!VEC = 0||VEC = 1
|-
|$000000~$00007F||$C00000~$C0007F||$000000~$00007F
|-
|$000080~$BFFFFF||colspan=2|$000080~$BFFFFF
|-
|$C00000~$C0007F||$000000~$00007F||$C00000~$C0007F
|-
|$C00080~$FFFFFF||colspan=2|$C00080~$FFFFFF
|}

Verilog from [[User:Kyuusaku]]:
<pre>{A23Z,A22Z} = A[23:22] ^ 2{~|{A[21:7],^A[23:22],VEC}}</pre>

=Pinouts=

==Input to output map=

* 64 -> 5
* 1 -> 6
* 2 -> 7
* 3 -> 8
* 4 -> 9
* 15 -> 11
* 16 -> 12
* 17 -> 13
* 18 -> 14
* 19 -> 22
* 20 -> 23
* 21 -> 24
* 31 -> 27
* 32 -> 28
* 33 -> 29
* 34 -> 30
* 36 -> 39
* 37 -> 40
* 38 -> 41
* 48 -> 43
* 49 -> 44
* 50 -> 45
* 51 -> 46
* 52 -> 47
* 53 -> 55 if VEC is high
* 54 -> 56 if VEC is high

==Console==

On the AES, the AND gate is used to make /SROMOE from (/SROMOEL AND /SROMOEU).

==MV2B & MV2-01 @ H7 pinout==

* 55 = sPCK1B
* 56 = sPCK2B
Pbus buffer

==MV2B @ G2 pinout==

{|
|
[[File:Neo-e0_G2_pinout.png|512px]]

OpenOffice Draw file: [[File:Neo-e0_mv2b_G2.odg]]
|
*A1~A23: [[68k]] address bus
*MCA0~MCA23: [[memory card]] address bus
*BNK0~BNK2: memory card banking from [[NEO-D0]]
*VEC: [[System ROM]] vector table swapping enable
|}

==MV2B @ F7 pinout==

{|
|
[[File:Neo-e0_F7_pinout.png|512px]]

OpenOffice Draw file: [[File:Neo-e0_mv2b_F7.odg]]
|
Acts just as a buffer.

*s*: signals to both slots
|}

==MV2F @ E1 pinout (to be confirmed)==

{|
|
[[File:Neo-e0_pinout.png|512px]]

OpenOffice Draw file: [[File:neo-e0.odg]]
|
*A1~A23: 68k address bus
*Y0~Y23: memory card address bus
*BNK0~BNK2: comes from [[NEO-D0]], [[memory card]] bank
*VEC: System ROM vector table swapping
*ANI0, ANI1, AND0: AND gate used to generate ROMOE from (ROMOEU and ROMOEL)
|}

[[Category:Chips]]

Graphics pipeline

2019-04-22T16:03:42Z

Pnauts: /* First gen PRO chipset */

=First gen PRO chipset=
*[[LSPC-A0]]
*[[PRO-B0]]
*[[PRO-CT0]]
*[[PRO-C0]]

=Second gen chipset=
*[[LSPC2-A2]], [[NEO-B1]] (most common)
==MVS==
[[File:Gpu2mvs.png]]
==AES==
[[File:Gpu2aes.png]]

=CD gen chipset=
*[[NEO-GRC]]
*[[NEO-OFC]] (CD systems)
*[[NEO-SFT]] new ZMC2 ?

The sprite and fix DRAM bus can be switched between from NEO-OFC and the 68k bus for upload of graphics, thus allowing [[software rendering]].

=Last gen chipset=
*[[NEO-GRZ]]

[[Category:Video system]]

NEO-ZMC2

2019-02-25T22:42:13Z

Pnauts: /* Pinout */

{{ChipInfo
|picture=mvs_zmc2.jpg
|pkg=QFP80R
|manu=fujitsu
|date=1994 ?
|gates=
|used_on={{PCB|MV1FZS}} [[Cartridges]]...
}}

{{Chipname|NEO-ZMC}} and {{Chipname|PRO-CT0}} in one package.

Found in second revision [[MVS hardware|MVS]] boards (for the PRO-CT0 logic only), and AES cartridges.

=Pinout=

{{Pinout|NEO-ZMC2|640px}}

NEO-ZMC part:
*SDA0,SDA1,SDA8~SDA15: [[Z80]] address bus
*MA11~MA21: M ROM address outputs

PRO-CT0 part, inputs:
*12M: 12MHz clock, outputs next pixel on falling edge.
*C0~C31: C ROM data bus (2*16 bits). Gives all the pixel data needed for a 8 pixel line.
*H: When high, reverse bit order of pixels shifted out (used for [[sprites]] horizontal flipping)
*EVEN: Swap A/B pixels.
*LOAD: Latch C ROM data on rising edge of 12M.
Outputs:
*DOTA: High when pixel A is opaque (color > 0)
*DOTB: High when pixel B is opaque (color > 0)
*GAD0~GAD3: Pixel A color index
*GBD0~GBD3: Pixel B color index

[[Category:Chips]]

Repair help

2019-01-31T20:53:00Z

Pnauts: /* Z80 error */

=Damaged chips=

==Smoke and other visible clues==

[[File:Friedchip.jpg|thumb|If a chip looks like the moon's surface, it can only be bad news. Here [[NEO-GRC2-F]] on a [[MV1B]], which fried under 12V.]]

Visual inspection can reveal physically damaged chips. Burnt, deformed or cracked chips are definitely dead.

On NeoGeo systems, burnt chips are often a sign that the 5V rail went way higher than 5V, probably because of a cab or [[supergun]] power supply failure, 12V short, or a reverse connection of the [[JAMMA_connector_pinout|JAMMA connector]]. Several chips are usually killed in that case, but all may not show visible damage.

Some chips may have survived on the board. '''May have'''.

==Internal damage==

Internal chip damage is more common, and can't be detected visually. Voltage spikes or shorts may cause microscopic, irreversible damage, resulting in floating or "stuck" pins.

That's why some pins of multi-purpose SNK chips like [[NEO-I0]] may still function, but others may be dead. Some custom chips can be saved if they're mostly functioning: the dead pins can be cut off and replaced with discrete logic chips with a bit of courage.

[[RAM_chip|RAM]] having unexplainable behavior are certainly internally damaged and need to be replaced. Multiple RAM chips may have been killed by a "long" voltage spike. RAM chips also tend to die one after the other on cabs which have their PSU's voltage set too high or drifting up with time.

=MVS=

==Backup/Work/Video RAM error==
Typical message looks like: ''Backup RAM error: Address 00D00000; Written 5555; Read 0000.''

The last part is the most usefull: ''Written XXXX Read YYZZ'' 
The YYZZ represent upper and lower bytes - each one handled by different SRAM IC: YY is upper RAM, ZZ is lower RAM.

The value can help you to know which line/trace cause problem. 
For example writting AAAA and reading AAA2 means the 4th data line of lower RAM causes problem. 
[[File:Calc-hexa.jpg|200px|]]

==Video RAM error==
*Address between $0000 and $7FFF: Check [[CXK58257]] [[VRAM]] chips next to [[GPU]]s (see [[RAM_chip]]).
*Address between $8000 and $86FF: Check [[CXK5814]] VRAM chips (see [[RAM_chip]]).
*Read high byte is different: check RAM chip with highest number.
*Read low byte is different: check RAM chip with lowest number.
*Read byte stuck to $FF (bad /OE ?), only a few bits different (traces cut ?), random address (floating /OE, /CE ?)

==No [[fix layer]]==
*Signal 1MB doesn't reach [[NEO-B1]].
*Signal PCK2B doesn't reach the cartridge slot.

==No sound==
*Backup RAM corrupt, '''SOUND_STOP''' ($D00046) is non-zero. Clear [[backup RAM]].
*[[YM2610]] has no clock, bad control signals (/CS mainly), or dead.
*[[YM3016]] has cut traces to YM2610, or dead.
*Low sound level: broken sliders/pots, bad caps.
*[[Power amp]] is fried.
*Unplugged or faulty [[NEO-CDD boards|NEO-CDD board]].
*Dead op-amps.

==Z80 error==
Can be caused by bad components / continuity with the following:
*Z80 <-> SM1
*Z80 <-> RAM
Second generation specific (todo: get pin numbers in a nice table)
*Z80 <-> NEO-D0 (NMI,A2-A4,IORQ) 1st generation is also concerned.
*Z80 <-> NEO-C1 (Z80 D0-D7)
*NEO-D0 <-> NEO-C1 (Z80R,Z80W,Z80CLR,SDW)

[[Category:Repairs]]

Repair help

2019-01-31T20:52:02Z

Pnauts: /* Z80 error */

=Damaged chips=

==Smoke and other visible clues==

[[File:Friedchip.jpg|thumb|If a chip looks like the moon's surface, it can only be bad news. Here [[NEO-GRC2-F]] on a [[MV1B]], which fried under 12V.]]

Visual inspection can reveal physically damaged chips. Burnt, deformed or cracked chips are definitely dead.

On NeoGeo systems, burnt chips are often a sign that the 5V rail went way higher than 5V, probably because of a cab or [[supergun]] power supply failure, 12V short, or a reverse connection of the [[JAMMA_connector_pinout|JAMMA connector]]. Several chips are usually killed in that case, but all may not show visible damage.

Some chips may have survived on the board. '''May have'''.

==Internal damage==

Internal chip damage is more common, and can't be detected visually. Voltage spikes or shorts may cause microscopic, irreversible damage, resulting in floating or "stuck" pins.

That's why some pins of multi-purpose SNK chips like [[NEO-I0]] may still function, but others may be dead. Some custom chips can be saved if they're mostly functioning: the dead pins can be cut off and replaced with discrete logic chips with a bit of courage.

[[RAM_chip|RAM]] having unexplainable behavior are certainly internally damaged and need to be replaced. Multiple RAM chips may have been killed by a "long" voltage spike. RAM chips also tend to die one after the other on cabs which have their PSU's voltage set too high or drifting up with time.

=MVS=

==Backup/Work/Video RAM error==
Typical message looks like: ''Backup RAM error: Address 00D00000; Written 5555; Read 0000.''

The last part is the most usefull: ''Written XXXX Read YYZZ'' 
The YYZZ represent upper and lower bytes - each one handled by different SRAM IC: YY is upper RAM, ZZ is lower RAM.

The value can help you to know which line/trace cause problem. 
For example writting AAAA and reading AAA2 means the 4th data line of lower RAM causes problem. 
[[File:Calc-hexa.jpg|200px|]]

==Video RAM error==
*Address between $0000 and $7FFF: Check [[CXK58257]] [[VRAM]] chips next to [[GPU]]s (see [[RAM_chip]]).
*Address between $8000 and $86FF: Check [[CXK5814]] VRAM chips (see [[RAM_chip]]).
*Read high byte is different: check RAM chip with highest number.
*Read low byte is different: check RAM chip with lowest number.
*Read byte stuck to $FF (bad /OE ?), only a few bits different (traces cut ?), random address (floating /OE, /CE ?)

==No [[fix layer]]==
*Signal 1MB doesn't reach [[NEO-B1]].
*Signal PCK2B doesn't reach the cartridge slot.

==No sound==
*Backup RAM corrupt, '''SOUND_STOP''' ($D00046) is non-zero. Clear [[backup RAM]].
*[[YM2610]] has no clock, bad control signals (/CS mainly), or dead.
*[[YM3016]] has cut traces to YM2610, or dead.
*Low sound level: broken sliders/pots, bad caps.
*[[Power amp]] is fried.
*Unplugged or faulty [[NEO-CDD boards|NEO-CDD board]].
*Dead op-amps.

==Z80 error==
Can be caused by bad components / continuity with the following:
*Z80 <-> SM1
*Z80 <-> RAM
Second generation specific (todo: get pin numbers in a nice table)
*Z80 <-> NEO-D0 (NMI,A2-A4,IORQ) 1st generation also.
*Z80 <-> NEO-C1 (Z80 D0-D7)
*NEO-D0 <-> NEO-C1 (Z80R,Z80W,Z80CLR,SDW)

[[Category:Repairs]]

NEO-I0

2018-09-17T21:35:59Z

Pnauts: /* Pinout */ No A0 pinout

{{ChipInfo
|picture=neo-i0.jpg
|pkg=QFP64R
|manu=fujitsu
|date=1990 ?
|gates=
|used_on={{PCB|MV2B}} ...
}}

MVS specific chip that does a bunch of unrelated things.

* [[S ROM]] 16bit address latch for the [[SFIX ROM]], same as S ROM portion of {{Chipname|NEO-273}}
* [[SM1]] /CS output when {{Chipname|Z80}} is reading from ROM and onboard ROMs are enabled
* {{Sig|ROMOE|ROMOE}} output for cartridge(s) [[PROG board]]
* Video sync inversion (or not) to [[JAMMA_connector_pinout|JAMMA connector]]
* [[Coin counter]] and [[coin lockout]] outputs

=Pinout=

{{Pinout|NEO-I0|640px}}

*A1~A3,A7: {{Chipname|68k}} address bus
*P0~P15: [[P bus]]
*Q01~Q18: [[SFIX ROM]] address lines
*SM1CS(ORO0): [[SM1]] ROM chip select, made from SYSTEM(ORI0) OR SDROM(ORI1)
*SYNCOUT = SYNCIN XOR SYNCREV (SYNCREV always tied to ground ?)
*Q21, Q22: METER1, METER2
*Q23, Q24: LOCK1, LOCK2
*DS0, DS1: Data select for 2-slot systems made from SLOT0, SLOT1, PORTADRS and ROMOE, goes to a {{Chipname|NEO-G0}}
*COUNTOUT: Address decode from {{Chipname|NEO-F0}}

[[Category:Chips]]

MVS board connectors pinouts

2018-03-23T18:11:10Z

Pnauts: This is MV4 only (Not MV4F)

All infos by MKL.

[[MV4]] PCB connectors pinouts:

=CN8=
<pre>
A1 +5V
A2 +5V
A3 +5V
A4 SC2 (15), PRO-CT0 (15)
A5 SC2 (13), PRO-CT0 (16)
A6 SC2 (10), PRO-CT0 (21)
A7 SC2 (8), PRO-CT0 (22)
A8 SC2 (6), PRO-CT0 (23)
A9 SC2 (4), PRO-CT0 (24)
A10 NOT CONNECTED
A11 R2 (1), R3 (3)
A12 NOT CONNECTED
A13 NOT CONNECTED
A14 P1 (9)
A15 P1 (12)
A16 P1 (7)
A17 P1 (14)
A18 P1 (5)
A19 P1 (16)
A20 P1 (3)
A21 P1 (18)
A22 R1 (9)
A23 R1 (12)
A24 R1 (7)
A25 R1 (14)
A26 R1 (5)
A27 R1 (16)
A28 R1 (3)
A29 R1 (18)
A30 GND
A31 GND
A32 GND

B1 +5V
B2 +5V
B3 +5V
B4 SC2 (14), PRO-CT0 (19)
B5 SC2 (12), PRO-CT0 (20)
B6 SC2 (9), PRO-CT0 (25)
B7 SC2 (7), PRO-CT0 (26)
B8 SC2 (5), PRO-CT0 (27)
B9 SC2 (3), PRO-CT0 (28)
B10 SFIX (13)
B11 SFIX (14)
B12 SFIX (15)
B13 SFIX (17)
B14 SFIX (18)
B15 SFIX (19)
B16 SFIX (20)
B17 SFIX (21)
B18 R3 (12)
B19 R3 (14)
B20 R3 (16)
B21 R3 (18)
B22 R2 (11)
B23 R2 (12)
B24 R2 (13)
B25 R2 (14)
B26 R2 (15)
B27 R2 (16)
B28 R2 (17)
B29 R2 (18)
B30 GND
B31 GND
B32 GND
</pre>

The ICs:

* P1 = 74AS244
* R1 = 74AS244
* R2 = 74AS245
* R3 = 74AS244

=CN9=
<pre>
A1 +5V
A2 +5V
A3 +5V
A4 R11 (9)
A5 R11 (12)
A6 R11 (7)
A7 R11 (14)
A8 R11 (5)
A9 R11 (16)
A10 R11 (3)
A11 R11 (18)
A12 R10 (9)
A13 R10 (12)
A14 R10 (7)
A15 R10 (14)
A16 R10 (5)
A17 R10 (16)
A18 R10 (3)
A19 R10 (18)
A20 SC1 (19), PRO-CT0 (59)
A21 SC1 (17), PRO-CT0 (60)
A22 SC1 (15), PRO-CT0 (61)
A23 SC1 (13), PRO-CT0 (62)
A24 SC1 (10), PRO-CT0 (5)
A25 SC1 (8), PRO-CT0 (6)
A26 SC1 (6), PRO-CT0 (7)
A27 SC1 (4), PRO-CT0 (8)
A28 SC2 (19), PRO-CT0 (13)
A29 SC2 (17), PRO-CT0 (14)
A30 GND
A31 GND
A32 GND

B1 +5V
B2 +5V
B3 +5V
B4 P11 (9)
B5 P11 (12)
B6 P11 (7)
B7 P11 (14)
B8 P11 (5)
B9 P11 (16)
B10 P11 (3)
B11 P11 (18)
B12 P10 (9)
B13 P10 (12)
B14 P10 (7)
B15 P10 (14)
B16 P10 (5)
B17 P10 (16)
B18 P10 (3)
B19 P10 (18)
B20 SC1 (18), PRO-CT0 (1)
B21 SC1 (16), PRO-CT0 (2)
B22 SC1 (14), PRO-CT0 (3)
B23 SC1 (12), PRO-CT0 (4)
B24 SC1 (9), PRO-CT0 (9)
B25 SC1 (7), PRO-CT0 (10)
B26 SC1 (5), PRO-CT0 (11)
B27 SC1 (3), PRO-CT0 (12)
B28 SC2 (18), PRO-CT0 (17)
B29 SC2 (16), PRO-CT0 (18)
B30 GND
B31 GND
B32 GND
</pre>

The ICs:

* R10 = 74LS244
* R11 = 74LS244
* P10 = 74LS244
* P11 = 74LS244

=CN10=

{|class="wikitable"
!Pin||Connected to||Location
|-
|A1||+5V||
|-
|A2||+5V||
|-
|A3||+5V||
|-
|A4||+5V||
|-
|A5||Pin 2 of 74AS245||B7
|-
|A6||Pin 3 of 74AS245||B7
|-
|A7||Pin 4 of 74AS245||B7
|-
|A8||Pin 5 of 74AS245||B7
|-
|A9||Pin 6 of 74AS245||B7
|-
|A10||Pin 7 of 74AS245||B7
|-
|A11||Pin 8 of 74AS245||B7
|-
|A12||Pin 9 of 74AS245||B7
|-
|A13||Pin 2 of 74AS245||B8
|-
|A14||Pin 3 of 74AS245||B8
|-
|A15||Pin 4 of 74AS245||B8
|-
|A16||Pin 5 of 74AS245||B8
|-
|A17||Pin 6 of 74AS245||B8
|-
|A18||Pin 7 of 74AS245||B8
|-
|A19||Pin 8 of 74AS245||B8
|-
|A20||Pin 9 of 74AS245||B8
|-
|A21||Pin 9 of 74AS245 + Pin 3 of 74AS244||B8 + C11
|-
|A22||Pin 5 of 74AS244||C11
|-
|A23||Pin 7 of 74AS244||C11
|-
|A24||Pin 9 of 74AS244||C11
|-
|A25||Pin 12 of 74AS244||C11
|-
|A26||Pin 14 of 74AS244||C11
|-
|A27||Pin 16 of 74AS244||C11
|-
|A28||Pin 18 of 74AS244||C11
|-
|A29||Ground||
|-
|A30||Ground||
|-
|A31||Ground||
|-
|A32||Ground||
|}

<pre>
B1 +5V
B2 +5V
B3 +5V
B4 +5V
B5 B9 (18)
B6 B9 (3)
B7 B9 (16)
B8 B9 (5)
B9 B9 (14)
B10 B9 (7)
B11 B9 (12)
B12 B9 (9)
B13 B10 (18)
B14 B10 (3)
B15 B10 (16)
B16 B10 (5)
B17 B10 (14)
B18 B10 (7)
B19 B10 (12)
B20 B10 (9)
B21 B11 (18)
B22 B11 (3)
B23 B11 (16)
B24 B11 (5)
B25 PRO-C0 (72)
B26 PRO-C0 (74)
B27 PRO-C0 (75)
B28 PRO-C0 (73)
B29 GND
B30 GND
B31 GND
B32 GND
</pre>

The ICs:

* B7 = 74AS245
* B8 = 74AS245
* B9 = 74HC244
* B10 = 74HC244
* B11 = 74AS244
* C11 = 74AS244

=CN11=
<pre>
A1 +5V
A2 +5V
A3 +5V
A4 +5V
A5 F2 (14)
A6 F2 (12)
A7 F2 (9)
A8 F2 (7)
A9 F2 (3)
A10 F2 (5)
A11 G2 (5)
A12 G2 (16)
A13 G2 (9)
A14 G2 (12)
A15 G2 (7)
A16 G2 (14)
A17 G2 (18)
A18 G2 (3)
A19 F2 (16)
A20 NOT CONNECTED
A21 B11 (14)
A22 G10 (13)
A23 NOT CONNECTED
A24 NOT CONNECTED
A25 NOT CONNECTED
A26 NOT CONNECTED
A27 NOT CONNECTED
A28 NOT CONNECTED
A29 GND
A30 GND
A31 GND
A32 GND

B1 +5V
B2 +5V
B3 +5V
B4 +5V
B5 F1 (9)
B6 F1 (8)
B7 F1 (7)
B8 F1 (6)
B9 F1 (5)
B10 F1 (4)
B11 F1 (3)
B12 F1 (2)
B13 G1 (9)
B14 G1 (8)
B15 G1 (7)
B16 G1 (6)
B17 G1 (5)
B18 G1 (4)
B19 G1 (3)
B20 G1 (2)
B21 B11 (7)
B22 B11 (12)
B23 B11 (9)
B24 NOT CONNECTED
B25 NOT CONNECTED
B26 NOT CONNECTED
B27 NOT CONNECTED
B28 NOT CONNECTED
B29 GND
B30 GND
B31 GND
B32 GND
</pre>

The ICs:

* B11 = 74AS244
* F1 = 74LS245
* F2 = 74LS244
* G1 = 74LS245
* G2 = 74LS244
* G10 = LS138

[[Category:Chips]]