NeoGeo Development Wiki - User contributions [en]

Diagnostics BIOS

2012-08-09T15:08:01Z

SMKDAN: added a summary and a few sample pics

A homebrew BIOS used to test various parts of cartridge systems. It includes improved/fixed versions of the tests found in the SNK BIOS along with many new ones to help indentify faults faster. A Z80 ROM, which is meant to be used in place of a game [[M1 ROM]], can optionally be used to test the digital part of the sound system.

==Sample images==
<gallery>
Image:diag1.png|Example of RAM error (data error in chip for lower byte)
Image:diag2.png|Example of Z80 error (lower address line problem from Z80 to RAM)
Image:diag0.png|Displayed at end of successful testing
Image:diag3.png|Interactive calendar test
Image:diag4.png|Controller test
</gallery>

==Homepage==
http://smkdan.eludevisibility.org/neo/diag/

[[Category:Repairs]]

File:Diag4.png

2012-08-09T14:47:02Z

SMKDAN:

File:Diag3.png

2012-08-09T14:47:02Z

SMKDAN:

File:Diag2.png

2012-08-09T14:47:02Z

SMKDAN:

File:Diag1.png

2012-08-09T14:47:02Z

SMKDAN:

File:Diag0.png

2012-08-09T14:47:02Z

SMKDAN:

NEO-F0

2012-07-25T03:07:07Z

SMKDAN:

[[File:mvs_f0.jpg|right|thumb|NEO-F0 chip found on a MV1S MVS board.]]

MVS specific chip.

Handles the [[UPD4990]] calendar access, dipswitches, cab switches (test, service...), coin counters, LED marquee outputs and slot selection signals for multi-slot boards.

=Pinout=
[[File:neo-f0_pinout.png]]

OpenOffice Draw file: [[File:neo-f0.odg]]

*A4~A7: [[68k]] address bus
*D0~D7: 68k data bus
*4990: [[uPD4990]] RTC interface
*DATA0~DATA7: LED marquee latch data
*SLOT*: /CS for multislot boards ?
*DIP00~DIP07: [[DIPs|Dipswitch]] inputs
*IN3: Output IN300~IN302 to D0~D2 and CALTP/CALDOUT to D6/D7 (read $320001)
*DIPRD: Output to D0~D7 depending on state of A7 (from
** A7 is low: output DIP00~DIP07 (read $300001)
** A7 is high: output IN01 to D7 (test switch) and TYPE? to D6 (read $300081)
*BITW0: writes to $3800x1 region...(fill in)
*SLOTA~SLOTC: slot selection
*SLOT0~SLOT5: decoded slot selection
MV1F:
*IN00: Ground
*IN01: Test switch
*IN300: P1 Coin switch
*IN301: P2 Coin switch
*IN302: Service switch
*IN303/IN304: VCC

[[Category:Chips]]

MVS cartridge pinout

2012-06-25T13:21:15Z

SMKDAN:

{| class="regdef" align="center" style="text-align:center;align:right;"
|CHA bottom
|CHA top
|PROG bottom
|PROG top
|-
|[[File:mvscartchabot.png|200px]]
|[[File:mvscartchatop.png|200px]]
|[[File:mvscartprgbot.png|200px]]
|[[File:mvscartprgtop.png|200px]]
|}

Beware ! Pinouts found elsewhere have ROMOE/4MB swapped, it's an error on the original schematics. /ROMOE is on pin 33 bottom, 4MB is on pin 34 bottom.

See [[Signal names]] for the description of each pin.

(SMKDAN)
"SYSTEMB" appears to actually be a slot selection pin.
*On MV-2F, slot 1 A42 is connected to NEO-F0 SLOT0
*slot 2 A42 is connected to NEO-F0 SLOT1
Makes sense for 1F schematics to connect it straight to SYSTEMB since there are no other possible slots. On multislot, it comes from NEO-F0 (or equivalent) SLOT* outputs. NEO-F0 has SYSTEMB as an input so it probably only has SLOT* pins active when the cart ROMs are selected.

Is this signal ever used ? It's a dead end on all my carts.
--[[User:Furrtek|Furrtek]] 06:37, 25 June 2012 (CEST)

I can't name any official boards that use it. BIOS was written to ensure it is enabled when it does the slot check though. I see it always selecting cart M1/FIX to enable the SYSTEMB output even though it never uses the M1/S1 from cart, but I don't know if any games needed a "/SLOTCS" like this.--[[User:SMKDAN|SMKDAN]] 15:21, 25 June 2012 (CEST)

User talk:SMKDAN

2012-06-23T07:10:00Z

SMKDAN:

Excellent page about the graphic glitches, will definitely take some time to get the pinout of lspc-a/pro chips next month. How did you emulate the glitches, is MAME low level enough to "cut the traces" in the code ?
--[[User:Furrtek|Furrtek]] 09:02, 17 June 2012 (CEST)

Thanks, any extra info you have would be great. I didn't modify MAME. It's just some tiny C apps that read in the unmodified ROMs and output files with the glitches simulated and ran MAME with those.
--[[User:SMKDAN|SMKDAN]] 08:30, 18 June 2012 (CEST)

Okay, I see. Do you think it's possible to simulate other cuts such as on DOTA/DOTB... and on those in between lspc/B1 without too much effort ? I'll trace out the old chips pinouts from a dead board asap.--[[User:Furrtek|Furrtek]] 11:07, 18 June 2012 (CEST)

I'd like to do something like that but I need low level info on how those work. I read DOTA/DOTB is output by ZMC2 or whatever when pixel is opaque and goes to LSPC2, so NEO-B1 does not automatically drop transparent pixels and requires LSPC to command it to draw every individual pixel? With xpos sent to it on P-bus etc.? That's my best guess for now. All the other LSPC<->B1 signals have really cryptic names but I have guesses as to what they are, but no easy way to confirm it. If the right info was posted I'd modify MAME's driver to create some realistic pics later on.--[[User:SMKDAN|SMKDAN]] 09:48, 20 June 2012 (CEST)

I really have no idea how both graphic chips work, I'm not even sure where are the line buffers (B1 from what you're saying ?). I don't have much equipment so all I'll be able to get is the pinouts. Signals between the chips will be hard to decrypt with what I have, curious to see what will go on if those lines are cut/pulled low/down. Kyuusaku said he had reversed some of the internal logic but don't know if he'll share.
Weird they always had 2/3 chips for graphics instead of just 1, they never got to integrate everything in one even with NEO-GRZ...--[[User:Furrtek|Furrtek]] 11:13, 20 June 2012 (CEST)

I only guessed that buffers are on B1 since that's where the GFX data and palette addresses come from. It just seemed odd to move it back and forth between LPSC/B1 like that and the B1 would otherwise have not much to do apart from watchdog and 68k palette access. It's still just a guess though, I have nothing 100% on it and I'm in a bad position to figure it out myself. It would be cool if you manage to figure anything out from those. It's already known what has to be sent to B1 based on how they're hooked up, just don't know how it's done exactly. --[[User:SMKDAN|SMKDAN]] 09:10, 23 June 2012 (CEST)

User talk:SMKDAN

2012-06-20T07:48:58Z

SMKDAN:

User talk:SMKDAN

2012-06-20T07:48:38Z

SMKDAN:

User talk:SMKDAN

2012-06-18T06:30:01Z

SMKDAN:

Graphic glitches

2012-06-03T08:00:35Z

SMKDAN:

This is supposed to be a repair guide that doesn't need much technical knowledge on the GFX hardware to understand. Only cart systems are covered here. Pics are provided for all glitches described and can be used to compare glitches that show up on faulty hardware for help in repairs.

todo: maybe add more detail, get rest of pics/descriptions up
..don't have any LSPC-A0 info to work with so only LSPC2 is included for now

=C ROM=

All sprites come from the C ROMs. Most graphics on screen are sprites as the Neo has no dedicated scrolling background layers like other systems. If it moves, scales or appears to be part of a background then assume it's a sprite.

==C ROM address==

[[File:aof2normal.png|thumb|right|Reference pic used in samples]]

C ROM address lines follow this path:

* LSPC2/LSPC-A0 to CHA slot (on multislots it will go through some buffers in between)
* CHA slot to 74273 or similar(on oldest games)/NEO-273(on most games)/NEO-CMC(on newest games)
* 273/CMC to C ROM address lines

See [[pinouts]] for the slot pin numbers of the P0~23/CA4 signals listed in the table.

===Lower address lines===

A stuck lower address line for C ROMs causes certain patterns with display glitches. The graphics appear to be selected correctly but are glitched in various ways. A bad trace in the path of pins listed in the table can cause the glitch shown in the sample pic.

{| class="wikitable"
|-
! scope="col" | Sample
! scope="col" | Address
! scope="col" | LSPC2 out
! scope="col" | NEO‑273 in
! scope="col" | NEO‑273 out
! scope="col" | C ROMs in
! scope="col" | Notes
|-
|[[File:C_A0.png|none|thumb|60px]]
|A0
|P16(134)
|P16(57)
|C_A0(64)
|A0(10)
|1 row of pixels mirrored. Sprites appear "pixelated" as if it's lower res.
|-
|[[File:C_A1.png|none|thumb|60px]]
|A1
|P17(135)
|P17(59)
|C_A1(1)
|A1(9)
|Sets of 2 rows are mirrored.
|-
|[[File:C_A2.png|none|thumb|60px]]
|A2
|P18(136)
|P18(25)
|C_A2(32)
|A2(8)
|Sets of 4 rows are mirrored.
|-
|[[File:C_A3.png|none|thumb|60px]]
|A3
|P19(137)
|P19(27)
|C_A3(33)
|A3(7)
|Sets of 8 rows are mirrored.
|-
|[[File:C_A4.png|none|thumb|60px]]
|A4
|CA4(102)
|N/A
|N/A
|A4(6)
|Sets of 8 columns are mirrored. Note NEO-273 isn't used and CA4 on CHA connector goes straight to C ROM A3.
|}

===Higher address lines===

[[File:C_A12.png|thumb|right|120px|A12 stuck high. Ryo in the bottom right is fine but everything else has the wrong sprites displayed.]]

Higher address lines can cause the 16x16 blocks of sprite graphics to appear without glitches but in completely wrong places. C ROM address A5 upwards can cause this. The patterns aren't obvious like they are for lower address lines so it's not as easy to diagnose. The sample pic to the right shows an example. Graphics from different stages, characters etc. can show up correctly but are misplaced.

==C ROM data==

jailbars..

=S ROM=

Graphics from the S ROM are used for stationary life bars, credit counters, on screen text and other graphics that don't need to move around. In the reference image, S ROM graphics are used for:
* "SELECT ENEMY"
* "TIME" and "5"
* "COM"
* "LEVEL-4" and "CREDIT 00"
They can't scroll or scale and they always appear "on top" of all sprites. This can cause S ROM issues to completely cover the screen while the opposite isn't true.

==S ROM address==

S ROM address lines follow the same path as [[Graphic_glitches#C ROM address|C ROM address lines]]. 16 lines are shared with sprites and a single bad trace can affect both depending on what part of the path is affected. The NEO-273 (or whatever else is used) outputs separate S ROM/C ROM addresses from the shared address bus.

===Lower address lines===

Certain patterns appear for bad lower address lines like they do for C ROMs.

{| class="wikitable"
|-
! scope="col" | Sample
! scope="col" | Address
! scope="col" | LSPC2 out
! scope="col" | NEO‑273 in
! scope="col" | NEO‑273 out
! scope="col" | S ROM in
! scope="col" | Notes
|-
|[[File:S_A0.png|none|thumb|60px]]
|A0
|P12(126)
|P12(52)
|S_A0(48)
|A0(12)
|1 row of pixels mirrored. Appears "pixelated".
|-
|[[File:S_A1.png|none|thumb|60px]]
|A1
|P13(128)
|P13(53)
|S_A1(49)
|A1(11)
|Sets of 2 rows mirrored.
|-
|[[File:S_A2.png|none|thumb|60px]]
|A2
|P14(129)
|P14(54)
|S_A2(50)
|A2(10)
|Sets of 4 rows mirrored.
|-
|[[File:S_A3.png|none|thumb|60px]]
|A3
|2H1(107)
|N/A
|N/A
|A3(9)
|Sets of 2 columns mirrored. CHA 2H1 goes straight to A3 on S ROM.
|-
|[[File:S_A4.png|none|thumb|60px]]
|A4
|P15(130)
|P15(55)
|S_A4(51)
|A4(8)
|Sets of 4 columns mirrored.
|}

==S ROM data==

[[File:S_D_0.png|thumb|right|S ROM D0 (FIXD0) stuck high which creates jailbars covering the whole screen]]

Data outputs from the S ROM go through [[pinouts|FIXD0~FIXD7]] on the cart slot. If any one of these traces is bad then it can cause glitches that cover the entire screen. A single bad output can cause every odd (or even) column of pixels on screen to be obscured. Sprites below can appear fine with half the screen covered up.

[[Category:Tools]]

File:C 1357 data.png

2012-06-02T03:27:34Z

SMKDAN:

Graphic glitches

2012-06-01T05:33:00Z

SMKDAN: /* S ROM data */

File:S D 0.png

2012-06-01T05:29:23Z

SMKDAN: uploaded a new version of "File:S D 0.png"

Graphic glitches

2012-06-01T05:17:59Z

SMKDAN: /* C ROM */

Graphic glitches

2012-06-01T05:15:47Z

SMKDAN: /* Lower address lines */

This is supposed to be a repair guide that doesn't need much technical knowledge on the GFX hardware to understand. Only cart systems are covered here. Pics are provided for all glitches described and can be used to compare glitches that show up on faulty hardware for help in repairs.

todo: maybe add more detail, get rest of pics/descriptions up
..don't have any LSPC-A0 info to work with so only LSPC2 is included for now

=C ROM=

==C ROM address==

[[File:aof2normal.png|thumb|right|Reference pic used in samples]]

C ROM address lines follow this path:

* LSPC2/LSPC-A0 to CHA slot (on multislots it will go through some buffers in between)
* CHA slot to 74273 or similar(on oldest games)/NEO-273(on most games)/NEO-CMC(on newest games)
* 273/CMC to C ROM address lines

See [[pinouts]] for the slot pin numbers of the P0~23/CA4 signals listed in the table.

===Lower address lines===

A stuck lower address line for C ROMs causes certain patterns with display glitches. The graphics appear to be selected correctly but are glitched in various ways. A bad trace in the path of pins listed in the table can cause the glitch shown in the sample pic.

{| class="wikitable"
|-
! scope="col" | Sample
! scope="col" | Address
! scope="col" | LSPC2 out
! scope="col" | NEO‑273 in
! scope="col" | NEO‑273 out
! scope="col" | C ROMs in
! scope="col" | Notes
|-
|[[File:C_A0.png|none|thumb|60px]]
|A0
|P16(134)
|P16(57)
|C_A0(64)
|A0(10)
|1 row of pixels mirrored. Sprites appear "pixelated" as if it's lower res.
|-
|[[File:C_A1.png|none|thumb|60px]]
|A1
|P17(135)
|P17(59)
|C_A1(1)
|A1(9)
|Sets of 2 rows are mirrored.
|-
|[[File:C_A2.png|none|thumb|60px]]
|A2
|P18(136)
|P18(25)
|C_A2(32)
|A2(8)
|Sets of 4 rows are mirrored.
|-
|[[File:C_A3.png|none|thumb|60px]]
|A3
|P19(137)
|P19(27)
|C_A3(33)
|A3(7)
|Sets of 8 rows are mirrored.
|-
|[[File:C_A4.png|none|thumb|60px]]
|A4
|CA4(102)
|N/A
|N/A
|A4(6)
|Sets of 8 columns are mirrored. Note NEO-273 isn't used and CA4 on CHA connector goes straight to C ROM A3.
|}

===Higher address lines===

[[File:C_A12.png|thumb|right|120px|A12 stuck high. Ryo in the bottom right is fine but everything else has the wrong sprites displayed.]]

Higher address lines can cause the 16x16 blocks of sprite graphics to appear without glitches but in completely wrong places. C ROM address A5 upwards can cause this. The patterns aren't obvious like they are for lower address lines so it's not as easy to diagnose. The sample pic to the right shows an example. Graphics from different stages, characters etc. can show up correctly but are misplaced.

==C ROM data==

jailbars..

=S ROM=

Graphics from the S ROM are used for stationary life bars, credit counters, on screen text and other graphics that don't need to move around. In the reference image, S ROM graphics are used for:
* "SELECT ENEMY"
* "TIME" and "5"
* "COM"
* "LEVEL-4" and "CREDIT 00"
They can't scroll or scale and they always appear "on top" of all sprites. This can cause S ROM issues to completely cover the screen while the opposite isn't true.

==S ROM address==

S ROM address lines follow the same path as [[Graphic_glitches#C ROM address|C ROM address lines]]. 16 lines are shared with sprites and a single bad trace can affect both depending on what part of the path is affected. The NEO-273 (or whatever else is used) outputs separate S ROM/C ROM addresses from the shared address bus.

===Lower address lines===

Certain patterns appear for bad lower address lines like they do for C ROMs.

{| class="wikitable"
|-
! scope="col" | Sample
! scope="col" | Address
! scope="col" | LSPC2 out
! scope="col" | NEO‑273 in
! scope="col" | NEO‑273 out
! scope="col" | S ROM in
! scope="col" | Notes
|-
|[[File:S_A0.png|none|thumb|60px]]
|A0
|P12(126)
|P12(52)
|S_A0(48)
|A0(12)
|1 row of pixels mirrored. Appears "pixelated".
|-
|[[File:S_A1.png|none|thumb|60px]]
|A1
|P13(128)
|P13(53)
|S_A1(49)
|A1(11)
|Sets of 2 rows mirrored.
|-
|[[File:S_A2.png|none|thumb|60px]]
|A2
|P14(129)
|P14(54)
|S_A2(50)
|A2(10)
|Sets of 4 rows mirrored.
|-
|[[File:S_A3.png|none|thumb|60px]]
|A3
|2H1(107)
|N/A
|N/A
|A3(9)
|Sets of 2 columns mirrored. CHA 2H1 goes straight to A3 on S ROM.
|-
|[[File:S_A4.png|none|thumb|60px]]
|A4
|P15(130)
|P15(55)
|S_A4(51)
|A4(8)
|Sets of 4 columns mirrored.
|}

==S ROM data==

jailbars..

Graphic glitches

2012-06-01T05:14:29Z

SMKDAN: /* S ROM address */

This is supposed to be a repair guide that doesn't need much technical knowledge on the GFX hardware to understand. Only cart systems are covered here. Pics are provided for all glitches described and can be used to compare glitches that show up on faulty hardware for help in repairs.

todo: maybe add more detail, get rest of pics/descriptions up
..don't have any LSPC-A0 info to work with so only LSPC2 is included for now

=C ROM=

==C ROM address==

[[File:aof2normal.png|thumb|right|Reference pic used in samples]]

C ROM address lines follow this path:

* LSPC2/LSPC-A0 to CHA slot (on multislots it will go through some buffers in between)
* CHA slot to 74273 or similar(on oldest games)/NEO-273(on most games)/NEO-CMC(on newest games)
* 273/CMC to C ROM address lines

See [[pinouts]] for the slot pin numbers of the P0~23/CA4 signals listed in the table.

===Lower address lines===

A stuck lower address line for C ROMs causes certain patterns with display glitches. The graphics appear to be selected correctly but are glitched in various ways. A bad trace in the path of pins listed in the table can cause the glitch shown in the sample pic.

{| class="wikitable"
|-
! scope="col" | Sample
! scope="col" | Address
! scope="col" | LSPC2 out
! scope="col" | NEO‑273 in
! scope="col" | NEO‑273 out
! scope="col" | C ROMs in
! scope="col" | Notes
|-
|[[File:C_A0.png|none|thumb|60px]]
|A0
|P16(134)
|P16(57)
|C_A0(64)
|A0(10)
|1 row of pixels mirrored. Sprites appear "pixelated" as if it's lower res.
|-
|[[File:C_A1.png|none|thumb|60px]]
|A1
|P17(135)
|P17(59)
|C_A1(1)
|A1(9)
|Sets of 2 rows are mirrored.
|-
|[[File:C_A2.png|none|thumb|60px]]
|A2
|P18(136)
|P18(25)
|C_A2(32)
|A2(8)
|Sets of 4 rows are mirrored.
|-
|[[File:C_A3.png|none|thumb|60px]]
|A3
|P19(137)
|P19(27)
|C_A3(33)
|A3(7)
|Sets of 8 rows are mirrored.
|-
|[[File:C_A4.png|none|thumb|60px]]
|A4
|CA4(102)
|N/A
|N/A
|A4(6)
|Sets of 8 columns are mirrored. Note NEO-273 isn't used and CA4 on CHA connector goes straight to C ROM A3.
|}

===Higher address lines===

[[File:C_A12.png|thumb|right|120px|A12 stuck high. Ryo in the bottom right is fine but everything else has the wrong sprites displayed.]]

Higher address lines can cause the 16x16 blocks of sprite graphics to appear without glitches but in completely wrong places. C ROM address A5 upwards can cause this. The patterns aren't obvious like they are for lower address lines so it's not as easy to diagnose. The sample pic to the right shows an example. Graphics from different stages, characters etc. can show up correctly but are misplaced.

==C ROM data==

jailbars..

=S ROM=

Graphics from the S ROM are used for stationary life bars, credit counters, on screen text and other graphics that don't need to move around. In the reference image, S ROM graphics are used for:
* "SELECT ENEMY"
* "TIME" and "5"
* "COM"
* "LEVEL-4" and "CREDIT 00"
They can't scroll or scale and they always appear "on top" of all sprites. This can cause S ROM issues to completely cover the screen while the opposite isn't true.

==S ROM address==

S ROM address lines follow the same path as [[Graphic_glitches#C ROM address|C ROM address lines]]. 16 lines are shared with sprites and a single bad trace can affect both depending on what part of the path is affected. The NEO-273 (or whatever else is used) outputs separate S ROM/C ROM addresses from the shared address bus.

===Lower address lines===

...

{| class="wikitable"
|-
! scope="col" | Sample
! scope="col" | Address
! scope="col" | LSPC2 out
! scope="col" | NEO‑273 in
! scope="col" | NEO‑273 out
! scope="col" | S ROM in
! scope="col" | Notes
|-
|[[File:S_A0.png|none|thumb|60px]]
|A0
|P12(126)
|P12(52)
|S_A0(48)
|A0(12)
|1 row of pixels mirrored. Appears "pixelated".
|-
|[[File:S_A1.png|none|thumb|60px]]
|A1
|P13(128)
|P13(53)
|S_A1(49)
|A1(11)
|Sets of 2 rows mirrored.
|-
|[[File:S_A2.png|none|thumb|60px]]
|A2
|P14(129)
|P14(54)
|S_A2(50)
|A2(10)
|Sets of 4 rows mirrored.
|-
|[[File:S_A3.png|none|thumb|60px]]
|A3
|2H1(107)
|N/A
|N/A
|A3(9)
|Sets of 2 columns mirrored. CHA 2H1 goes straight to A3 on S ROM.
|-
|[[File:S_A4.png|none|thumb|60px]]
|A4
|P15(130)
|P15(55)
|S_A4(51)
|A4(8)
|Sets of 4 columns mirrored.
|}

==S ROM data==

jailbars..

Graphic glitches

2012-06-01T05:10:49Z

SMKDAN: /* S ROM */

This is supposed to be a repair guide that doesn't need much technical knowledge on the GFX hardware to understand. Only cart systems are covered here. Pics are provided for all glitches described and can be used to compare glitches that show up on faulty hardware for help in repairs.

todo: maybe add more detail, get rest of pics/descriptions up
..don't have any LSPC-A0 info to work with so only LSPC2 is included for now

=C ROM=

==C ROM address==

[[File:aof2normal.png|thumb|right|Reference pic used in samples]]

C ROM address lines follow this path:

* LSPC2/LSPC-A0 to CHA slot (on multislots it will go through some buffers in between)
* CHA slot to 74273 or similar(on oldest games)/NEO-273(on most games)/NEO-CMC(on newest games)
* 273/CMC to C ROM address lines

See [[pinouts]] for the slot pin numbers of the P0~23/CA4 signals listed in the table.

===Lower address lines===

A stuck lower address line for C ROMs causes certain patterns with display glitches. The graphics appear to be selected correctly but are glitched in various ways. A bad trace in the path of pins listed in the table can cause the glitch shown in the sample pic.

{| class="wikitable"
|-
! scope="col" | Sample
! scope="col" | Address
! scope="col" | LSPC2 out
! scope="col" | NEO‑273 in
! scope="col" | NEO‑273 out
! scope="col" | C ROMs in
! scope="col" | Notes
|-
|[[File:C_A0.png|none|thumb|60px]]
|A0
|P16(134)
|P16(57)
|C_A0(64)
|A0(10)
|1 row of pixels mirrored. Sprites appear "pixelated" as if it's lower res.
|-
|[[File:C_A1.png|none|thumb|60px]]
|A1
|P17(135)
|P17(59)
|C_A1(1)
|A1(9)
|Sets of 2 rows are mirrored.
|-
|[[File:C_A2.png|none|thumb|60px]]
|A2
|P18(136)
|P18(25)
|C_A2(32)
|A2(8)
|Sets of 4 rows are mirrored.
|-
|[[File:C_A3.png|none|thumb|60px]]
|A3
|P19(137)
|P19(27)
|C_A3(33)
|A3(7)
|Sets of 8 rows are mirrored.
|-
|[[File:C_A4.png|none|thumb|60px]]
|A4
|CA4(102)
|N/A
|N/A
|A4(6)
|Sets of 8 columns are mirrored. Note NEO-273 isn't used and CA4 on CHA connector goes straight to C ROM A3.
|}

===Higher address lines===

[[File:C_A12.png|thumb|right|120px|A12 stuck high. Ryo in the bottom right is fine but everything else has the wrong sprites displayed.]]

Higher address lines can cause the 16x16 blocks of sprite graphics to appear without glitches but in completely wrong places. C ROM address A5 upwards can cause this. The patterns aren't obvious like they are for lower address lines so it's not as easy to diagnose. The sample pic to the right shows an example. Graphics from different stages, characters etc. can show up correctly but are misplaced.

==C ROM data==

jailbars..

=S ROM=

Graphics from the S ROM are used for stationary life bars, credit counters, on screen text and other graphics that don't need to move around. In the reference image, S ROM graphics are used for:
* "SELECT ENEMY"
* "TIME" and "5"
* "COM"
* "LEVEL-4" and "CREDIT 00"
They can't scroll or scale and they always appear "on top" of all sprites. This can cause S ROM issues to completely cover the screen while the opposite isn't true.

==S ROM address==

S ROM address lines follow the same path as [[Graphic_glitches#C ROM address|C ROM address lines]]. 16 lines are shared with sprites and a single bad trace can affect both depending on what part of the path is affected.

===Lower address lines===

...

{| class="wikitable"
|-
! scope="col" | Sample
! scope="col" | Address
! scope="col" | LSPC2 out
! scope="col" | NEO‑273 in
! scope="col" | NEO‑273 out
! scope="col" | S ROM in
! scope="col" | Notes
|-
|[[File:S_A0.png|none|thumb|60px]]
|A0
|P12(126)
|P12(52)
|S_A0(48)
|A0(12)
|1 row of pixels mirrored. Appears "pixelated".
|-
|[[File:S_A1.png|none|thumb|60px]]
|A1
|P13(128)
|P13(53)
|S_A1(49)
|A1(11)
|Sets of 2 rows mirrored.
|-
|[[File:S_A2.png|none|thumb|60px]]
|A2
|P14(129)
|P14(54)
|S_A2(50)
|A2(10)
|Sets of 4 rows mirrored.
|-
|[[File:S_A3.png|none|thumb|60px]]
|A3
|2H1(107)
|N/A
|N/A
|A3(9)
|Sets of 2 columns mirrored. CHA 2H1 goes straight to A3 on S ROM.
|-
|[[File:S_A4.png|none|thumb|60px]]
|A4
|P15(130)
|P15(55)
|S_A4(51)
|A4(8)
|Sets of 4 columns mirrored.
|}

==S ROM data==

jailbars..

Graphic glitches

2012-05-31T12:53:25Z

SMKDAN:

File:S D 0.png

2012-05-31T12:23:01Z

SMKDAN:

File:S A12.png

2012-05-31T12:23:01Z

SMKDAN:

File:S A4.png

2012-05-31T12:23:01Z

SMKDAN:

File:S A3.png

2012-05-31T12:23:01Z

SMKDAN:

File:S A2.png

2012-05-31T12:23:01Z

SMKDAN:

File:S A1.png

2012-05-31T12:23:01Z

SMKDAN:

File:S A0.png

2012-05-31T12:23:00Z

SMKDAN:

Graphic glitches

2012-05-30T11:22:21Z

SMKDAN: /* C ROM */

Graphic glitches

2012-05-30T11:20:10Z

SMKDAN: repair help

File:Aof2normal.png

2012-05-30T09:57:04Z

SMKDAN: uploaded a new version of "File:Aof2normal.png"

File:C A0.png

2012-05-30T09:56:50Z

SMKDAN: uploaded a new version of "File:C A0.png"

File:C A1.png

2012-05-30T09:56:37Z

SMKDAN: uploaded a new version of "File:C A1.png"

File:C A2.png

2012-05-30T09:56:21Z

SMKDAN: uploaded a new version of "File:C A2.png"

File:C A3.png

2012-05-30T09:56:08Z

SMKDAN: uploaded a new version of "File:C A3.png"

File:C A4.png

2012-05-30T09:55:55Z

SMKDAN: uploaded a new version of "File:C A4.png"

File:C A12.png

2012-05-30T09:55:30Z

SMKDAN: uploaded a new version of "File:C A12.png"

File:C A12.png

2012-05-30T09:48:11Z

SMKDAN:

File:C A4.png

2012-05-30T09:48:11Z

SMKDAN:

File:C A3.png

2012-05-30T09:48:11Z

SMKDAN:

File:C A2.png

2012-05-30T09:48:11Z

SMKDAN:

File:C A1.png

2012-05-30T09:48:11Z

SMKDAN:

File:C A0.png

2012-05-30T09:48:11Z

SMKDAN:

File:Aof2normal.png

2012-05-30T09:48:10Z

SMKDAN:

MV2F

2012-05-10T06:19:39Z

SMKDAN: /* V ROM / YM2610 access */

Revised 2 slot board with the second generation chipset.

==Pinouts==

todo: formatting, maybe pics

===C ROM / LSPC2 / NEO-ZMC2===

todo. Pair of NEO-257 on far left of board used for this? 32 bits per slot multiplexed to NEO-ZMC2?

===S ROM / LSPC2 / NEO-B1===

FIXD0~FIXD7 is multiplexed from each from by NEO-257 @ J9. Same one is used for Z80 D0~D7 for cart M1 access.

{| class="wikitable"
|NEO-257 || CHA slot #1
|-
|A0(4) || FIXD0(B39)
|-
|A1(6) || FIXD1(B40)
|-
|A2(13) || FIXD2(B41)
|-
|A3(15) || FIXD3(B42)
|-
|A4(19) || FIXD4(B43)
|-
|A5(21) || FIXD5(B44)
|-
|A6(29) || FIXD6(B45)
|-
|A7(31) || FIXD7(B46)
|}

{| class="wikitable"
|NEO-257 || CHA slot #2
|-
|B0(5) || FIXD0(B39)
|-
|B1(7) || FIXD1(B40)
|-
|B2(14) || FIXD2(B41)
|-
|B3(16) || FIXD3(B42)
|-
|B4(20) || FIXD4(B43)
|-
|B5(22) || FIXD5(B44)
|-
|B6(30) || FIXD6(B45)
|-
|B7(32) || FIXD7(B46)
|}

Selected FIX data is output to NEO-B1 from Y0~Y7.

{| class="wikitable"
|NEO-257 || NEO-B1
|-
|Y0(8) || FIXD0(131)
|-
|Y1(9) || FIXD1(132)
|-
|Y2(11) || FIXD2(133)
|-
|Y3(12) || FIXD3(134)
|-
|Y4(23) || FIXD4(135)
|-
|Y5(24) || FIXD5(136)
|-
|Y6(27) || FIXD6(137)
|-
|Y7(28) || FIXD7(138)
|}

The 257 seems to have common enable/select lines. See M ROM section for those as cart M ROM/S ROM are always enabled together.

===V ROM / YM2610 access===

====ADPCM-A====

YM2610 RAD0~RAD7 goes through NEO-G0 @ K9 and out to each cart slot through a separate set of pins. (NEO-G0 needs a proper set of pin names).

{| class="wikitable"
|NEO-G0 || YM2610
|-
|(2) || RAD0(17)
|-
|(3) || RAD1(16)
|-
|(4) || RAD2(15)
|-
|(5) || RAD3(14)
|-
|(15) || RAD4(13)
|-
|(16) || RAD5(12)
|-
|(17) || RAD6(11)
|-
|(18) || RAD7(10)
|}

{| class="wikitable"
|NEO-G0 || PROG slot #1
|-
|(6) || SDRAD0(B49)
|-
|(7) || SDRAD1(B50)
|-
|(8) || SDRAD2(B51)
|-
|(9) || SDRAD3(B52)
|-
|(11) || SDRAD4(B53)
|-
|(12) || SDRAD5(B54)
|-
|(13) || SDRAD6(B55)
|-
|(14) || SDRAD7(B56)
|}

{| class="wikitable"
|NEO-G0 || PROG slot #2
|-
|(62) || SDRAD0(B49)
|-
|(63) || SDRAD1(B50)
|-
|(64) || SDRAD2(B51)
|-
|(1) || SDRAD3(B52)
|-
|(21) || SDRAD4(B53)
|-
|(22) || SDRAD5(B54)
|-
|(23) || SDRAD6(B55)
|-
|(24) || SDRAD7(B56)
|}

Control signals and other address lines buffered through NEO-E0 to both cart slots @ F8.

{| class="wikitable"
|NEO-E0 || YM2610
|-
|A7(16) || RA8(23)
|-
|A8(17) || RA9(22)
|-
|A9(18) || RA20(35)
|-
|A10(19) || RA21(36)
|-
|A11(20) || RA22(37)
|-
|A12(21) || RA23(38)
|-
|A13(31) || RMPX(20)
|-
|A14(32) || /ROE(21)
|}

{| class="wikitable"
|NEO-E0 || PROG slot #1 & #2
|-
|Y6(12) || SDRA8(A49)
|-
|Y7(13) || SDRA9(A50)
|-
|Y8(14) || SDRA20(A51)
|-
|Y9(22) || SDRA21(A52)
|-
|Y10(23) || SDRA22(A53)
|-
|Y11(24) || SDRA23(A54)
|-
|Y12(27) || SDRMPX(A55)
|-
|Y13(28) || SDROE(A56)
|}

Direction control of NEO-G0 (D0~D7) @ K9 is set to inverted /ROE from YM2610.

{| class="wikitable"
|NEO-E0 || 74AS04
|-
|Y13(28) || A5(11)
|}

{| class="wikitable"
|NEO-G0 || 74AS04
|-
|D0~D7 dir(40) || Y5(10)
|}

====ADPCM-B====

YM2610 PAD0~PAD7 goes through NEO-G0 @ K9 and out to each cart slot through a separate set of pins.

{| class="wikitable"
|NEO-G0 || YM2610
|-
|(31) || PAD0(48)
|-
|(32) || PAD1(49)
|-
|(33) || PAD2(50)
|-
|(34) || PAD3(51)
|-
|(47) || PAD4(52)
|-
|(48) || PAD5(53)
|-
|(49) || PAD6(54)
|-
|(50) || PAD7(55)
|}

{| class="wikitable"
|NEO-G0 || PROG slot #1
|-
|(27) || SDPAD0(B41)
|-
|(28) || SDPAD1(B42)
|-
|(29) || SDPAD2(B43)
|-
|(30) || SDPAD3(B44)
|-
|(43) || SDPAD4(B45)
|-
|(44) || SDPAD5(B46)
|-
|(45) || SDPAD6(B47)
|-
|(46) || SDPAD7(B48)
|}

{| class="wikitable"
|NEO-G0 || PROG slot #2
|-
|(35) || SDPAD0(B41)
|-
|(36) || SDPAD1(B42)
|-
|(37) || SDPAD2(B43)
|-
|(38) || SDPAD3(B44)
|-
|(53) || SDPAD4(B45)
|-
|(54) || SDPAD5(B46)
|-
|(55) || SDPAD6(B47)
|-
|(56) || SDPAD7(B48)
|}

Control signals and other address lines buffered through NEO-E0 to both cart slots @ F8.

{| class="wikitable"
|NEO-E0 || YM2610
|-
|A15(33) || PA8(41)
|-
|A16(34) || PA9(42)
|-
|A17(36) || PA10(43)
|-
|A18(37) || PA11(44)
|-
|A19(38) || PMPX(47)
|-
|A20(48) || /POE(46)
|-
|}

{| class="wikitable"
|NEO-E0 || PROG slot #1 & #2
|-
|Y14(29) || SDPA8(A43)
|-
|Y15(30) || SDPA9(A44)
|-
|Y16(39) || SDPA10(A45)
|-
|Y17(40) || SDPA11(A46)
|-
|Y18(41) || SDPMPX(A47)
|-
|Y19(43) || SDPOE(A48)
|}

Direction control of NEO-G0 (D8~D15) @ K9 is set to inverted /POE from YM2610.

{| class="wikitable"
|NEO-E0 || 74AS04
|-
|Y19(43) || A6(13)
|}

{| class="wikitable"
|NEO-G0 || 74AS04
|-
|D8~D15 dir(52) || Y6(12)
|}

===P ROM / 68k access===

todo. some NEO-G0 for D0~D15? NEO-E0 for A1~A23?

===M ROM / Z80 access===

Z80 A0~A15 is buffered through [[NEO-E0]] @ K10 to SDA0~SDA15 of both cart slots.

{| class="wikitable"
|Z80 || NEO-E0
|-
|A0(30) || A1(64)
|-
|A1(31) || A2(1)
|-
|A2(32) || A3(2)
|-
|A3(33) || A4(3)
|-
|A4(34) || A5(4)
|-
|A5(35) || A6(15)
|-
|A6(36) || A7(16)
|-
|A7(37) || A8(17)
|-
|A8(38) || A9(18)
|-
|A9(39 || A10(19)
|-
|A10(40) || A11(20)
|-
|A11(1) || A12(21)
|-
|A12(2) || A13(31)
|-
|A13(3) || A14(32)
|-
|A14(4) || A15(33)
|-
|A15(5) || A16(34)
|}

{| class="wikitable"
|NEO-E0 || CHA slot #1 & #2
|-
|Y0(5) || SDA0(A43)
|-
|Y1(6) || SDA1(A44)
|-
|Y2(7) || SDA2(A45)
|-
|Y3(8) || SDA3(A46)
|-
|Y4(9) || SDA4(A47)
|-
|Y5(11) || SDA5(A48)
|-
|Y6(12) || SDA6(A49)
|-
|Y7(13) || SDA7(A50)
|-
|Y8(14) || SDA8(A51)
|-
|Y9(22) || SDA9(A52)
|-
|Y10(23) || SDA10(A53)
|-
|Y11(24) || SDA11(A54)
|-
|Y12(27) || SDA12(A55)
|-
|Y13(28) || SDA13(A56)
|-
|Y14(29) || SDA14(A57)
|-
|Y15(30) || SDA15(A58)
|}

Z80 D0~D7 is multiplexed from each slot by [[NEO-257]] @ J9. No need for bidirectional D0~D7 since only reads can be done from cart.

{| class="wikitable"
|Z80 || NEO-257
|-
|D0(14) || Y8(40)
|-
|D1(15) || Y9(41)
|-
|D2(12) || Y10(43)
|-
|D3(8) || Y11(44)
|-
|D4(7) || Y12(55)
|-
|D5(9) || Y13(56)
|-
|D6(10) || Y14(59)
|-
|D7(13) || Y15(60)
|}

{| class="wikitable"
|NEO-257 || CHA slot #1
|-
|A8(36) || CHA SDD0(B51)
|-
|A9(38) || CHA SDD1(B52)
|-
|A10(45) || CHA SDD2(B53)
|-
|A11(47) || CHA SDD3(B54)
|-
|A12(51) || CHA SDD4(B55)
|-
|A13(53) || CHA SDD5(B56)
|-
|A14(62) || CHA SDD6(B57)
|-
|A15(64) || CHA SDD7(B58)
|-
|}

{| class="wikitable"
|NEO-257 || CHA slot #2
|-
|B8(37) || CHA SDD0(B51)
|-
|B9(39) || CHA SDD1(B52)
|-
|B10(46) || CHA SDD2(B53)
|-
|B11(48) || CHA SDD3(B54)
|-
|B12(52) || CHA SDD4(B55)
|-
|B13(54) || CHA SDD5(B56)
|-
|B14(63) || CHA SDD6(B57)
|-
|B15(1) || CHA SDD7(B58)
|-
|}

Multiplexer slot selection from [[NEO-F0]], /OE from NEO-D0 and OE from 74HC259 to NEO-257. The 257 must only output to Z80 when it is trying to read ROM (NEO-D0) and the cart M1/S1 is selected (74HC259).

{| class="wikitable"
|NEO-D0 || NEO-257
|-
|SDROM(11) || Y8~Y15 /OE(33)
|}

{| class="wikitable"
|NEO-F0 || NEO-257
|-
|SLOTA(39) || SELECT(17)
|}

{| class="wikitable"
|74HC259 || NEO-257
|-
|Q5(10) || Y8~Y15 OE(35)
|}

[[NEO-D0]] signals for Z80 reads are also buffered through NEO-E0 @ K10.

{| class="wikitable"
|NEO-D0 || NEO-E0
|-
|SDMRD(39) || A17(36)
|-
|SDROM(11) || A18(37)
|-
|SDRD0(45) || A19(38)
|-
|SDRD1(46) || A20(48)
|}

{| class="wikitable"
|NEO-E0 || CHA slot #1 & #2
|-
|Y16(39) || SDMRD(B50)
|-
|Y17(40) || SDROM(B49)
|-
|Y18(41) || SDRD0(B47)
|-
|Y19(43) || SDRD1(B48)
|}

MV2F

2012-05-10T06:18:29Z

SMKDAN: rest of ADPCM-B

Revised 2 slot board with the second generation chipset.

==Pinouts==

todo: formatting, maybe pics

===C ROM / LSPC2 / NEO-ZMC2===

todo. Pair of NEO-257 on far left of board used for this? 32 bits per slot multiplexed to NEO-ZMC2?

===S ROM / LSPC2 / NEO-B1===

FIXD0~FIXD7 is multiplexed from each from by NEO-257 @ J9. Same one is used for Z80 D0~D7 for cart M1 access.

{| class="wikitable"
|NEO-257 || CHA slot #1
|-
|A0(4) || FIXD0(B39)
|-
|A1(6) || FIXD1(B40)
|-
|A2(13) || FIXD2(B41)
|-
|A3(15) || FIXD3(B42)
|-
|A4(19) || FIXD4(B43)
|-
|A5(21) || FIXD5(B44)
|-
|A6(29) || FIXD6(B45)
|-
|A7(31) || FIXD7(B46)
|}

{| class="wikitable"
|NEO-257 || CHA slot #2
|-
|B0(5) || FIXD0(B39)
|-
|B1(7) || FIXD1(B40)
|-
|B2(14) || FIXD2(B41)
|-
|B3(16) || FIXD3(B42)
|-
|B4(20) || FIXD4(B43)
|-
|B5(22) || FIXD5(B44)
|-
|B6(30) || FIXD6(B45)
|-
|B7(32) || FIXD7(B46)
|}

Selected FIX data is output to NEO-B1 from Y0~Y7.

{| class="wikitable"
|NEO-257 || NEO-B1
|-
|Y0(8) || FIXD0(131)
|-
|Y1(9) || FIXD1(132)
|-
|Y2(11) || FIXD2(133)
|-
|Y3(12) || FIXD3(134)
|-
|Y4(23) || FIXD4(135)
|-
|Y5(24) || FIXD5(136)
|-
|Y6(27) || FIXD6(137)
|-
|Y7(28) || FIXD7(138)
|}

The 257 seems to have common enable/select lines. See M ROM section for those as cart M ROM/S ROM are always enabled together.

===V ROM / YM2610 access===

todo. NEO-E0 for address outputs only, some NEO-G0 for the databuses?

====ADPCM-A====

YM2610 RAD0~RAD7 goes through NEO-G0 @ K9 and out to each cart slot through a separate set of pins. (NEO-G0 needs a proper set of pin names).

{| class="wikitable"
|NEO-G0 || YM2610
|-
|(2) || RAD0(17)
|-
|(3) || RAD1(16)
|-
|(4) || RAD2(15)
|-
|(5) || RAD3(14)
|-
|(15) || RAD4(13)
|-
|(16) || RAD5(12)
|-
|(17) || RAD6(11)
|-
|(18) || RAD7(10)
|}

{| class="wikitable"
|NEO-G0 || PROG slot #1
|-
|(6) || SDRAD0(B49)
|-
|(7) || SDRAD1(B50)
|-
|(8) || SDRAD2(B51)
|-
|(9) || SDRAD3(B52)
|-
|(11) || SDRAD4(B53)
|-
|(12) || SDRAD5(B54)
|-
|(13) || SDRAD6(B55)
|-
|(14) || SDRAD7(B56)
|}

{| class="wikitable"
|NEO-G0 || PROG slot #2
|-
|(62) || SDRAD0(B49)
|-
|(63) || SDRAD1(B50)
|-
|(64) || SDRAD2(B51)
|-
|(1) || SDRAD3(B52)
|-
|(21) || SDRAD4(B53)
|-
|(22) || SDRAD5(B54)
|-
|(23) || SDRAD6(B55)
|-
|(24) || SDRAD7(B56)
|}

Control signals and other address lines buffered through NEO-E0 to both cart slots @ F8.

{| class="wikitable"
|NEO-E0 || YM2610
|-
|A7(16) || RA8(23)
|-
|A8(17) || RA9(22)
|-
|A9(18) || RA20(35)
|-
|A10(19) || RA21(36)
|-
|A11(20) || RA22(37)
|-
|A12(21) || RA23(38)
|-
|A13(31) || RMPX(20)
|-
|A14(32) || /ROE(21)
|}

{| class="wikitable"
|NEO-E0 || PROG slot #1 & #2
|-
|Y6(12) || SDRA8(A49)
|-
|Y7(13) || SDRA9(A50)
|-
|Y8(14) || SDRA20(A51)
|-
|Y9(22) || SDRA21(A52)
|-
|Y10(23) || SDRA22(A53)
|-
|Y11(24) || SDRA23(A54)
|-
|Y12(27) || SDRMPX(A55)
|-
|Y13(28) || SDROE(A56)
|}

Direction control of NEO-G0 (D0~D7) @ K9 is set to inverted /ROE from YM2610.

{| class="wikitable"
|NEO-E0 || 74AS04
|-
|Y13(28) || A5(11)
|}

{| class="wikitable"
|NEO-G0 || 74AS04
|-
|D0~D7 dir(40) || Y5(10)
|}

====ADPCM-B====

YM2610 PAD0~PAD7 goes through NEO-G0 @ K9 and out to each cart slot through a separate set of pins.

{| class="wikitable"
|NEO-G0 || YM2610
|-
|(31) || PAD0(48)
|-
|(32) || PAD1(49)
|-
|(33) || PAD2(50)
|-
|(34) || PAD3(51)
|-
|(47) || PAD4(52)
|-
|(48) || PAD5(53)
|-
|(49) || PAD6(54)
|-
|(50) || PAD7(55)
|}

{| class="wikitable"
|NEO-G0 || PROG slot #1
|-
|(27) || SDPAD0(B41)
|-
|(28) || SDPAD1(B42)
|-
|(29) || SDPAD2(B43)
|-
|(30) || SDPAD3(B44)
|-
|(43) || SDPAD4(B45)
|-
|(44) || SDPAD5(B46)
|-
|(45) || SDPAD6(B47)
|-
|(46) || SDPAD7(B48)
|}

{| class="wikitable"
|NEO-G0 || PROG slot #2
|-
|(35) || SDPAD0(B41)
|-
|(36) || SDPAD1(B42)
|-
|(37) || SDPAD2(B43)
|-
|(38) || SDPAD3(B44)
|-
|(53) || SDPAD4(B45)
|-
|(54) || SDPAD5(B46)
|-
|(55) || SDPAD6(B47)
|-
|(56) || SDPAD7(B48)
|}

Control signals and other address lines buffered through NEO-E0 to both cart slots @ F8.

{| class="wikitable"
|NEO-E0 || YM2610
|-
|A15(33) || PA8(41)
|-
|A16(34) || PA9(42)
|-
|A17(36) || PA10(43)
|-
|A18(37) || PA11(44)
|-
|A19(38) || PMPX(47)
|-
|A20(48) || /POE(46)
|-
|}

{| class="wikitable"
|NEO-E0 || PROG slot #1 & #2
|-
|Y14(29) || SDPA8(A43)
|-
|Y15(30) || SDPA9(A44)
|-
|Y16(39) || SDPA10(A45)
|-
|Y17(40) || SDPA11(A46)
|-
|Y18(41) || SDPMPX(A47)
|-
|Y19(43) || SDPOE(A48)
|}

Direction control of NEO-G0 (D8~D15) @ K9 is set to inverted /POE from YM2610.

{| class="wikitable"
|NEO-E0 || 74AS04
|-
|Y19(43) || A6(13)
|}

{| class="wikitable"
|NEO-G0 || 74AS04
|-
|D8~D15 dir(52) || Y6(12)
|}

===P ROM / 68k access===

todo. some NEO-G0 for D0~D15? NEO-E0 for A1~A23?

===M ROM / Z80 access===

Z80 A0~A15 is buffered through [[NEO-E0]] @ K10 to SDA0~SDA15 of both cart slots.

{| class="wikitable"
|Z80 || NEO-E0
|-
|A0(30) || A1(64)
|-
|A1(31) || A2(1)
|-
|A2(32) || A3(2)
|-
|A3(33) || A4(3)
|-
|A4(34) || A5(4)
|-
|A5(35) || A6(15)
|-
|A6(36) || A7(16)
|-
|A7(37) || A8(17)
|-
|A8(38) || A9(18)
|-
|A9(39 || A10(19)
|-
|A10(40) || A11(20)
|-
|A11(1) || A12(21)
|-
|A12(2) || A13(31)
|-
|A13(3) || A14(32)
|-
|A14(4) || A15(33)
|-
|A15(5) || A16(34)
|}

{| class="wikitable"
|NEO-E0 || CHA slot #1 & #2
|-
|Y0(5) || SDA0(A43)
|-
|Y1(6) || SDA1(A44)
|-
|Y2(7) || SDA2(A45)
|-
|Y3(8) || SDA3(A46)
|-
|Y4(9) || SDA4(A47)
|-
|Y5(11) || SDA5(A48)
|-
|Y6(12) || SDA6(A49)
|-
|Y7(13) || SDA7(A50)
|-
|Y8(14) || SDA8(A51)
|-
|Y9(22) || SDA9(A52)
|-
|Y10(23) || SDA10(A53)
|-
|Y11(24) || SDA11(A54)
|-
|Y12(27) || SDA12(A55)
|-
|Y13(28) || SDA13(A56)
|-
|Y14(29) || SDA14(A57)
|-
|Y15(30) || SDA15(A58)
|}

Z80 D0~D7 is multiplexed from each slot by [[NEO-257]] @ J9. No need for bidirectional D0~D7 since only reads can be done from cart.

{| class="wikitable"
|Z80 || NEO-257
|-
|D0(14) || Y8(40)
|-
|D1(15) || Y9(41)
|-
|D2(12) || Y10(43)
|-
|D3(8) || Y11(44)
|-
|D4(7) || Y12(55)
|-
|D5(9) || Y13(56)
|-
|D6(10) || Y14(59)
|-
|D7(13) || Y15(60)
|}

{| class="wikitable"
|NEO-257 || CHA slot #1
|-
|A8(36) || CHA SDD0(B51)
|-
|A9(38) || CHA SDD1(B52)
|-
|A10(45) || CHA SDD2(B53)
|-
|A11(47) || CHA SDD3(B54)
|-
|A12(51) || CHA SDD4(B55)
|-
|A13(53) || CHA SDD5(B56)
|-
|A14(62) || CHA SDD6(B57)
|-
|A15(64) || CHA SDD7(B58)
|-
|}

{| class="wikitable"
|NEO-257 || CHA slot #2
|-
|B8(37) || CHA SDD0(B51)
|-
|B9(39) || CHA SDD1(B52)
|-
|B10(46) || CHA SDD2(B53)
|-
|B11(48) || CHA SDD3(B54)
|-
|B12(52) || CHA SDD4(B55)
|-
|B13(54) || CHA SDD5(B56)
|-
|B14(63) || CHA SDD6(B57)
|-
|B15(1) || CHA SDD7(B58)
|-
|}

Multiplexer slot selection from [[NEO-F0]], /OE from NEO-D0 and OE from 74HC259 to NEO-257. The 257 must only output to Z80 when it is trying to read ROM (NEO-D0) and the cart M1/S1 is selected (74HC259).

{| class="wikitable"
|NEO-D0 || NEO-257
|-
|SDROM(11) || Y8~Y15 /OE(33)
|}

{| class="wikitable"
|NEO-F0 || NEO-257
|-
|SLOTA(39) || SELECT(17)
|}

{| class="wikitable"
|74HC259 || NEO-257
|-
|Q5(10) || Y8~Y15 OE(35)
|}

[[NEO-D0]] signals for Z80 reads are also buffered through NEO-E0 @ K10.

{| class="wikitable"
|NEO-D0 || NEO-E0
|-
|SDMRD(39) || A17(36)
|-
|SDROM(11) || A18(37)
|-
|SDRD0(45) || A19(38)
|-
|SDRD1(46) || A20(48)
|}

{| class="wikitable"
|NEO-E0 || CHA slot #1 & #2
|-
|Y16(39) || SDMRD(B50)
|-
|Y17(40) || SDROM(B49)
|-
|Y18(41) || SDRD0(B47)
|-
|Y19(43) || SDRD1(B48)
|}

MV2F

2012-05-10T06:03:35Z

SMKDAN: more YM stuff

Revised 2 slot board with the second generation chipset.

==Pinouts==

todo: formatting, maybe pics

===C ROM / LSPC2 / NEO-ZMC2===

todo. Pair of NEO-257 on far left of board used for this? 32 bits per slot multiplexed to NEO-ZMC2?

===S ROM / LSPC2 / NEO-B1===

FIXD0~FIXD7 is multiplexed from each from by NEO-257 @ J9. Same one is used for Z80 D0~D7 for cart M1 access.

{| class="wikitable"
|NEO-257 || CHA slot #1
|-
|A0(4) || FIXD0(B39)
|-
|A1(6) || FIXD1(B40)
|-
|A2(13) || FIXD2(B41)
|-
|A3(15) || FIXD3(B42)
|-
|A4(19) || FIXD4(B43)
|-
|A5(21) || FIXD5(B44)
|-
|A6(29) || FIXD6(B45)
|-
|A7(31) || FIXD7(B46)
|}

{| class="wikitable"
|NEO-257 || CHA slot #2
|-
|B0(5) || FIXD0(B39)
|-
|B1(7) || FIXD1(B40)
|-
|B2(14) || FIXD2(B41)
|-
|B3(16) || FIXD3(B42)
|-
|B4(20) || FIXD4(B43)
|-
|B5(22) || FIXD5(B44)
|-
|B6(30) || FIXD6(B45)
|-
|B7(32) || FIXD7(B46)
|}

Selected FIX data is output to NEO-B1 from Y0~Y7.

{| class="wikitable"
|NEO-257 || NEO-B1
|-
|Y0(8) || FIXD0(131)
|-
|Y1(9) || FIXD1(132)
|-
|Y2(11) || FIXD2(133)
|-
|Y3(12) || FIXD3(134)
|-
|Y4(23) || FIXD4(135)
|-
|Y5(24) || FIXD5(136)
|-
|Y6(27) || FIXD6(137)
|-
|Y7(28) || FIXD7(138)
|}

The 257 seems to have common enable/select lines. See M ROM section for those as cart M ROM/S ROM are always enabled together.

===V ROM / YM2610 access===

todo. NEO-E0 for address outputs only, some NEO-G0 for the databuses?

====ADPCM-A====

YM2610 RAD0~RAD7 goes through NEO-G0 @ K9 and out to each cart slot through a separate set of pins. (NEO-G0 needs a proper set of pin names).

{| class="wikitable"
|NEO-G0 || YM2610
|-
|(2) || RAD0(17)
|-
|(3) || RAD1(16)
|-
|(4) || RAD2(15)
|-
|(5) || RAD3(14)
|-
|(15) || RAD4(13)
|-
|(16) || RAD5(12)
|-
|(17) || RAD6(11)
|-
|(18) || RAD7(10)
|}

{| class="wikitable"
|NEO-G0 || PROG slot #1
|-
|(6) || SDRAD0(B49)
|-
|(7) || SDRAD1(B50)
|-
|(8) || SDRAD2(B51)
|-
|(9) || SDRAD3(B52)
|-
|(11) || SDRAD4(B53)
|-
|(12) || SDRAD5(B54)
|-
|(13) || SDRAD6(B55)
|-
|(14) || SDRAD7(B56)
|}

{| class="wikitable"
|NEO-G0 || PROG slot #2
|-
|(62) || SDRAD0(B49)
|-
|(63) || SDRAD1(B50)
|-
|(64) || SDRAD2(B51)
|-
|(1) || SDRAD3(B52)
|-
|(21) || SDRAD4(B53)
|-
|(22) || SDRAD5(B54)
|-
|(23) || SDRAD6(B55)
|-
|(24) || SDRAD7(B56)
|}

Control signals and other address lines buffered through NEO-E0 to both cart slots @ F8.

{| class="wikitable"
|NEO-E0 || YM2610
|-
|A7(16) || RA8(23)
|-
|A8(17) || RA9(22)
|-
|A9(18) || RA20(35)
|-
|A10(19) || RA21(36)
|-
|A11(20) || RA22(37)
|-
|A12(21) || RA23(38)
|-
|A13(31) || RMPX(20)
|-
|A14(32) || /ROE(21)
|}

{| class="wikitable"
|NEO-E0 || PROG slot #1 & #2
|-
|Y6(12) || SDRA8(A49)
|-
|Y7(13) || SDRA9(A50)
|-
|Y8(14) || SDRA20(A51)
|-
|Y9(22) || SDRA21(A52)
|-
|Y10(23) || SDRA22(A53)
|-
|Y11(24) || SDRA23(A54)
|-
|Y12(27) || SDRMPX(A55)
|-
|Y13(28) || SDROE(A56)
|}

Direction control of NEO-G0 @ K9 is set to inverted /ROE from YM2610.

{| class="wikitable"
|NEO-E0 || 74AS04
|-
|Y13(28) || A5(11)
|}

{| class="wikitable"
|NEO-G0 || 74AS04
|-
|D0~D7 dir(40) || Y5(10)
|}

====ADPCM-B====

===P ROM / 68k access===

todo. some NEO-G0 for D0~D15? NEO-E0 for A1~A23?

===M ROM / Z80 access===

Z80 A0~A15 is buffered through [[NEO-E0]] @ K10 to SDA0~SDA15 of both cart slots.

{| class="wikitable"
|Z80 || NEO-E0
|-
|A0(30) || A1(64)
|-
|A1(31) || A2(1)
|-
|A2(32) || A3(2)
|-
|A3(33) || A4(3)
|-
|A4(34) || A5(4)
|-
|A5(35) || A6(15)
|-
|A6(36) || A7(16)
|-
|A7(37) || A8(17)
|-
|A8(38) || A9(18)
|-
|A9(39 || A10(19)
|-
|A10(40) || A11(20)
|-
|A11(1) || A12(21)
|-
|A12(2) || A13(31)
|-
|A13(3) || A14(32)
|-
|A14(4) || A15(33)
|-
|A15(5) || A16(34)
|}

{| class="wikitable"
|NEO-E0 || CHA slot #1 & #2
|-
|Y0(5) || SDA0(A43)
|-
|Y1(6) || SDA1(A44)
|-
|Y2(7) || SDA2(A45)
|-
|Y3(8) || SDA3(A46)
|-
|Y4(9) || SDA4(A47)
|-
|Y5(11) || SDA5(A48)
|-
|Y6(12) || SDA6(A49)
|-
|Y7(13) || SDA7(A50)
|-
|Y8(14) || SDA8(A51)
|-
|Y9(22) || SDA9(A52)
|-
|Y10(23) || SDA10(A53)
|-
|Y11(24) || SDA11(A54)
|-
|Y12(27) || SDA12(A55)
|-
|Y13(28) || SDA13(A56)
|-
|Y14(29) || SDA14(A57)
|-
|Y15(30) || SDA15(A58)
|}

Z80 D0~D7 is multiplexed from each slot by [[NEO-257]] @ J9. No need for bidirectional D0~D7 since only reads can be done from cart.

{| class="wikitable"
|Z80 || NEO-257
|-
|D0(14) || Y8(40)
|-
|D1(15) || Y9(41)
|-
|D2(12) || Y10(43)
|-
|D3(8) || Y11(44)
|-
|D4(7) || Y12(55)
|-
|D5(9) || Y13(56)
|-
|D6(10) || Y14(59)
|-
|D7(13) || Y15(60)
|}

{| class="wikitable"
|NEO-257 || CHA slot #1
|-
|A8(36) || CHA SDD0(B51)
|-
|A9(38) || CHA SDD1(B52)
|-
|A10(45) || CHA SDD2(B53)
|-
|A11(47) || CHA SDD3(B54)
|-
|A12(51) || CHA SDD4(B55)
|-
|A13(53) || CHA SDD5(B56)
|-
|A14(62) || CHA SDD6(B57)
|-
|A15(64) || CHA SDD7(B58)
|-
|}

{| class="wikitable"
|NEO-257 || CHA slot #2
|-
|B8(37) || CHA SDD0(B51)
|-
|B9(39) || CHA SDD1(B52)
|-
|B10(46) || CHA SDD2(B53)
|-
|B11(48) || CHA SDD3(B54)
|-
|B12(52) || CHA SDD4(B55)
|-
|B13(54) || CHA SDD5(B56)
|-
|B14(63) || CHA SDD6(B57)
|-
|B15(1) || CHA SDD7(B58)
|-
|}

Multiplexer slot selection from [[NEO-F0]], /OE from NEO-D0 and OE from 74HC259 to NEO-257. The 257 must only output to Z80 when it is trying to read ROM (NEO-D0) and the cart M1/S1 is selected (74HC259).

{| class="wikitable"
|NEO-D0 || NEO-257
|-
|SDROM(11) || Y8~Y15 /OE(33)
|}

{| class="wikitable"
|NEO-F0 || NEO-257
|-
|SLOTA(39) || SELECT(17)
|}

{| class="wikitable"
|74HC259 || NEO-257
|-
|Q5(10) || Y8~Y15 OE(35)
|}

[[NEO-D0]] signals for Z80 reads are also buffered through NEO-E0 @ K10.

{| class="wikitable"
|NEO-D0 || NEO-E0
|-
|SDMRD(39) || A17(36)
|-
|SDROM(11) || A18(37)
|-
|SDRD0(45) || A19(38)
|-
|SDRD1(46) || A20(48)
|}

{| class="wikitable"
|NEO-E0 || CHA slot #1 & #2
|-
|Y16(39) || SDMRD(B50)
|-
|Y17(40) || SDROM(B49)
|-
|Y18(41) || SDRD0(B47)
|-
|Y19(43) || SDRD1(B48)
|}

NEO-G0

2012-05-10T05:28:14Z

SMKDAN: direction

[[File:Aes_g0.jpg|right|thumb|NEO-G0 chip found on an AES board.]]

Gates the [[68k]] data bus to the memory card slot and palette RAM. Only found in AES systems ?

PROG B22 (AES cart ROMOE ?) = ROMOEU AND ROMOEL like in [[NEO-E0]] ?

PALWE = PAL OR R/W.

=Pinout=

[[File:Neo-g0_pinout.png]]

OpenOffice Draw file: [[File:neo-g0.odg]]

*D0~D15: 68k data bus
*PALD0~PALD7: lower byte of palette data
*PAUD0~PAUD7: upper byte of palette data
*MCD0~MCD15: memory card data bus
*(51) is "enable MCD0~MCD15" pin
*(39) is "enable PALD0~PALD15" pin (confirmed on MV-2F chip used as ADPCM-A multiplexer):
**NEO-F0 -> NEO-G0 @ K9:
**SLOT0(48) -> SEL?(51)
**SLOT1(49) -> "PAL"(39)
*(40) is a direction select for "D0~D7" (negated /ROE from 2610 sent here and RAD0~RAD7 connected to "D0~D7" of G0
*(52) is a direction select for "D8~D15" (negated /POE sent here, PAD0~PAD7 connected to "D8~D15"

[[Category:Chips]]

Pinouts

2012-05-09T15:04:36Z

SMKDAN: "SYSTEMB" stuff

=Cartridges=
==Signal names==

*6M, 12M, 24M: 6MHz, 12MHz, and 24MHz clock signals
*4MB: 4MHz inverted signal
*A1~A19: [[68k]] address bus
*D0~D15: 68k data bus
*R/W: 68k R/W
*AS: 68k /AS
*/ROMOEL: $000000-$0FFFFF odd byte read
*/ROMOEU: $000000-$0FFFFF even byte read
*/ROMOE: $000000-$0FFFFF read
*/PORTOEL: $200000-$2FFFFF odd byte read
*/PORTOEU: $200000-$2FFFFF even byte read
*/PORTWEL: $200000-$2FFFFF odd byte write
*/PORTWEU: $200000-$2FFFFF even byte write
*/PORTADRS: $200000-$2FFFFF any access
*CR0~CR31: [[C ROM]]s data bus (2*16bits)
*SDRAD0~SDRAD7: ADPCM-A ROM [[YM2610#Multiplexed bus|multiplexed bus]] (data/address)
*SDRA8,SDRA9,SDRA20~SDRA23: ADPCM-A ROM address bus
*SDPAD0~SDPAD7: ADPCM-B ROM multiplexed bus (data/address)
*SDPA8,SDPA9,SDPA10,SDPA11: ADPCM-B ROM address bus
*P0~P23: C ROM and [[S ROM]] address bus (multiplexed)
*PCK1B: Clock to latch C ROM address from P0~P23 ([[NEO-273|mapping]]) on rising edge
*PCK2B: Clock to latch S ROM address from P0~P15 ([[NEO-273|mapping]]) on rising edge
*CA4: C ROM A4
*2H1: S ROM A3
*FIXD0~FIXD7: S ROM data bus

==AES Cartridge==

{| class="regdef" align="center" style="text-align:center;align:right;"
|PROG
|CHA
|-
|[[File:aesprogpinout.png]]
|[[File:aeschapinout.png]]
|}

*: Audio loops only used on NEO-AES systems (info from [[User:Kyuusaku]])

==MVS Cartridge==

{| class="regdef" align="center" style="text-align:center;align:right;"
|CHA bottom
|CHA top
|PROG bottom
|PROG top
|-
|[[File:mvscartchabot.png|200px]]
|[[File:mvscartchatop.png|200px]]
|[[File:mvscartprgbot.png|200px]]
|[[File:mvscartprgtop.png|200px]]
|}

Beware ! Pinouts found elsewhere have ROMOE/4MB swapped, it's an error on the original schematics. ROMOE is on pin 33 bottom, 4MB is on pin 34 bottom.

possible correction (delete this text whenever): "SYSTEMB" appears to actually be a slot selection pin.
*On MV-2F, slot 1 A42 is connected to NEO-F0 SLOT0
*slot 2 A42 is connected to NEO-F0 SLOT1
Makes sense for 1F schematics to connect it straight to SYSTEMB since there are no other possible slots. On multislot, it comes from NEO-F0 (or equivalent) SLOT* outputs. NEO-F0 has SYSTEMB as an input so it probably only has SLOT* pins active when the cart ROMs are selected.

=Joypad ports=

Inputs are pulled high to +5V.

<center>[[File:Joypad_pinout.png]]</center>

=JAMMA connector=
Infos from [[http://www.hardmvs.com HardMVS.com]]

{| class="regdef"
|bgcolor="#DDDDDD"|GND
|'''A'''
|'''1'''
|bgcolor="#DDDDDD"|GND
|-
|bgcolor="#DDDDDD"|GND
|'''B'''
|'''2'''
|bgcolor="#DDDDDD"|GND
|-
|bgcolor="#DD8888"| +5V
|'''C'''
|'''3'''
|bgcolor="#DD8888"| +5V
|-
|bgcolor="#DD8888"| +5V
|'''D'''
|'''4'''
|bgcolor="#DD8888"| +5V
|-
|
|'''E'''
|'''5'''
|
|-
|bgcolor="#DDDD88"| +12V
|'''F'''
|'''6'''
|bgcolor="#DDDD88"| +12V
|-
|Key
|'''H'''
|'''7'''
|Key
|-
|Coin counter #2
|'''J'''
|'''8'''
|Coin counter #1
|-
|Lockout coil #2
|'''K'''
|'''9'''
|Lockout coil #1
|-
|bgcolor="#DD8844"|Left speaker +
|'''L'''
|'''10'''
|bgcolor="#DD8844"|Right speaker +
|-
|Test switch
|'''M'''
|'''11'''
|bgcolor="#DD8844"|Mono audio +
|-
|bgcolor="#44FF44"|Video green
|'''N'''
|'''12'''
|bgcolor="#FF4444"|Video red
|-
|bgcolor="#FFFF44"|Video sync
|'''P'''
|'''13'''
|bgcolor="#4444FF"|Video blue
|-
|Service switch
|'''R'''
|'''14'''
|bgcolor="#DDDDDD"|Video GND
|-
|Coin switch #4 P2
|'''S'''
|'''15'''
|Coin switch #3 P1
|-
|Coin switch #2 P2
|'''T'''
|'''16'''
|Coin switch #1 P1
|-
|P2 Start
|'''U'''
|'''17'''
|P1 Start
|-
|P2 Up
|'''V'''
|'''18'''
|P1 Up
|-
|P2 Down
|'''W'''
|'''19'''
|P1 Down
|-
|P2 Left
|'''X'''
|'''20'''
|P1 Left
|-
|P2 Right
|'''Y'''
|'''21'''
|P1 Right
|-
|P2 A
|'''Z'''
|'''22'''
|P1 A
|-
|P2 B
|'''a'''
|'''23'''
|P1 B
|-
|P2 C
|'''b'''
|'''24'''
|P1 C
|-
|P2 D
|'''c'''
|'''25'''
|P1 D
|-
|Select down
|'''d'''
|'''26'''
|Select up
|-
|bgcolor="#DDDDDD"|GND
|'''e'''
|'''27'''
|bgcolor="#DDDDDD"|GND
|-
|bgcolor="#DDDDDD"|GND
|'''f'''
|'''28'''
|bgcolor="#DDDDDD"|GND
|}

=CD/CDZ=

==YM2610 digital audio==
[[File:Cd2_cn7.jpg|Cd2_cn7.jpg]]
Clock, L, R ?

==Video and CDDA==
[[File:Cd2_cn1cn3.jpg|400px]]
R, V, B, S, Burst, GND ?
Clock, L, R ?

==CD reader==
[[File:Cd2_cn4.jpg|400px]]

==Power==
[[File:Cd2_cn5.jpg]]

=Multiplayer jack=
To do.

[[Category:Chips]]
[[Category:Base system]]

MV2F

2012-05-09T14:34:55Z

SMKDAN: /* V ROM / YM2610 access */

Revised 2 slot board with the second generation chipset.

==Pinouts==

todo: formatting, maybe pics

===C ROM / LSPC2 / NEO-ZMC2===

todo. Pair of NEO-257 on far left of board used for this? 32 bits per slot multiplexed to NEO-ZMC2?

===S ROM / LSPC2 / NEO-B1===

FIXD0~FIXD7 is multiplexed from each from by NEO-257 @ J9. Same one is used for Z80 D0~D7 for cart M1 access.

{| class="wikitable"
|NEO-257 || CHA slot #1
|-
|A0(4) || FIXD0(B39)
|-
|A1(6) || FIXD1(B40)
|-
|A2(13) || FIXD2(B41)
|-
|A3(15) || FIXD3(B42)
|-
|A4(19) || FIXD4(B43)
|-
|A5(21) || FIXD5(B44)
|-
|A6(29) || FIXD6(B45)
|-
|A7(31) || FIXD7(B46)
|}

{| class="wikitable"
|NEO-257 || CHA slot #2
|-
|B0(5) || FIXD0(B39)
|-
|B1(7) || FIXD1(B40)
|-
|B2(14) || FIXD2(B41)
|-
|B3(16) || FIXD3(B42)
|-
|B4(20) || FIXD4(B43)
|-
|B5(22) || FIXD5(B44)
|-
|B6(30) || FIXD6(B45)
|-
|B7(32) || FIXD7(B46)
|}

Selected FIX data is output to NEO-B1 from Y0~Y7.

{| class="wikitable"
|NEO-257 || NEO-B1
|-
|Y0(8) || FIXD0(131)
|-
|Y1(9) || FIXD1(132)
|-
|Y2(11) || FIXD2(133)
|-
|Y3(12) || FIXD3(134)
|-
|Y4(23) || FIXD4(135)
|-
|Y5(24) || FIXD5(136)
|-
|Y6(27) || FIXD6(137)
|-
|Y7(28) || FIXD7(138)
|}

The 257 seems to have common enable/select lines. See M ROM section for those as cart M ROM/S ROM are always enabled together.

===V ROM / YM2610 access===

todo. NEO-E0 for address outputs only, some NEO-G0 for the databuses?

====ADPCM-A====

YM2610 RAD0~RAD7 goes through NEO-G0 @ K9 and out to each cart slot through a separate set of pins. (NEO-G0 needs a proper set of pin names).

{| class="wikitable"
|NEO-G0 || YM2610
|-
|(2) || RAD0(17)
|-
|(3) || RAD1(16)
|-
|(4) || RAD2(15)
|-
|(5) || RAD3(14)
|-
|(15) || RAD4(13)
|-
|(16) || RAD5(12)
|-
|(17) || RAD6(11)
|-
|(18) || RAD7(10)
|}

{| class="wikitable"
|NEO-G0 || PROG slot #1
|-
|(6) || SDRAD0(B49)
|-
|(7) || SDRAD1(B50)
|-
|(8) || SDRAD2(B51)
|-
|(9) || SDRAD3(B52)
|-
|(11) || SDRAD4(B53)
|-
|(12) || SDRAD5(B54)
|-
|(13) || SDRAD6(B55)
|-
|(14) || SDRAD7(B56)
|}

{| class="wikitable"
|NEO-G0 || PROG slot #2
|-
|(62) || SDRAD0(B49)
|-
|(63) || SDRAD1(B50)
|-
|(64) || SDRAD2(B51)
|-
|(1) || SDRAD3(B52)
|-
|(21) || SDRAD4(B53)
|-
|(22) || SDRAD5(B54)
|-
|(23) || SDRAD6(B55)
|-
|(24) || SDRAD7(B56)
|}

Control signals buffered through NEO-E0 to both cart slots @ F8.

{| class="wikitable"
|NEO-E0 || YM2610
|-
|A13(31) || RMPX(20)
|-
|A14(32) || /ROE(21)
|}

{| class="wikitable"
|NEO-E0 || PROG slot #1 & #2
|-
|Y12(27) || SDRMPX(A55)
|-
|Y13(28) || SDROE(A56)
|}

Direction control of NEO-G0 @ K9 is set to inverted /ROE from YM2610.

{| class="wikitable"
|NEO-E0 || 74AS04
|-
|Y13(28) || A5(11)
|}

{| class="wikitable"
|NEO-G0 || 74AS04
|-
|"R/W"(40) || Y5(10)
|}

(rest will come later)

===P ROM / 68k access===

todo. some NEO-G0 for D0~D15? NEO-E0 for A1~A23?

===M ROM / Z80 access===

Z80 A0~A15 is buffered through [[NEO-E0]] @ K10 to SDA0~SDA15 of both cart slots.

{| class="wikitable"
|Z80 || NEO-E0
|-
|A0(30) || A1(64)
|-
|A1(31) || A2(1)
|-
|A2(32) || A3(2)
|-
|A3(33) || A4(3)
|-
|A4(34) || A5(4)
|-
|A5(35) || A6(15)
|-
|A6(36) || A7(16)
|-
|A7(37) || A8(17)
|-
|A8(38) || A9(18)
|-
|A9(39 || A10(19)
|-
|A10(40) || A11(20)
|-
|A11(1) || A12(21)
|-
|A12(2) || A13(31)
|-
|A13(3) || A14(32)
|-
|A14(4) || A15(33)
|-
|A15(5) || A16(34)
|}

{| class="wikitable"
|NEO-E0 || CHA slot #1 & #2
|-
|Y0(5) || SDA0(A43)
|-
|Y1(6) || SDA1(A44)
|-
|Y2(7) || SDA2(A45)
|-
|Y3(8) || SDA3(A46)
|-
|Y4(9) || SDA4(A47)
|-
|Y5(11) || SDA5(A48)
|-
|Y6(12) || SDA6(A49)
|-
|Y7(13) || SDA7(A50)
|-
|Y8(14) || SDA8(A51)
|-
|Y9(22) || SDA9(A52)
|-
|Y10(23) || SDA10(A53)
|-
|Y11(24) || SDA11(A54)
|-
|Y12(27) || SDA12(A55)
|-
|Y13(28) || SDA13(A56)
|-
|Y14(29) || SDA14(A57)
|-
|Y15(30) || SDA15(A58)
|}

Z80 D0~D7 is multiplexed from each slot by [[NEO-257]] @ J9. No need for bidirectional D0~D7 since only reads can be done from cart.

{| class="wikitable"
|Z80 || NEO-257
|-
|D0(14) || Y8(40)
|-
|D1(15) || Y9(41)
|-
|D2(12) || Y10(43)
|-
|D3(8) || Y11(44)
|-
|D4(7) || Y12(55)
|-
|D5(9) || Y13(56)
|-
|D6(10) || Y14(59)
|-
|D7(13) || Y15(60)
|}

{| class="wikitable"
|NEO-257 || CHA slot #1
|-
|A8(36) || CHA SDD0(B51)
|-
|A9(38) || CHA SDD1(B52)
|-
|A10(45) || CHA SDD2(B53)
|-
|A11(47) || CHA SDD3(B54)
|-
|A12(51) || CHA SDD4(B55)
|-
|A13(53) || CHA SDD5(B56)
|-
|A14(62) || CHA SDD6(B57)
|-
|A15(64) || CHA SDD7(B58)
|-
|}

{| class="wikitable"
|NEO-257 || CHA slot #2
|-
|B8(37) || CHA SDD0(B51)
|-
|B9(39) || CHA SDD1(B52)
|-
|B10(46) || CHA SDD2(B53)
|-
|B11(48) || CHA SDD3(B54)
|-
|B12(52) || CHA SDD4(B55)
|-
|B13(54) || CHA SDD5(B56)
|-
|B14(63) || CHA SDD6(B57)
|-
|B15(1) || CHA SDD7(B58)
|-
|}

Multiplexer slot selection from [[NEO-F0]], /OE from NEO-D0 and OE from 74HC259 to NEO-257. The 257 must only output to Z80 when it is trying to read ROM (NEO-D0) and the cart M1/S1 is selected (74HC259).

{| class="wikitable"
|NEO-D0 || NEO-257
|-
|SDROM(11) || Y8~Y15 /OE(33)
|}

{| class="wikitable"
|NEO-F0 || NEO-257
|-
|SLOTA(39) || SELECT(17)
|}

{| class="wikitable"
|74HC259 || NEO-257
|-
|Q5(10) || Y8~Y15 OE(35)
|}

[[NEO-D0]] signals for Z80 reads are also buffered through NEO-E0 @ K10.

{| class="wikitable"
|NEO-D0 || NEO-E0
|-
|SDMRD(39) || A17(36)
|-
|SDROM(11) || A18(37)
|-
|SDRD0(45) || A19(38)
|-
|SDRD1(46) || A20(48)
|}

{| class="wikitable"
|NEO-E0 || CHA slot #1 & #2
|-
|Y16(39) || SDMRD(B50)
|-
|Y17(40) || SDROM(B49)
|-
|Y18(41) || SDRD0(B47)
|-
|Y19(43) || SDRD1(B48)
|}