NeoGeo Development Wiki - Recent changes [en]

BIOS RAM locations

Furrtek — Tue, 08 Sep 2026 08:43:23 GMT

Game Related

@@ Line 61: / Line 61: @@
 |byte
 |Game
 |-
 |$10FEC5

Magician Lord

Furrtek — Tue, 08 Sep 2026 05:23:09 GMT

← Older revision		Revision as of 07:23, 8 September 2026
Line 26:		Line 26:

	Uses no custom chips.		Uses no custom chips.

			The letter G of the "MAX 330 MEGA" text is slightly fucked up.

	[[Category:Games]]		[[Category:Games]]

NEO-PCM2

Furrtek — Sat, 05 Sep 2026 18:35:46 GMT

← Older revision		Revision as of 20:35, 5 September 2026
Line 3:		Line 3:
	\|pkg=QFP120		\|pkg=QFP120
	\|manu=fujitsu		\|manu=fujitsu
	\|date=~~2001 ?~~		\|date=1999, 2002
	\|gates=		\|gates=
	\|used_on=[[Cartridges]], [[ROM-Only boards]]		\|used_on=[[Cartridges]], [[ROM-Only boards]]
	}}		}}

	Second version of {{Chipname\|PCM}}. [[V ROM]] ~~(de)multiplexer~~, decryption and [[P ROM]] banking chip.		Second version of {{Chipname\|PCM}} which confusingly exists in two forms under the same name. [[V ROM]] demultiplexer, decryption and [[P ROM]] banking chip.

	The decryption algorithm used by emulators ~~may not be~~ perfectly exact, ~~this could be~~ a ~~possible cause of incorrect data~~ in decrypted romsets causing minor audio glitches (Samurai Shodown V "Basara").		The demultiplexing logic is exactly the same as the one found in PCM.

			=Jumpers=

			The ROM and mapping configuration for a given game is set by external jumpers. There are 3 for the V ROMs (JV1 to JV3) and 4 for the P ROMs (J1 to J4).
			These do not appear to affect security functions.

			V ROM mapping uses address bits 20 to 23. There are 4 chip select outputs.

			=Security=

			The security function of the 1999 SNK branded version only performs address descrambling on V ROMs. The Playmore version which came out in 2002 adds a data decryption layer on top, which means both are not interchangeable.

			The decryption algorithm used by emulators currently isn't perfectly exact, which explains the presence of a few corrupt bytes in decrypted romsets causing minor audio glitches (Samurai Shodown V "Basara" sample).

			==SNK version==

			P ROM bank selection is done by writing the 3 lower bits of the [[68k memory map\|port zone]] with A19 high to not affect the V ROM setting. ie. $200000 (word) or $200001 (even) with mirrors up to $2FFFFF.
			Metal Slug 4 for example writes words to $2FFFF0. Todo: how does the bank number map to an address.

			V ROM address scrambling is only done on the 4 lower bits by selectively inverting them depending on the configuration set by the [[68k]] CPU. Bits 4 to 23 go straight through.

			This is set by first writing 7 to the [[68k memory map\|port zone]], the same way P bank 7 would be selected. And then writing the 3 bit configuration value with A19 low.
			Metal Slug 4 for example writes words on startup to the bogus addresses $200000, $208000 and $220000.

			To test:
			{\| class="wikitable"
			\|-
			! V configuration !! VA3 !! VA2 !! VA1 !! VA0
			\|-
			\| 0 \|\| invert \|\| invert \|\| invert \|\| invert
			\|-
			\| 1 \|\| invert \|\| invert \|\| normal \|\| invert
			\|-
			\| 2 \|\| normal \|\| invert \|\| invert \|\| invert
			\|-
			\| 3 \|\| invert \|\| invert \|\| normal \|\| invert
			\|-
			\| 4 \|\| invert \|\| invert \|\| invert \|\| invert
			\|-
			\| 5 \|\| invert \|\| invert \|\| normal \|\| normal
			\|-
			\| 6 \|\| invert \|\| normal \|\| invert \|\| invert
			\|-
			\| 7 \|\| invert \|\| invert \|\| normal \|\| invert
			\|}

			==Playmore version==

			Todo.

			=Games=

	Used by:		Used by:
			* [[Matrimelee]] (Playmore)
	* [[Matrimelee]]		* [[Metal Slug 4]] (SNK)
	* [[Metal Slug 4]]		* [[Metal Slug 5]] (Playmore)
	* [[Metal Slug 5]]		* [[Pochi and Nyaa]] (SNK)
	* [[Pochi and Nyaa]]		* [[Rage of the Dragons]] (SNK)
	* [[Rage of the Dragons]]		* [[Samurai Shodown V]] (Playmore)
	* [[Samurai Shodown V]]		* [[Samurai Shodown V Special]] (Playmore)
	* [[Samurai Shodown V Special]]		* [[SNK vs. Capcom - SVC Chaos]] (Playmore)
	* [[SNK vs. Capcom - SVC Chaos]]		* [[The King of Fighters 2001]] (SNK)
	* [[The King of Fighters 2001]]		* [[The King of Fighters 2002]] (Playmore)
	* [[The King of Fighters 2002]]		* [[The King of Fighters 2003]] (Playmore)
	* [[The King of Fighters 2003]]

	=Pinout=		=Pinout=
Line 31:		Line 81:

	OpenOffice Draw file: [[File:neo-pcm2.odg]]		OpenOffice Draw file: [[File:neo-pcm2.odg]]

			Does the Playmore version have the same pinout ?

	[[Category:Chips]]		[[Category:Chips]]

Main Page

Furrtek — Mon, 31 Aug 2026 21:50:39 GMT

← Older revision		Revision as of 23:50, 31 August 2026
Line 134:		Line 134:
	<div class="head cat-games">[[:Category:Games\|<span class="cattitle"><span>Games</span></span>]]</div>		<div class="head cat-games">[[:Category:Games\|<span class="cattitle"><span>Games</span></span>]]</div>
	<div class="content">		<div class="content">
	<p>~~Remarquable games for some~~ of ~~their technical aspects:~~ special effects, unusual hardware ~~use, hidden features~~...</p>		<p>Game technical data and oddities such as use of special effects, unusual hardware...</p>
	</div>		</div>
	<div>		<div>

NEO-HYCS

Furrtek — Mon, 24 Aug 2026 07:59:48 GMT

← Older revision		Revision as of 09:59, 24 August 2026
Line 4:		Line 4:
	Original bodge board from SNK to fix [[V ROM]] selection on a few {{PCB\|PROGBK2R}} and {{PCB\|PROGBK3R}} based carts:		Original bodge board from SNK to fix [[V ROM]] selection on a few {{PCB\|PROGBK2R}} and {{PCB\|PROGBK3R}} based carts:

	* [[~~SNK_vs~~.~~_Capcom_~~-~~_SVC_Chaos~~]]		* [[SNK vs. Capcom - SVC Chaos]]
	* [[~~Samurai_Shodown_V~~]]		* [[Samurai Shodown V]]

	Apparently used to disable the V1 ROM for a short period at power on, possibly to allow [[NEO-PCM2]] to read the decryption parameters properly. Removing the board causes corrupt sound or games to show a "bank error".		Apparently used to disable the V1 ROM for a short period at power on, possibly to allow [[NEO-PCM2]] to read the decryption parameters properly. Removing the board causes corrupt sound or games to show a "bank error".

	MM311: Mitsumi PST600D reset generator (4.2V threshold). Forces V1 /CS high at startup, then lets the PCM2 signal through.		MM311: Mitsumi PST600D reset generator (4.2V threshold). Forces V1 /CS high at startup, then lets the PCM2 signal through.

			This fix was implemented in {{PCB\|PROGBK3S}} boards.

	[[Category:Cartridge systems]]		[[Category:Cartridge systems]]
	[[Category:Chips]]		[[Category:Chips]]

Sprite graphics format

Furrtek — Wed, 19 Aug 2026 00:57:02 GMT

← Older revision		Revision as of 02:57, 19 August 2026
Line 1:		Line 1:
	[[File:spritegfx2.png\|center]]		[[File:spritegfx2.png\|center]]

	The NeoGeo uses 16x16 pixels, ~~4bpp~~ tiles for sprites.		The NeoGeo uses 16x16 pixels, 4 bits per pixel tiles for sprites.

	They are stored as 4, 8x8 pixels blocks. Each row of these 8x8 blocks is stored '''backwards''' in a ~~4bit~~ planar organization.		They are stored as four 8x8 pixels blocks in the top-right, bottom-right, top-left, bottom-left order. Each row of these 8x8 blocks is stored '''backwards''' in a planar organization (each byte represents a bitplane).

	* On cartridge systems, bitplanes 0 and 1 go in the odd [[C ROM]]s (C1, C3...), while bitplanes 2 and 3 go in the even ones (C2, C4...).		* On cartridge systems, bitplanes 0 and 1 go in the odd [[C ROM]]s (C1, C3...), while bitplanes 2 and 3 go in the even ones (C2, C4...).
Line 20:		Line 20:
	n: Tile number (multiple bits)		n: Tile number (multiple bits)
	C: Block column, 0 = blocks 1 & 2, 1 = blocks 3 & 4		C: Block column, 0 = blocks 1 & 2, 1 = blocks 3 & 4
	L: Block ~~line~~ # (0~15)		L: Block row # (0~15)
	</pre>		</pre>

Z80 bankswitching

Furrtek — Tue, 18 Aug 2026 23:22:21 GMT

@@ Line 1: / Line 1: @@
-The [[Z80]] can only natively address 64kiB of memory because of its 16-bit address bus. To overcome this limit, bankswitching is provided in [[cartridges]] and [[CD systems]] to access up to 4MiB of [[M1 ROM]].
+The [[Z80]] can only natively address 64kiB of memory at most because of its 16-bit address bus. To overcome this limit, bankswitching is provided in [[cartridges]] to access up to 4MiB of [[M1 ROM]]. [[CD systems]] provide no Z80 bankswitching.
 =Operation=
-A standard of four bankswitching windows are available. The $0000 to $7FFF range is fixed to the first 32kiB of ROM, and $F800~$FFFF to [[Z80 RAM]].
+A standard of four bankswitching windows are available. The [[Z80|$0000~$7FFF range]] is fixed to the first 32kiB of ROM, and $F800~$FFFF to [[Z80 RAM]].
 All windows allow an 8-bit bank selection.
@@ Line 37: / Line 37: @@
 in a,(c)    ; Places $F3 = 243 on address[15:8] (bank number), $0B on address[7:0] (port number)
 </pre>
 ==Details==

Z80

Furrtek — Tue, 18 Aug 2026 23:14:58 GMT

Cartridge systems

@@ Line 16: / Line 16: @@
 * IRQs (address $38) are triggered by the YM2610 timers, if enabled.
-* An NMI (address $66) is triggered when the 68k sends a command byte, if enabled.
+* An NMI (address $66) is triggered when the 68k sends a command byte, if enabled (see [[Z80 port map]]).
 =Memory map=
@@ Line 38: / Line 38: @@
 |$BFFF
 |16KiB
-|Switching window 3
+|[[Z80 bankswitching|Bankswitching window 3]]
 |-
 |$C000
 |$DFFF
 |8KiB
-|Switching window 2
+|Bankswitching window 2
 |-
 |$E000
 |$EFFF
 |4KiB
-|Switching window 1
+|Bankswitching window 1
 |-
 |$F000
 |$F7FF
 |2KiB
-|Switching window 0
+|Bankswitching window 0
 |-
 |$F800
@@ Line 60: / Line 60: @@
 |[[Z80 RAM|Work RAM]]
 |}
 ==CD systems==

Z80 bankswitching

Furrtek — Tue, 18 Aug 2026 23:09:36 GMT

← Older revision		Revision as of 01:09, 19 August 2026
Line 1:		Line 1:
	The [[Z80]] can only natively address 64kiB of memory because of its 16-bit address bus. To overcome this limit, bankswitching is provided in [[cartridges]] and [[CD systems]].		The [[Z80]] can only natively address 64kiB of memory because of its 16-bit address bus. To overcome this limit, bankswitching is provided in [[cartridges]] and [[CD systems]] to access up to 4MiB of [[M1 ROM]].

	=Operation=		=Operation=

	A standard of four bankswitching windows are available. The $0000 to $7FFF range is fixed to the first 32kiB of ~~[[M1~~ ROM]], and $F800~$FFFF to [[Z80 RAM]].		A standard of four bankswitching windows are available. The $0000 to $7FFF range is fixed to the first 32kiB of ROM, and $F800~$FFFF to [[Z80 RAM]].

	All windows allow an 8-bit bank selection.		All windows allow an 8-bit bank selection.

NEO-ZMC2

Furrtek — Tue, 18 Aug 2026 23:09:13 GMT

← Older revision		Revision as of 01:09, 19 August 2026
Line 8:		Line 8:
	}}		}}

	{{Chipname\|NEO-ZMC}} and {{Chipname\|PRO-CT0}} in one package.		{{Chipname\|NEO-ZMC}} ([[Z80 bankswitching]]) and {{Chipname\|PRO-CT0}} (sprite graphics serializer) in one package.

	~~Can address up to 4MiB of [[M1 ROM]]~~.

	Found in second revision [[MVS hardware\|MVS]] boards (for the PRO-CT0 logic only), and AES cartridges.		Found in second revision [[MVS hardware\|MVS]] boards (for the PRO-CT0 logic only), and AES cartridges.

Z80 bankswitching

Furrtek — Tue, 18 Aug 2026 23:08:20 GMT

Created page with "The Z80 can only natively address 64kiB of memory because of its 16-bit address bus. To overcome this limit, bankswitching is provided in cartridges and CD systems. =Operation= A standard of four bankswitching windows are available. The $0000 to $7FFF range is fixed to the first 32kiB of M1 ROM, and $F800~$FFFF to Z80 RAM. All windows allow an 8-bit bank selection. {|class="wikitable" !Z80 port !Window address !Size !Bank range |- |$08||$F000~$F7F..."

New page

The [[Z80]] can only natively address 64kiB of memory because of its 16-bit address bus. To overcome this limit, bankswitching is provided in [[cartridges]] and [[CD systems]].

=Operation=

A standard of four bankswitching windows are available. The $0000 to $7FFF range is fixed to the first 32kiB of [[M1 ROM]], and $F800~$FFFF to [[Z80 RAM]].

All windows allow an 8-bit bank selection.

{|class="wikitable"
!Z80 port
!Window address
!Size
!Bank range
|-
|$08||$F000~$F7FF||2KiB||$000000~$07FFFF
|-
|$09||$E000~$EFFF||4KiB||$000000~$0FFFFF
|-
|$0A||$C000~$DFFF||8KiB||$000000~$1FFFFF
|-
|$0B||$8000~$BFFF||16KiB||$000000~$3FFFFF
|}

Bank numbers are undefined on startup, the Z80 code must initialize them.

To save pins on bankswitching chips in cartridges such as the {{chipname|NEO-ZMC}}, SNK used a quirk of the Z80 that allows placing data on its address bus. Therefore, to set a bank number, the Z80 port must be '''read''' with the bank number in the upper address bits.

For example, this will set the $F000~$F7FF window to bank 25, ie. ROM 25 * 2kiB = $C800~$CFFF
<pre>
ld a,25
in a,(8) ; Places 25 on address[15:8] (bank number), 8 on address[7:0] (port number)
</pre>

For example, this will set the $8000~$BFFF window to bank 243, ie. ROM 243 * 16kiB = $3CC000~$3CFFFF
<pre>
ld bc,$F30B
in a,(c) ; Places $F3 = 243 on address[15:8] (bank number), $0B on address[7:0] (port number)
</pre>

==Details==

SDA8~SDA15 are used for the bank number (data), SDA0 and SDA1 for selecting the window.

The write (Z80 read) strobe SDRD0 is [[Z80 port map|port]] address decoded inside the system when SDA[3:2] = 2 (ports $8~$B).

Internal logic: [https://github.com/furrtek/Neogeo_MiSTer_old/blob/master/io/zmc.v zmc.v (verilog)]

SDRD0 must be high before configuring banks.

To configure a bank with NEO-ZMC:
* Set SDRD0 low (prepare for new bank configuration, outputs are tri-stated ?)
* Set SDA[15:0] = '''$050B''', bank 5 in $8000~$BFFF window
* Set SDRD0 high (latch bank)
* Now when the Z80 reads the '''$8000~BFFF''' range, it will be mapped to M1 ROM '''$14000~$17FFF'''

[[Category:Audio system]]

NEO-ZMC

Furrtek — Tue, 18 Aug 2026 22:39:15 GMT

@@ Line 8: / Line 8: @@
 }}
-{{Chipname|Z80}} '''M'''emory '''C'''ontroller. Handles [[Z80]] bankswitching in cartridges allowing [[M1 ROM]]s up to 512KiB. To save pins, the Z80's upper address line are also used as data input. The chip's write strobe SDRD0 is [[Z80 port map|port]] address decoded inside the system when SDA[3:2] = 2 (ports $8~$B).
+{{Chipname|Z80}} '''M'''emory '''C'''ontroller. Handles [[Z80 bankswitching]] in cartridges allowing [[M1 ROM]]s up to 512KiB (possibly 4MiB ?). Later evolved into {{Chipname|NEO-ZMC2}}.
 =Pinout=
@@ Line 16: / Line 14: @@
 {{Pinout|NEO-ZMC|512}}
-Pins 10, 11, 12 may be M1 higher address bits ?
+Pins 10, 11, 12 may be M1 A19, A20 and A21. This would match pins available on NEO-ZMC2.
 * SDA0, SDA1, SDA8~15: Z80 address bus
 * M1 A11~M1 A18: [[M1 ROM]] address lines
 * SDRD0: Decoded write signal from {{Chipname|NEO-D0}} (latch on rising edge)
 [[Category:Audio system]]
 [[Category:Chips]]

NEO-ZMC2

Furrtek — Tue, 18 Aug 2026 03:59:04 GMT

Pinout

← Older revision		Revision as of 05:59, 18 August 2026
Line 22:		Line 22:
	*MA11~MA21: M ROM address outputs		*MA11~MA21: M ROM address outputs

	~~PRO-CT0~~ part, inputs:		Serializer part, inputs:
	*12M: 12MHz clock, outputs next pixel on falling edge.		*12M: 12MHz clock, outputs next pixel on falling edge.
	C0~C31: C ROM data bus (216 bits). Gives all the pixel data needed for a 8 pixel line.		C0~C31: C ROM data bus (216 bits). Gives all the pixel data needed for a 8 pixel line.
	*H: When high, reverse bit order of pixels shifted out (used for [[sprites]] horizontal flipping)		*H: When high, reverse bit order of pixels shifted out (used for [[sprites]] horizontal flipping)
	*EVEN: Swap A/B ~~pixels.~~		*EVEN: Swap A/B pixel outputs
	*LOAD: Latch C ROM data on ~~rising~~ edge of 12M.		*LOAD: Latch C ROM data on falling edge of 12M
			*CSDOT: Active low DOTA/DOTB output enable
			*CS: Active low GADx/GBDx output enable
	Outputs:		Outputs:
	*DOTA: High when pixel A is opaque (color > 0)		*DOTA: High when pixel A is opaque (color > 0)

Clock

Furrtek — Mon, 17 Aug 2026 20:09:58 GMT

In cartridge systems

← Older revision		Revision as of 22:09, 17 August 2026
(One intermediate revision by the same user not shown)
Line 1:		Line 1:
	Not to be confused with the [[RTC\|real time clock]] (RTC), which is clocked independently.		Not to be confused with the [[RTC\|real time clock]] (RTC), which is a time-keeping system used in the [[MVS]] and clocked independently from the rest of the system.

	[[File:Clkdistribution.png\|frame]]		[[File:Clkdistribution.png\|frame]]
Line 5:		Line 5:
	=In cartridge systems=		=In cartridge systems=

	The main system clock (often called '''mclk''') is either 24MHz (MVS) or 24.167829MHz (AES). It is generated and divided ~~by 2, 4 and 8~~ by {{Chipname\|NEO-D0}} ~~from a crystal oscillator~~, to provide the 12MHz clock for {{Chipname\|NEO-ZMC2}}, the ~~inverted~~ 6MHz ~~one~~ for [[video DAC\|video output]] and ~~also the 3MHz one for {{Chipname\|NEO-B1}}~~.		The main system clock (often called '''mclk''') is either 24MHz (MVS) or 24.167829MHz (AES). It is generated from a crystal oscillator and divided down by {{Chipname\|NEO-D0}} (or other later chips), to provide the 12MHz clock for {{Chipname\|NEO-ZMC2}}, the 6MHz pixel clock for [[video DAC\|video output]] and many others.

	{{Chipname\|LSPC2-A2}} divides it by 3 and 6 to provide the 8MHz clock for the {{Chipname\|YM2610}} and the 4MHz one for the {{Chipname\|Z80}}.		{{Chipname\|LSPC2-A2}} (or other later chips) divides it by 3 and 6 to provide the 8MHz clock for the {{Chipname\|YM2610}} and the 4MHz one for the {{Chipname\|Z80}}.

	The cartridge connector provides the 24MHz, 12MHz, 8MHz and 4MHz inverted clock signals.		The cartridge connector provides the 24MHz, 12MHz, 8MHz and 4MHz inverted clock signals.

NEO-PCM2

Furrtek — Sun, 16 Aug 2026 19:01:10 GMT

← Older revision		Revision as of 21:01, 16 August 2026
Line 9:		Line 9:

	Second version of {{Chipname\|PCM}}. [[V ROM]] (de)multiplexer, decryption and [[P ROM]] banking chip.		Second version of {{Chipname\|PCM}}. [[V ROM]] (de)multiplexer, decryption and [[P ROM]] banking chip.

			The decryption algorithm used by emulators may not be perfectly exact, this could be a possible cause of incorrect data in decrypted romsets causing minor audio glitches (Samurai Shodown V "Basara").

			Used by:

			* [[Matrimelee]]
			* [[Metal Slug 4]]
			* [[Metal Slug 5]]
			* [[Pochi and Nyaa]]
			* [[Rage of the Dragons]]
			* [[Samurai Shodown V]]
			* [[Samurai Shodown V Special]]
			* [[SNK vs. Capcom - SVC Chaos]]
			* [[The King of Fighters 2001]]
			* [[The King of Fighters 2002]]
			* [[The King of Fighters 2003]]

	=Pinout=		=Pinout=

NEO-244

Furrtek — Sat, 15 Aug 2026 23:59:55 GMT

← Older revision		Revision as of 01:59, 16 August 2026
(One intermediate revision by the same user not shown)
Line 8:		Line 8:
	}}		}}

	Just a bunch of buffers for second revision 4-slot MVS boards.		Just a bunch of buffers for second revision 4-slot MVS boards. 18 inputs to 2 x 18 always enabled outputs. See MV4F schematics.

	=Pinouts=		=Pinouts=

	~~To fix on diagram:~~
	~~Pin 18 input, output 15, 21.~~
	~~Pin 50 not an /OE, regular input, output 47, 53. Never used on any board ?~~
	~~Outputs are always enabled. See MV4F schematics. Simple 18 inputs to 2x18 outputs.~~

	==Generic==		==Generic==

File:NEO-244 pinout.png

Furrtek — Sat, 15 Aug 2026 23:58:48 GMT

Furrtek uploaded a new version of File:NEO-244 pinout.png

New page

File:Neo-253.odg

Furrtek — Sat, 15 Aug 2026 23:58:25 GMT

Furrtek deleted page File:Neo-253.odg SVGPinout

NEO-253

Furrtek — Sat, 15 Aug 2026 23:58:11 GMT

Pinout

← Older revision		Revision as of 01:58, 16 August 2026
Line 15:		Line 15:

	[[File:Neo-253_pinout.png\|512px]]		[[File:Neo-253_pinout.png\|512px]]

	~~OpenOffice Draw file: [[File:neo-253.odg]]~~

	~~Pin 56 is a general /OE.~~

	Select signals come from {{Chipname\|NEO-F0}} SLOTA and SLOTB.		Select signals come from {{Chipname\|NEO-F0}} SLOTA and SLOTB.

File:Neo-253 pinout.png

Furrtek — Sat, 15 Aug 2026 23:57:20 GMT

Furrtek uploaded a new version of File:Neo-253 pinout.png

New page

NEO-244

Furrtek — Sat, 15 Aug 2026 23:37:21 GMT

Pinouts

← Older revision		Revision as of 01:37, 16 August 2026
Line 11:		Line 11:

	=Pinouts=		=Pinouts=

			To fix on diagram:
			Pin 18 input, output 15, 21.
			Pin 50 not an /OE, regular input, output 47, 53. Never used on any board ?
			Outputs are always enabled. See MV4F schematics. Simple 18 inputs to 2x18 outputs.

	==Generic==		==Generic==

NEO-253

Furrtek — Sat, 15 Aug 2026 23:31:20 GMT

Pinout

← Older revision		Revision as of 01:31, 16 August 2026
Line 17:		Line 17:

	OpenOffice Draw file: [[File:neo-253.odg]]		OpenOffice Draw file: [[File:neo-253.odg]]

			Pin 56 is a general /OE.

	Select signals come from {{Chipname\|NEO-F0}} SLOTA and SLOTB.		Select signals come from {{Chipname\|NEO-F0}} SLOTA and SLOTB.

Wait cycle

Furrtek — Sat, 15 Aug 2026 17:49:34 GMT

Cartridge configuration

← Older revision		Revision as of 19:49, 15 August 2026
Line 10:		Line 10:

	Configuration is done by setting the levels of the following [[pinouts\|cartridge pins]]. '1' means pulled to 5V, '0' means pulled to ground. All signals are active low.		Configuration is done by setting the levels of the following [[pinouts\|cartridge pins]]. '1' means pulled to 5V, '0' means pulled to ground. All signals are active low.

			Many cartridges have all these pins tied to 5V to select full speed for both memory areas.

	{\|class="wikitable"		{\|class="wikitable"

Template:BR

Furrtek — Sat, 15 Aug 2026 14:51:11 GMT

← Older revision		Revision as of 16:51, 15 August 2026
(2 intermediate revisions by the same user not shown)
Line 1:		Line 1:
	<span style="background: #ADD; padding:2px; font-size:8pt;">		<span style="background: #ADD; padding:2px; font-size:8pt;">'''[[BIOS_RAM_locations#{{{1}}}\|{{{1}}}]]''' ({{ #ifeq: {{{1\|}}} \| BIOS_GAME_DIP \| $10FD84+}}{{ #ifeq: {{{1\|}}} \| BIOS_USER_REQUEST \| $10FDAE}}{{ #ifeq: {{{1\|}}} \| BIOS_USER_MODE \| $10FDAF}}{{ #ifeq: {{{1\|}}} \| BIOS_UPSRC \| $10FEF8}}{{ #ifeq: {{{1\|}}} \| BIOS_UPDEST \| $10FEF4}}{{ #ifeq: {{{1\|}}} \| BIOS_UPSIZE \| $10FEFC}}{{ #ifeq: {{{1\|}}} \| BIOS_UPZONE \| $10FEDA}}{{ #ifeq: {{{1\|}}} \| BIOS_UPBANK \| $10FEDB}}{{ #ifeq: {{{1\|}}} \| BIOS_DEVMODE \| $10FE80}}{{ #ifeq: {{{1\|}}} \| BIOS_COMPULSION_TIMER \| $10FDDA}}{{ #ifeq: {{{1\|}}} \| BIOS_GAME_DIP \| $10FD84}}{{ #ifeq: {{{1\|}}} \| BIOS_CREDIT_DEC1 \| $10FDB0}}{{ #ifeq: {{{1\|}}} \| BIOS_CREDIT_DEC2 \| $10FDB1}}{{ #ifeq: {{{1\|}}} \| BIOS_START_FLAG \| $10FDB4}}{{ #ifeq: {{{1\|}}} \| BIOS_PLAYER_MOD \| $10FDB6}}{{ #ifeq: {{{1\|}}} \| BIOS_P1STATUS \| $10FD94}}{{ #ifeq: {{{1\|}}} \| BIOS_MONTH \| $10FDD3}}{{ #ifeq: {{{1\|}}} \| BIOS_MVS_FLAG \| $10FD82}})</span>
	'''[[BIOS_RAM_locations#{{{1}}}\|{{{1}}}]] '''
	({{ #ifeq: {{{1\|}}} \| BIOS_GAME_DIP \| $10FD84+}}{{ #ifeq: {{{1\|}}} \| BIOS_USER_REQUEST \| $10FDAE}}{{ #ifeq: {{{1\|}}} \| BIOS_USER_MODE \| $10FDAF}}{{ #ifeq: {{{1\|}}} \| BIOS_UPSRC \| $10FEF8}}{{ #ifeq: {{{1\|}}} \| BIOS_UPDEST \| $10FEF4}}{{ #ifeq: {{{1\|}}} \| BIOS_UPSIZE \| $10FEFC}}{{ #ifeq: {{{1\|}}} \| BIOS_UPZONE \| $10FEDA}}{{ #ifeq: {{{1\|}}} \| BIOS_UPBANK \| $10FEDB}}{{ #ifeq: {{{1\|}}} \| BIOS_DEVMODE \| $10FE80}}{{ #ifeq: {{{1\|}}} \| BIOS_COMPULSION_TIMER \| $10FDDA}}
	{{ #ifeq: {{{1\|}}} \| BIOS_GAME_DIP \| $10FD84}}{{ #ifeq: {{{1\|}}} \| BIOS_CREDIT_DEC1 \| $10FDB0}}{{ #ifeq: {{{1\|}}} \| BIOS_CREDIT_DEC2 \| $10FDB1}}{{ #ifeq: {{{1\|}}} \| BIOS_START_FLAG \| $10FDB4}}{{ #ifeq: {{{1\|}}} \| BIOS_PLAYER_MOD \| $10FDB6}}{{ #ifeq: {{{1\|}}} \| BIOS_P1STATUS \| $10FD94}}{{ #ifeq: {{{1\|}}} \| BIOS_MONTH \| $10FDD3}}{{ #ifeq: {{{1\|}}} \| BIOS_MVS_FLAG \| $10FD82}}) </span>

Slot check security

Furrtek — Sat, 15 Aug 2026 14:47:32 GMT

← Older revision		Revision as of 16:47, 15 August 2026
Line 3:		Line 3:
	Slot checking is a MVS security measure added in some games produced after 1998 due to the emergence of [[bootleg MVS boards]]. It displays a warning screen and locks the game up if some checks fail.		Slot checking is a MVS security measure added in some games produced after 1998 due to the emergence of [[bootleg MVS boards]]. It displays a warning screen and locks the game up if some checks fail.

	Someone who would want to bypass this check ~~will~~ typically search for the warning text string in the [[P ROM]] and references to it in the code. Such text can't be found because the checking routine uses a XORed version of ~~the same text~~ instead, ~~certainly~~ to confuse hackers.		Someone who would want to bypass this check would typically search for the warning text string in the [[P ROM]] and references to it in the code. Such text can't be found because the checking routine uses a XORed version of it instead, to confuse hackers.

	=KOF 98=		=KOF 98=

	If the game figures out it is being run for the first time on the system (thanks to [[backup RAM]] data), it ~~forces~~ a [[watchdog]] reset. If the system ~~doesn't reset itself after a certain amount of time (~~due to the ~~eventual~~ absence of the watchdog circuit), the game displays the warning screen and locks up.		If the game figures out it is being run for the first time on the system (thanks to [[backup RAM]] data), it tries to trigger a [[watchdog]] reset. If the system continues running instead due to the absence of the watchdog circuit, the game displays the warning screen and locks up.

	=Other games=		=Other games=
Line 26:		Line 26:
	As seen in MAME's source ([[https://github.com/mamedev/mame/blob/master/src/mame/drivers/neogeo.cpp neogeo.cpp]]), a few games are known to do this check:		As seen in MAME's source ([[https://github.com/mamedev/mame/blob/master/src/mame/drivers/neogeo.cpp neogeo.cpp]]), a few games are known to do this check:

	*[[Nightmare in the Dark]]		*[[Nightmare in the Dark]] (can be disabled with an RTS at $19978)
	~~- Can~~ be disabled with RTS at $19978
	*[[The King of Fighters 2000]]		*[[The King of Fighters 2000]]
	*[[Sengoku 3]]: MVS SLOT CHECK Ver2.30 00/04/25		*[[Sengoku 3]]: MVS SLOT CHECK Ver2.30 00/04/25
Line 33:		Line 32:
	*[[Metal Slug 2]]		*[[Metal Slug 2]]
	*[[Metal Slug 5]]		*[[Metal Slug 5]]
			* [[Sengoku 3]]: Checks M1 ROM too, displays "M1-ROM ERROR." if Z80 doesn't reply to command 1 in $7FFF iterations loop.
	[[Sengoku 3]]: Checks M1 ROM too, displays "M1-ROM ERROR." if Z80 doesn't reply to command 1 in $7FFF iterations loop.

	[[Category:Games]]		[[Category:Games]]

Puzzle Bobble

Furrtek — Fri, 14 Aug 2026 21:22:36 GMT

← Older revision		Revision as of 23:22, 14 August 2026
(One intermediate revision by the same user not shown)
Line 13:		Line 13:
	\|mvs_date=1994		\|mvs_date=1994
	\|mvs_pchip=		\|mvs_pchip=
	\|mvs_pboard=~~PROGBK1~~		\|mvs_pboard=PROGTOP
	\|mvs_cboard=CHA256		\|mvs_cboard=CHA256
	\|cd_release=y		\|cd_release=y
Line 21:		Line 21:
	}}		}}

	~~Some~~ [[Power Spikes II]] MVS cartridges were converted to Puzzle Bobble by SNK by doing the following:		Many [[Power Spikes II]] MVS cartridges were converted to Puzzle Bobble by SNK by doing the following:
	* Replaced the Power Spikes II P1 ROM by the Puzzle Bobble "d96-07" P1 ROM in the EP1 spot.		* Replaced the Power Spikes II P1 ROM by the Puzzle Bobble "d96-07" P1 ROM in the EP1 spot.
	* Replaced the Power Spikes II V3 ROM by the Puzzle Bobble "d96-01" V3 ROM, also added the "d96-05" V4 ROM.		* Replaced the Power Spikes II V3 ROM by the Puzzle Bobble "d96-01" V3 ROM, also added the "d96-05" V4 ROM.

Memory mapped registers

ArcadeTV — Wed, 12 Aug 2026 10:33:33 GMT

System registers: Correction: (From the off. SNK Docs) $3A000F -> Palette Bank 0, $3A001F -> Palette Bank 1

← Older revision		Revision as of 12:33, 12 August 2026
Line 466:		Line 466:
	\|-		\|-
	\|$3A000F		\|$3A000F
	\|~~REG_PALBANK1~~		\|REG_PALBANK0
	\|Use [[palette RAM\|palette]] bank 1		\|Use [[palette RAM\|palette]] bank 0
	\|-		\|-
	\|$3A001F		\|$3A001F
	\|~~REG_PALBANK0~~		\|REG_PALBANK1
	\|Use palette bank 0		\|Use palette bank 1
	\|}		\|}

68k ASM defines

ArcadeTV — Wed, 12 Aug 2026 10:10:49 GMT

corrected: BIOS_P2TIMER equ $10FD9F because $10FD99 is BIOS_P1TIMER

← Older revision		Revision as of 12:10, 12 August 2026
Line 105:		Line 105:
	BIOS_P2CHANGE equ $10FD9D		BIOS_P2CHANGE equ $10FD9D
	BIOS_P2REPEAT equ $10FD9E		BIOS_P2REPEAT equ $10FD9E
	BIOS_P2TIMER equ $~~10FD99~~		BIOS_P2TIMER equ $10FD9F

	BIOS_STATCURNT equ $10FDAC		BIOS_STATCURNT equ $10FDAC