68k interrupts

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Revision as of 06:58, 11 October 2018 by Furrtek (talk | contribs) (Changed wording, clarification regarding irq mask)
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The cartridge systems use 3 auto-vectored interrupt levels. The CD systems use 3 additional vectored interrupts.

Interrupts must to be acknowledged for them to re-trigger in the future by writing to register REG_IRQACK.

  • bit 2: Acknowledge v-blank interrupt
  • bit 1: Acknowledge timer interrupt
  • bit 0: Acknowledge reset interrupt

Multiple bits can be set:

move	#$0007,REG_IRQACK     ; Acknowledge all interrupts

Bits 8~10 of the 68k's SR register can be used to mask them:

move	#$2000,SR     ; Accept all interrupts (+Supervisor mode)
move	#$2700,SR     ; Ignore all interrupts (+Supervisor mode)

Note that the 68k's interrupt mask is different from the interrupt configuration bits in REG_LSPCMODE.

Vertical blank interrupt

The v-blank interrupt is almost always used. It occurs when the rendering of a frame is about to start (~60 times per second). See display timing.

Timer interrupt

The timer interrupt's behavior can be programmed through the GPU's memory mapped registers. It is triggered by a 32-bit down counter clocked by the 6MHz pixel clock, and a corresponding reset register. When the counter reaches 0, an interrupt is generated. Intervals can range from 166.7ns (dangerous interrupt flood) to 11.9 minutes (?).

It can be used for special video effects such as scanline effects, for example:

AES/MVS interrupt levels

  • Level 1: V-blank
  • Level 2: Timer
  • Level 3: Pending after reset

CD interrupt levels

The V-blank and Timer levels are swapped compared to the cartridge systems.

  • Level 1: Timer
  • Level 2: V-blank
  • Level 3: Not used ?
  • Vector 21: CD host decoder interrupt (data ready)
  • Vector 22: CD drive communication start
  • Vector 23: Used but not understood