Clock: Difference between revisions

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==Signals==
==Signals==


{{Sig|24M|24M}}, {{Sig|12M|12M}}, {{Sig|68KCLK|68KCLK}}, {{Sig|68KCLKB|68KCLKB}}, {{Sig|8M|8M}}, {{Sig|6MB|8MB}}, {{Sig|4M|4M}}, {{Sig|4MB|4MB}}, {{Sig|1MB|1MB}}
{{Sig|24M|24M}} (~24MHz), {{Sig|12M|12M}} (12MHz), {{Sig|68KCLK|68KCLK}} (12MHz), {{Sig|68KCLKB|68KCLKB}} (12MHz), {{Sig|8M|8M}} (8MHz), {{Sig|6MB|6MB}} (6MHz), {{Sig|4M|4M}} (12MHz), {{Sig|4MB|4MB}} (4MHz), {{Sig|1MB|1MB}} ('''3MHz''')


=In CD systems=
=In CD systems=

Revision as of 11:29, 30 September 2016

Not to be confused with the real time clock (RTC), which is clocked independently.

File:Clkdistribution.png

In cartridge systems

The main system clock (often called mclk) is either 24MHz (MVS) or 24.167829MHz (AES). It is generated and divided by 2, 4 and 8 by NEO-D0 from a crystal oscillator, to provide the 12MHz clock for NEO-ZMC2, the inverted 6MHz one for video output and also the 3MHz one for NEO-B1.

LSPC2-A2 divides it by 3 and 6 to provide the 8MHz clock for the YM2610 and the 4MHz one for the Z80.

The cartridge connector provides the 24MHz, 12MHz, 8MHz and 4MHz inverted clock signals.

A second quartz oscillator is used for generating the color burst needed by composite video, for the video encoders.

A third 32768Hz quartz oscillator is used for the RTC.

Phase relations

Signals

24M (~24MHz), 12M (12MHz), 68KCLK (12MHz), 68KCLKB (12MHz), 8M (8MHz), 6MB (6MHz), 4M (12MHz), 4MB (4MHz), 1MB (3MHz)

In CD systems

File:Cd2 quartz.jpg
System clock and video PLL circuit on a CDM3-2 board.

NEO-GRC ?