Display timing: Difference between revisions

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[[File:disp.png|right|frame]]
In both NTSC or PAL mode, the full display is always 384 * 264 pixels.
In NTSC mode, the display is 320x224 pixels. In PAL mode, it is 320x256 pixels.


Upper 9 bits of register [[Memory mapped registers|'''REG_LSPCMODE''']] ($3C0006):
See [[frame size]] for the '''active''' display size.
*$00F8-$00FF : Vertical sync (8)
*$0100-$010F : Top border (16)
*$0110-$01EF : Active display (224)
*$01F0-$01FF : Bottom border (16)


From mvstech.txt (by Charles MacDonald):
'''mclk''' refers to the 24MHz master [[clock]]. A pixel lasts 4 mclk.
<pre>
Measured in reference to main 24 MHz clock (mclk):


Horizontal timing
Notes: After /RESET goes high, SYNC goes high after 1399 mclk.


Pulse widths:                                
[[File:Sync_timing.png|1024px]]
  111 mclks horizontal sync                    27.75 pixels
  256 mclks horizontal blanking                  64 pixels
1280 mclks active display                      320 pixels
1536 mclks per scanline                        384 pixels


State to state timing:
{{Sig|CHBL|CHBL}} is the horizontal blanking signal, it tells {{Chipname|NEO-B1}} to output color 0 of [[palettes|palette]] 0, which is the [[palettes|reference color]].
  118 mclks /HSYNC rising to /HBLANK rising    29.5 pixels (left border)
1280 mclks /HBLANK rising to /HBLANK falling    320 pixels (display)
  27 mclks /HBLANK falling to /HSYNC falling  6.75 pixels (right border)
  111 mclks /HSYNC falling to /HSYNC rising    27.75 pixels (horizontal sync)


384 pixels per scanline: (rounding up)
{{Sig|BNKB|BNKB}} is the vertical blanking signal, it forces the [[video DAC]] inputs to 0.


  28 pixels horizontal sync pulse width
=Horizontal timing=
  29 pixels /HSYNC low to /HBLANK high
320 pixels /HBLANK high to /HBLANK low
  7 pixels /HBLANK low to /HSYNC low


Vertical timing
[[File:Timing_video_lines.png]]
[[File:Timing_video_hblank.png]]


264 scanlines per frame:
* 112 mclks (28px) horizontal sync pulse
* 112 mclks (28px) back porch
* 1280 mclks (320px) active display
* 32 mclks (8px) front porch


  8 scanlines vertical sync pulse
* 32 + 112 + 112 = 256 mclks (64px) horizontal blanking
  16 scanlines top border
* 32 + 112 + 112 + 1280 = 1536 mclks (384px) total per scanline
224 scanlines active display
  16 scanlines bottom border


Frame timing
[[File:Timing_video_vblank.png]]


Frame rate is 6 MHz / 384 / 264 = 59.18 Hz.
BNKB (blanking to 0V) changes state 14px after H-sync (middle of the back porch)
</pre>
 
=Vertical timing=
 
Corrected from and added on from mvstech.txt (by Charles MacDonald).
 
There are 264 scanlines per frame:
* 8 scanlines vertical sync pulse
* 16 scanlines top border (active in PAL, blanked in NTSC)
* 224 scanlines active display
* 16 scanlines bottom border (active in PAL, blanked in NTSC)
 
Upper 9 bits of register {{Reg|REG_LSPCMODE}}:
* $0F8~$0FF : Vertical sync (8px)
* $100~$10F : Top border (16px)
* $110~$1EF : Active display (224px)
* $1F0~$1FF : Bottom border (16px)
 
=Frame timing=
 
See [[framerate]].


[[Category:Video system]]
[[Category:Video system]]

Revision as of 09:38, 19 March 2017

In both NTSC or PAL mode, the full display is always 384 * 264 pixels.

See frame size for the active display size.

mclk refers to the 24MHz master clock. A pixel lasts 4 mclk.

Notes: After /RESET goes high, SYNC goes high after 1399 mclk.

CHBL is the horizontal blanking signal, it tells NEO-B1 to output color 0 of palette 0, which is the reference color.

BNKB is the vertical blanking signal, it forces the video DAC inputs to 0.

Horizontal timing

  • 112 mclks (28px) horizontal sync pulse
  • 112 mclks (28px) back porch
  • 1280 mclks (320px) active display
  • 32 mclks (8px) front porch
  • 32 + 112 + 112 = 256 mclks (64px) horizontal blanking
  • 32 + 112 + 112 + 1280 = 1536 mclks (384px) total per scanline

BNKB (blanking to 0V) changes state 14px after H-sync (middle of the back porch)

Vertical timing

Corrected from and added on from mvstech.txt (by Charles MacDonald).

There are 264 scanlines per frame:

  • 8 scanlines vertical sync pulse
  • 16 scanlines top border (active in PAL, blanked in NTSC)
  • 224 scanlines active display
  • 16 scanlines bottom border (active in PAL, blanked in NTSC)

Upper 9 bits of register REG_LSPCMODE:

  • $0F8~$0FF : Vertical sync (8px)
  • $100~$10F : Top border (16px)
  • $110~$1EF : Active display (224px)
  • $1F0~$1FF : Bottom border (16px)

Frame timing

See framerate.

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