Display timing

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In both NTSC or PAL mode, the full display is always 384 * 264 pixels.

See frame size for the active display size.

mclk refers to the 24MHz master clock. A pixel lasts 4 mclk.

Notes: After /RESET goes high, SYNC goes high after 1399 mclk.

Sync timing.png

Sig.pngCHBL is the horizontal blanking signal, it tells Chipicon.png NEO-B1 to output color 0 of palette 0, which is the reference color.

Sig.pngBNKB is the vertical blanking signal, it forces the video DAC inputs to 0.

Horizontal timing

Timing video lines.png Timing video hblank.png

  • 112 mclks (28px) horizontal sync pulse
  • 112 mclks (28px) back porch
  • 1280 mclks (320px) active display
  • 32 mclks (8px) front porch
  • 32 + 112 + 112 = 256 mclks (64px) horizontal blanking
  • 32 + 112 + 112 + 1280 = 1536 mclks (384px) total per scanline

Timing video vblank.png

BNKB (blanking to 0V) changes state 14px after H-sync (middle of the back porch)

Vertical timing

Corrected from and added on from mvstech.txt (by Charles MacDonald).

There are 264 scanlines per frame:

  • 8 scanlines vertical sync pulse
  • 16 scanlines top border (active in PAL, blanked in NTSC)
  • 224 scanlines active display
  • 16 scanlines bottom border (active in PAL, blanked in NTSC)

Upper 9 bits of register Reg.png REG_LSPCMODE:

  • $0F8~$0FF : Vertical sync (8px)
  • $100~$10F : Top border (16px)
  • $110~$1EF : Active display (224px)
  • $1F0~$1FF : Bottom border (16px)

Frame timing

See framerate.