Graphics pipeline: Difference between revisions
Jump to navigation
Jump to search
mNo edit summary |
mNo edit summary |
||
| Line 1: | Line 1: | ||
=First gen PRO chipset= | =First gen PRO chipset= | ||
*[[ | *[[LSPC-A0]] | ||
*[[PRO-B0]] | *[[PRO-B0]] | ||
*[[PRO-CT0]] | *[[PRO-CT0]] | ||
Revision as of 02:39, 23 December 2015
First gen PRO chipset
Second gen chipset
MVS
AES
CD gen chipset
The sprite and fix DRAM bus can be switched between from NEO-OFC and the 68k bus for upload of graphics, thus allowing software rendering.