LSPC2-A2: Difference between revisions

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==Pinout==
==Pinout==
LSPC2-A2


D0~D3:2~5
(Max size:[[:File:lspc2-a2_pinout.png]])<br>
GND:6
[[File:lspc2-a2_pinout.png|640px]]
D4~D6:7~9
D7:10
11
VCC:12
D8~D11:13~16
GND:17
D12~D15:18~21
GND:22
B0~B4:23~27
28
B5~B8:29~32
VCC:33
B9~B13:34~38
GND:39
B14:40
E0~E8:41~49
GND:50
E9~E13:51~55
VCC:56?
E14~E15:57~58
BOE:59?
BWE:60?
GND:61
REF:62?
63
INT:64
DOTA:65
DOTB:66
F0~F4:67~71
GND:72
F5~F8:73~76
VCC:77
F9,F10:78,79
F11~F13:80~82
GND:83
F14,F15:84,85
86
87
88
89
90
C3~C5:91~93
GND:94
C6~C10:95~99
VCC:100
4H:101
CC4:102
PK1:103
PK2:104
GND:105
1H1:106
2H1:107
SCH?:108
H:109
EVEN1:110
EVEN2:111
P0~P3:112~115
GND:116
P4~P7:117~120
VCC:121
P8~P13:122~126
GND:127
128
P14~P15:129,130
DIVO:131
TST0:132
133
P16~P19:134~137
GND:138
139
140
141
142
DIVI:143
VCC:144
VCS:145
RESETF:146
LOAD:147
148
GND?:149
SYNC:150
?NK2:151
CM?L:152
SL1?:153
SL2?:154
WE1~WE4:155~158
CK1:159
GND:160
CK2~CK4:161~163
SS1,SS2:164~165
VCC:166
IP0:167
IP1:168
RES:169
24H?:170
GND:171
LSPOE:172
LSPWE:173
A1~A3:174~176


CWE:??
Need to find: 28,87,128,133
SW?:14?
 
TST:??
*A1~A3: [[68k]] address bus
*D0~D15: [[68k]] data bus
*B0~B14: VRAM bank 0 address bus
*E0~E15: VRAM bank 0 data bus
*C0~C10: VRAM bank 1 address bus
*F0~F15: VRAM bank 1 data bus
*P0~P13: "Internal" multiplexed bus
*/BOE,/BWE: VRAM bank 0 read/write
*/CWE: VRAM bank 1 write enable
*/LSPOE,/LSPWE: Chip read/write (VRAM access,...)
*/RES: Reset
*1H1/2H1:
*24M: 24MHz clock ?
*4M: 4MHz clock ?
*CC4:
*DIVI/DIVO: Frequency divider ?
*DOTA/DOTB: See [[NEO-ZMC2]]
*EVEN1/EVEN2:
*H:
*INT:
*IP0/IP1:
*LOAD:
*PK1/PK2:
*REF:
*RESETF:
*SCH?:
*SL1?/SL2?:
*SW?:148?
*SYNC:
*TST:
*TST0:
*VCS:
*WE1~WE4,CK1~CK4,SS1,SS2: [[NEO-B1]] communication
 
*?NK2:
*CM?L:


[[Category:Chips]]
[[Category:Chips]]

Revision as of 14:17, 11 March 2011

LSPC2-A2 graphics chip found in an AES system.

The LSPC chips are only found in cartridge systems, they provide pixel data for the Video DAC. (the line buffer for color data is most likely in the NEO-B1 but don't know for sure...).

LSPC-A0 chips can be found on early MVS slots and AES systems and work alongside the PRO-B0 chip. LSPC2-A2 chips are found in second revision systems and work with the NEO-B1 chip.

Graphics

Two separate buses run in parallel to fetch data from VRAM for rendering the screen. Each bus connects to a pair of 8bit chips, forming a 16bit bus.

  • VRAM 0000-7FFF - 2x 62256/43256 (120ns(?) or faster)
  • VRAM 8000-87FF - 2x 5814/5863/6116 (45ns or faster)

The LSPC arbitrates all VRAM access and allows for 68k access at any time during rendering without display glitches. The interface is slow and data writes are ignored when games write VRAM too quickly, especially with overclocked systems *specifics go here maybe*.

It shares a 24bit bus with the NEO-B1 which goes out to the CHA connector on the cart slot for addressing S ROMs, C ROMs and the on-board LO ROM.

IRQ

All 3 68k interrupts are generated by this chip.

Pinout

(Max size:File:lspc2-a2_pinout.png)
File:Lspc2-a2 pinout.png

Need to find: 28,87,128,133

  • A1~A3: 68k address bus
  • D0~D15: 68k data bus
  • B0~B14: VRAM bank 0 address bus
  • E0~E15: VRAM bank 0 data bus
  • C0~C10: VRAM bank 1 address bus
  • F0~F15: VRAM bank 1 data bus
  • P0~P13: "Internal" multiplexed bus
  • /BOE,/BWE: VRAM bank 0 read/write
  • /CWE: VRAM bank 1 write enable
  • /LSPOE,/LSPWE: Chip read/write (VRAM access,...)
  • /RES: Reset
  • 1H1/2H1:
  • 24M: 24MHz clock ?
  • 4M: 4MHz clock ?
  • CC4:
  • DIVI/DIVO: Frequency divider ?
  • DOTA/DOTB: See NEO-ZMC2
  • EVEN1/EVEN2:
  • H:
  • INT:
  • IP0/IP1:
  • LOAD:
  • PK1/PK2:
  • REF:
  • RESETF:
  • SCH?:
  • SL1?/SL2?:
  • SW?:148?
  • SYNC:
  • TST:
  • TST0:
  • VCS:
  • WE1~WE4,CK1~CK4,SS1,SS2: NEO-B1 communication
  • ?NK2:
  • CM?L: