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Aes lspc2a2.jpg
Package QFP176
Manufacturer Logo fujitsu.jpg
First use 1992 ?
Approx. gates ?
Used on Pcb.pngNEO-AES3-4 Pcb.pngMV1F


LSPC2-A2 is the second generation Line SPrite Controller, it is only found in cartridge systems.

  • Generates Chipicon.png S ROM, Chipicon.png C ROM and Chipicon.png LO ROM addresses based on current display line and VRAM content
  • Sync output
  • Chipicon.png NEO-B1 control
  • 68k IRQs
  • 68k VRAM access arbitration

First generation Chipicon.png LSPC-A0 chips can be found in earlier systems.


Two separate busses run in parallel to fetch data from the two VRAM zones. Each bus connects to a pair of 8-bit RAM chips.

  • VRAM $0000~$7FFF - 2x 62256/43256
  • VRAM $8000~$87FF - 2x 5814/5863/6116

The LSPC arbitrates all VRAM access and allows for Chipicon.png 68k access at any time during rendering without display glitches if they aren't made too fast. See VRAM for timing requirements.

It shares the 24-bit P bus (P0~P23) with NEO-B1 and the on-board L0 ROM, which goes out to the CHA connector on the cart slot for addressing Chipicon.png S ROMs and Chipicon.png C ROMs.


All 3 possible 68k interrupts are generated by this chip.


(Max size:File:lspc2-a2_pinout.png)
Lspc2-a2 pinout.png

OpenOffice Draw file: File:Lspc2-a2.odg

  • A1~A3: 68k address bus
  • D0~D15: 68k data bus
  • /LSPOE,/LSPWE: Chip read/write, provided by Chipicon.png NEO-C1
  • B0~B14: VRAM bank 0 address bus
  • E0~E15: VRAM bank 0 data bus
  • /BOE,/BWE: VRAM bank 0 read/write
  • C0~C10: VRAM bank 1 address bus
  • /CWE: VRAM bank 1 write enable
  • F0~F15: VRAM bank 1 data bus
  • P0~P23: Multiplexed P bus
  • /RES: Reset
  • 1H1: Clock used by NEO-B1
  • 2H1: S ROM A3
  • 24M: 24MHz clock input from Chipicon.png NEO-D0
  • 8M: 8MHz clock output to the Chipicon.png YM2610
  • 6M: 6MHz clock output to the cartridge connector
  • 4M: 4MHz clock output to the Chipicon.png Z80
  • CA4: C ROM A4
  • DIVI/DIVO/REF: Independant frequency division circuit used by the video PLL
  • EVEN1, EVEN2, H, LOAD: C ROM serializer control, see Chipicon.png NEO-ZMC2
  • DOTA/DOTB: Pixel opacity inputs from NEO-ZMC2
  • IP0/IP1: 68k interrupt lines
  • PK1: Clock to latch C ROM address from P bus
  • PK2: Clock to latch S ROM address from P bus
  • RESETP: Reset pulse output
  • 6MB: Pixel clock output
  • SYNC: Video sync signal output
  • TST: Enable test mode, uses D0~D10 (always tied to ground)
  • VCS: L0 ROM output enable
  • WE1~WE4: Synchronous write enable signals for NEO-B1
  • CK1~CK4: Clocks for rendering and output from NEO-B1
  • SS1, SS2: NEO-B1 control
  • BNKB: Video blanking (for V-blank)
  • CHBL: Video blanking (for H-blank, sent to NEO-B1)
  • PAL/NTSC: Video mode selection, latched during reset