Memory mapped registers: Difference between revisions

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{{8BitRegister|Freeze|1|Freeplay|1|Enable [[Multiplayer]] configuration|1|Communication identification code|2|0:Normal controller<br>1:Mahjong keyboard|1|0:One coin chute<br>1:Two coin chutes|1|Settings mode|1}}
{{8BitRegister|Freeze|1|Freeplay|1|Enable [[Multiplayer]] configuration|1|Communication identification code|2|0:Normal controller<br>1:Mahjong keyboard|1|0:One coin chute<br>1:Two coin chutes|1|Settings mode|1}}
|Kick watchdog
|Kick watchdog
|[[NEO-F0]] (read)
|[[NEO-F0]] (read), [[NEO-B1]] (write)
|-
|-
|$300081~?, odd bytes
|$300081~?, odd bytes
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|[[68k/Z80 communication|Read Z80 reply code]]
|[[68k/Z80 communication|Read Z80 reply code]]
|Send command to Z80
|Send command to Z80
||[[NEO-C1]]
|[[NEO-C1]]
|-
|-
|$320001~?, odd bytes
|$320001~?, odd bytes
|REG_STATUS_A  
|REG_STATUS_A  
|Switch inputs are active low
|Switch inputs are active low
{{8BitRegister|NEC D4990 data bit|1|NEC D4990 time pulse|1|0 on 4SLOT 1 on 6SLOT|1|Coin 4|1|Coin 3|1|Service|1|Coin 2|1|Coin 1|1}}
{{8BitRegister|NEC D4990 data bit|1|NEC D4990 time pulse|1|0:4SLOT<br>1:6SLOT|1|Coin-in 4|1|Coin-in 3|1|Service|1|Coin-in 2|1|Coin-in 1|1}}
|?
|?
|[[NEO-F0]]
|[[NEO-F0]]
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|Joypad ports [[Pinouts#joypad ports|outputs]]
|Joypad ports [[Pinouts#joypad ports|outputs]]
{{8BitRegister|?|2|P2 outputs|3|P1 outputs|3}}
{{8BitRegister|?|2|P2 outputs|3|P1 outputs|3}}
MAME select_controller
|[[NEO-D0]]
|[[NEO-D0]]
|-
|-
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|?
|?
|{{8BitRegister|?|5|Slot #|3|}}
|{{8BitRegister|?|5|Slot #|3|}}
(On home systems this address is a mirror of REG_POUTPUT)
(Mirror of REG_POUTPUT on the AES)
|[[NEO-F0]]
|[[NEO-F0]]
|-
|-
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|REG_LEDLATCHES
|REG_LEDLATCHES
|?
|?
|MAME set_output_latch {{8BitRegister|?|2|Latch LED2 data|1|Latch LED1 data|1|Latch EL panel data|1|?|3}}
|{{8BitRegister|?|2|Latch LED2 data|1|Latch LED1 data|1|Latch EL panel data|1|?|3}}
Data is latched on falling edge (1 to 0 transition)
LED data is latched on 1 to 0 transition.
|[[NEO-F0]]
|[[NEO-F0]]
|-
|-
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|REG_LEDDATA
|REG_LEDDATA
|?
|?
|MAME set_output_data (for LEDs and EL panel)
|8-bit data for LEDs and EL panel. See [[MV-LED]].
|[[NEO-F0]]
|[[NEO-F0]]
|-
|-
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|?
|?
|MAME upd4990a_control_16_w ([[Calendar]]){{8BitRegister||5|D4990 Strobe|1|D4990 Clock|1|D4990 DIN|1|}}
|MAME upd4990a_control_16_w ([[Calendar]]){{8BitRegister||5|D4990 Strobe|1|D4990 Clock|1|D4990 DIN|1|}}
|[[NEO-F0]]?
|[[NEO-F0]]
|-
|-
|$380061~?, odd bytes
|$380061~?, odd bytes
|?
|REG_RESETCC1
|
|
|Chute 1 coin counter -> High
|Any, [[coin counter]] 1 floats
|[[NEO-I0]]
|[[NEO-I0]]
|-
|-
|$380063~?, odd bytes
|$380063~?, odd bytes
|?
|REG_RESETCC2
|
|
|Chute 2 coin counter -> High
|Any, coin counter 2 floats
||[[NEO-I0]]
||[[NEO-I0]]
|-
|-
|$380065~?, odd bytes
|$380065~?, odd bytes
|?
|REG_RESETCL1
|
|
|Chute 1 coin lockout -> High
|Any, [[coin lockout]] 1 floats
|[[NEO-I0]]
|[[NEO-I0]]
|-
|-
|$380067~?, odd bytes
|$380067~?, odd bytes
|?
|REG_RESETCL2
|
|
|Chute 2 coin lockout -> High
|Any, coin lockout 2 floats
|[[NEO-I0]]
|[[NEO-I0]]
|-
|-
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|-
|-
|$3800E1~?, odd bytes
|$3800E1~?, odd bytes
|REG_SETCC1
|?
|?
|?
|Any, coin counter 1 sinks current
|Chute 1 coin counter -> Low
|[[NEO-I0]]
|[[NEO-I0]]
|-
|-
|$3800E3~?, odd bytes
|$3800E3~?, odd bytes
|REG_SETCC2
|?
|?
|?
|Any, coin counter 2 sinks current
|Chute 2 coin counter -> Low
|[[NEO-I0]]
|[[NEO-I0]]
|-
|-
|$3800E5~?, odd bytes
|$3800E5~?, odd bytes
|REG_SETCL1
|?
|?
|?
|Any, coin lockout 1 sinks current
|Chute 1 coin lockout -> Low
|[[NEO-I0]]
|[[NEO-I0]]
|-
|-
|$3800E7~?, odd bytes
|$3800E7~?, odd bytes
|REG_SETCL2
|?
|?
|?
|Any, coin lockout 2 sinks current
|Chute 2 coin lockout -> Low
|[[NEO-I0]]
|[[NEO-I0]]
|}
|}
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|Use the cart's vector table
|Use the cart's vector table
|-
|-
|$3A0005
|$3A0005~?, odd bytes
|REG_CRDUNLOCK1
|REG_CRDUNLOCK1
|Enable writes to memory card (use REG_CRDUNLOCK2 too)
|Enable writes to memory card (use REG_CRDUNLOCK2 too)
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==Video registers==
==Video registers==
Handled by the [[GPU]]s. Byte writes only work on even addresses and stores the same data in the MSB and LSB. Odd addresses aren't mapped ?
Handled by the [[GPU]]s. Byte writes only work on even addresses and stores the same data in the MSB and LSB. Odd addresses aren't mapped ?
{| class="regdef"
{| class="regdef"
|'''Address'''
|'''Address'''
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|REG_TIMERSTOP
|REG_TIMERSTOP
|Invalid
|Invalid
|Bit 0=1: Stop timer counter for 32 raster lines when in PAL mode
|Bit 0=1: Stops timer counter during first and last 16 lines (32 total) when in PAL mode.
|}
|}


Revision as of 01:19, 3 March 2016

I/O registers

Odd/even infos and mirroring ranges aren't tested !

Address Name Read Write Handled by
$300000~$31FFFE, even bytes REG_P1CNT Player 1 controls or trackball data (active low)
Bit 7 6 5 4 3 2 1 0
Def D CBARightLeftDownUp
? NEO-C1
$300001~?, odd bytes REG_DIPSW Hardware DIPs (active low)
Bit 7 6 5 4 3 2 1 0
Def Freeze FreeplayEnable Multiplayer configurationCommunication identification code0:Normal controller
1:Mahjong keyboard		0:One coin chute
1:Two coin chutes		Settings mode
Kick watchdog NEO-F0 (read), NEO-B1 (write)
$300081~?, odd bytes ? IN01 to D7 (test switch) and TYPE to D6, see NEO-F0 ? NEO-F0
$320000~$33FFFE, even bytes REG_SOUND Read Z80 reply code Send command to Z80 NEO-C1
$320001~?, odd bytes REG_STATUS_A Switch inputs are active low
Bit 7 6 5 4 3 2 1 0
Def NEC D4990 data bit NEC D4990 time pulse0:4SLOT
1:6SLOT		Coin-in 4Coin-in 3ServiceCoin-in 2Coin-in 1
? NEO-F0
$340000~$37FFFE, even bytes REG_P2CNT Player 2 controls (active low)
Bit 7 6 5 4 3 2 1 0
Def D CBARightLeftDownUp
? NEO-C1
$380000~$3BFFFE(?), even bytes REG_STATUS_B Aux inputs (active low)
Bit 7 6 5 4 3 2 1 0
Def 0:AES
1:MVS		 Memory card
write protected		Memory card
inserted if 00		Select P2Start P2Select P1Start P1
? NEO-C1
$380001~?, odd bytes REG_POUTPUT ? Joypad ports outputs
Bit 7 6 5 4 3 2 1 0
Def ? P2 outputsP1 outputs
NEO-D0
$380011~?, odd bytes REG_CRDBANK ?
Bit 7 6 5 4 3 2 1 0
Def Memory card bank selection
NEO-D0
$380021~?, odd bytes REG_SLOT ?
Bit 7 6 5 4 3 2 1 0
Def ? Slot #

(Mirror of REG_POUTPUT on the AES)

NEO-F0
$380031~?, odd bytes REG_LEDLATCHES ?
Bit 7 6 5 4 3 2 1 0
Def ? Latch LED2 dataLatch LED1 dataLatch EL panel data?

LED data is latched on 1 to 0 transition.

NEO-F0
$380041~?, odd bytes REG_LEDDATA ? 8-bit data for LEDs and EL panel. See MV-LED. NEO-F0
$380051~?, odd bytes REG_RTCCTRL ? MAME upd4990a_control_16_w (Calendar)
Bit 7 6 5 4 3 2 1 0
Def D4990 StrobeD4990 ClockD4990 DIN
NEO-F0
$380061~?, odd bytes REG_RESETCC1 Any, coin counter 1 floats NEO-I0
$380063~?, odd bytes REG_RESETCC2 Any, coin counter 2 floats NEO-I0
$380065~?, odd bytes REG_RESETCL1 Any, coin lockout 1 floats NEO-I0
$380067~?, odd bytes REG_RESETCL2 Any, coin lockout 2 floats NEO-I0
$3800D1~?, odd bytes ? Write to RTC

uPD4990AWrite(byteValue & 2, byteValue & 4, byteValue & 1);

?
$3800E1~?, odd bytes REG_SETCC1 ? Any, coin counter 1 sinks current NEO-I0
$3800E3~?, odd bytes REG_SETCC2 ? Any, coin counter 2 sinks current NEO-I0
$3800E5~?, odd bytes REG_SETCL1 ? Any, coin lockout 1 sinks current NEO-I0
$3800E7~?, odd bytes REG_SETCL2 ? Any, coin lockout 2 sinks current NEO-I0

System registers

Handled by a 74HC259 adressable latch on cart systems. Byte writes only.

Address Name Write
$3A0001~?, odd bytes REG_NOSHADOW Normal video output
$3A0011~?, odd bytes REG_SHADOW Darken video output
$3A0003~?, odd bytes REG_SWPBIOS BIOS vector table
$3A0013~?, odd bytes REG_SWPROM Use the cart's vector table
$3A0005~?, odd bytes REG_CRDUNLOCK1 Enable writes to memory card (use REG_CRDUNLOCK2 too)
$3A0015~?, odd bytes REG_CRDLOCK1 Disable writes to memory card
$3A0007~?, odd bytes REG_CRDLOCK2 Disable writes to memory card
$3A0017~?, odd bytes REG_CRDUNLOCK2 Enable writes to memory card (use REG_CRDUNLOCK1 too)
$3A0009~?, odd bytes REG_CRDREGSEL Enable "Register select" for memory card
$3A0019~?, odd bytes REG_CRDNORMAL Disable "Register select" for memory card
$3A000B~?, odd bytes REG_BRDFIX Use the embedded SFIX and SM1 ROM
$3A001B~?, odd bytes REG_CRTFIX Use the cart's S ROM and M1 ROM
$3A000D~?, odd bytes REG_SRAMLOCK Write-protects backup RAM (MVS)
$3A001D~?, odd bytes REG_SRAMULOCK Unprotects backup RAM (MVS)
$3A000F~?, odd bytes REG_PALBANK1 Use palette bank 1
$3A001F~?, odd bytes REG_PALBANK0 Use palette bank 0


Video registers

Handled by the GPUs. Byte writes only work on even addresses and stores the same data in the MSB and LSB. Odd addresses aren't mapped ?

Address Name Read Write
$3C0000 REG_VRAMADDR Read VRAM (address isn't changed) Sets VRAM address
$3C0002 REG_VRAMRW Read VRAM (address isn't changed) Write VRAM
$3C0004 REG_VRAMMOD Reads VRAM address modulo Sets VRAM address modulo (signed)
$3C0006 REG_LSPCMODE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Def Raster line counter.
See Display timing		 -1:50Hz
0:60Hz (LSPC2 only)		Auto animation counter
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Def Auto animation speed
(in frames)		 Timer interrupt
mode		Timer interrupt enableDisable auto animation?
$3C0008 REG_TIMERHIGH Invalid MSBs of timer reload value.
$3C000A REG_TIMERLOW Invalid LSBs of timer reload value.
$3C000C REG_IRQACK Invalid Interrupt Acknowledge (byte !).
Bit 7 6 5 4 3 2 1 0
Def ? Ack VBlankAck HBlankAck IRQ3
$3C000E REG_TIMERSTOP Invalid Bit 0=1: Stops timer counter during first and last 16 lines (32 total) when in PAL mode.


NeoGeo CD registers

NEO-MGA / LC8953 / LC98000 ?

Address Name Size Read Write Handled by
$FF0002 ? Word ? NeoRaine load_files, really interrupt mask ? ?
$FF0004 ? Word ? CDM3-2 BIOS writes 0,1,3,7 ?
$FF0006 ? Word ? CDM3-2 BIOS writes 0x71FF, CDZ writes 0x71FF ?
$FF0008 ? Word ? CDM3-2 BIOS writes 0x0000, CDZ writes 0x0000 ?
$FF000A ? Word ? CDM3-2 BIOS writes 0x7E40, CDZ writes 0x7E00 ?
$FF000E ? Byte ? CDM3-2 BIOS writes $3F,$3C ?
$FF000F ? Byte ? NeoCDIRQUpdate(byteValue);

CDM3-2 BIOS writes $20,$10,$08,$04

?
$FF0011 ? Byte ? CDM3-2 BIOS writes $FE ?
$FF0017 ? Byte nNeoCDMode

CDM3-2 BIOS read/writes bit 0

?
$FF0061 ? Byte ? Bit 6: Execute DMA microcode LC8953
$FF0064~$FF0073 ? (Long)words ? Registers used by microcode (NeoRaine upload_param)
$FF007E~$FF008F ? Words ? Microcode (16x9bit instructions ?)
$FF0101 ? Byte nLC8951Register (4 LSB)

CDM3-2 BIOS writes low nibble

LC8951
$FF0103 ? Byte nLC8951Register value

CDM3-2 BIOS writes 0x10, CDZ writes 0x00 (start up init)

LC8951
$FF0105 ? Byte ? nActiveTransferArea = byteValue

upload_type_w

?
$FF0108 ? Word ? CDM3-2 BIOS writes $5555 ?
$FF010C ? Word ? CDM3-2 BIOS writes $5555 and reads ?
$FF0111 REG_DISBLSPR Byte ? 1=Disable 0=Enable sprites NEO-GRC/NEO-OFC
$FF0115 REG_DISBLFIX Byte ? 1=Disable 0=Enable fix layer
$FF0119 REG_ENVIDEO Byte ? Video output. 1=Enable 0=Disable
$FF011C REG_CDCONFIG Word
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Def 1 CD Mech
0:TOP/CDZ
1:FRONT		Lid Status
(Opposite on CDZ)		Configuration
jumpers		?
? NEO-CDD board
$FF0121 REG_UPMAPSPR Byte ? NeoSetSpriteSlot(1);

Set upload zone to SPR DRAM

?
$FF0123 REG_UPMAPPCM Set upload zone to PCM DRAM
$FF0127 REG_UPMAPZ80 Set upload zone to Z80 DRAM
$FF0129 REG_UPMAPFIX Set upload zone to FIX DRAM
$FF0141 REG_UPUNMAPSPR Unset SPR DRAM to upload zone
$FF0143 REG_UPUNMAPPCM Unset PCM DRAM to upload zone
$FF0147 REG_UPUNMAPZ80 Unset Z80 DRAM to upload zone
$FF0149 REG_UPUNMAPFIX Unset FIX DRAM to upload zone
$FF0161 ? ? ? NeoCDCommsRead Status FIFO 10 values (4 bits) ?
$FF0163 ? ? ? NeoCDCommsWrite(byteValue) Command FIFO 10 values (4 bits) ?
$FF0165 ? ? ? NeoCDCommsControl(byteValue & 1, byteValue & 2); (clock,send) ?
$FF016D Byte ? MapVectorTable(!(byteValue == 0xFF)); ?
$FF016F REG_DISBLIRQ Byte ? Disable/enable interrupts nTransferWriteEnable = byteValue ?
$FF0181 Byte ? Enable/Disable (Reset) CD assy ?
$FF0183 REG_ENZ80 Byte ? Enable/Disable (Reset) Z80 ?
$FF0188 REG_CDDALEFTL Word See Reading CDDA sound levels No effect NEO-MGA
$FF018A REG_CDDARIGHTL
$FF01A1 ? Byte ? Upload zone 1MiB SPR DRAM bank selection ?
$FF01A3 ? Byte ? Upload zone 512KiB PCM DRAM bank selection ?
$FF01A7 ? Byte ? CDM3-2 BIOS writes ?
$FF01FC ? Word ? CDDA control ? ?
$FF01FE ? Word ? CD DA/data switch ? ?
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