NEO-B1: Difference between revisions

From NeoGeo Development Wiki
Jump to navigation Jump to search
mNo edit summary
m (removed note because pinout is corrected)
 
(11 intermediate revisions by 2 users not shown)
Line 1: Line 1:
[[File:aes_b1.jpg|right|thumb|NEO-B1 chip found in an AES system.]]
{{ChipInfo
|picture=aes_b1.jpg
|pkg=QFP160
|manu=fujitsu
|date=1992 ?
|gates=
|used_on={{PCB|NEO-AES3-4 board|NEO-AES3-4}}...
}}


The NEO-B1 chip is found in second revision cartridge-based systems.
[[File:b1die.jpg|right|thumb|(Damaged) B1 die showing pre-built memory cells.]]


==Graphics==
The NEO-B1 chip is found in second generation cartridge-based systems.


Both FIX graphics from the [[S ROM]] and sprite graphics from the [[C ROM]] are fed to the NEO-B1 for display on screen.  Sprite graphics are sourced from the C ROM multiplexer ([[NEO-ZMC2]], [[PRO-CT0]] or [[NEO-CMC]]), while FIX graphics are sourced directly from the currently enabled FIX ROM.
=Graphics=


The [[palette RAM]] address lines are directly connected to the NEO-B1 for pixel output. The data output of the palette RAM is latched by a pair of 8bit registers, which in turn output to the [[video DAC]].  The NEO-B1 arbitrates access to palette RAM and will pass the 68k address through to the palette RAM when reading/writing/testing the palette RAM. Priority is always given to the 68k which results in harmless display glitches when games access palette RAM while rendering the screen.
Both [[fix layer|fix]] graphics from the [[S ROM]] and serialized sprite graphics from the [[C ROM]]s are fed to NEO-B1 for display on screen via 2 pairs of alternating line buffers. Sprite graphics come from the C ROM multiplexer ({{Chipname|NEO-ZMC2}}, {{Chipname|PRO-CT0}} or {{Chipname|NEO-CMC}}), while fix graphics come directly from the currently enabled fix ROM. Two pixels are written at a time.


==Watchdog==
Sprite rendering is done in the internal [[line buffers]].


The [[watchdog]] is integrated into the NEO-B1. /HALT and /RESET are generated by this chip on power-on and whenever the 68k fails to write the watchdog register in time. It seems to decode the write to watchdog itself instead of using the [[NEO-C1]].
The chip outputs the [[palette RAM]] address to select colors for pixel output. The data output of the palette RAM is latched by a pair of 8bit registers, which in turn feed the [[video DAC]]. The NEO-B1 handles address bus switching between the [[68k]] bus and palette RAM. Priority is always given to the 68k which results in harmless display glitches when games access palette RAM during active display.
 
=Watchdog=
 
The [[watchdog]] is integrated into NEO-B1. {{Sig|HALT|HALT}} and {{Sig|RESET|RESET}} are generated by this chip on power-on and whenever the 68k fails to kick the watchdog in time. The write to {{Reg|REG_DIPSW}} is decoded on the chip instead of using a signal from {{Chipname|NEO-C1}}.


Watchdog can be disabled by bringing pin 94 DOGE to ground (J2 jumper on main board).
Watchdog can be disabled by bringing pin 94 DOGE to ground (J2 jumper on main board).


==Pinout==
=Pinout=
 
{{Pinout|NEO-B1|640}}


(Max size:[[:File:neo-b1_pinout.png]])<br>
[[File:neo-b1_pinout.png|640px]]


OpenOffice Draw file: [[File:neo-b1.odg]]
=Signals=


*A1~A21: [[68k]] address bus
*A1~A21, A22I, A23I: [[68k]] address bus and modified upper lines
*A22I,A23I: 68k A22,A23 passed through [[NEO-E0]]
*FIX0~FIX7: Fix ROM data bus
*FIX0~FIX7: [[Fix layer|FIX]] ROM data bus
*PCK1/PCK2: Latch signals coming from {{Chipname|LSPC2-A2}}
*PCK1/PCK2: Latch signals, shared with [[LSPC2-A2]] (inverted for [[NEO-273]])
*PA0~PA11: Palette RAM address bus
*PA0~PA11: [[Palette RAM]] address bus
*GAD0~GAD3, GBD0~GBD3: Sprite pixel data (2 pixels)
*TDO0~TDO11: NC on the MV1F
*CK1~CK4: Clocks for each buffer
*GAD0~GAD3: Pixel data from [[NEO-ZMC2]]
*WE1~WE4: Write enable for each buffer
*GBD0~GBD3: Pixel data from NEO-ZMC2
*SS1/SS2: Mode select for each pair of buffers
*FLIP: Horizontal flip pixel line
*LD1/LD2: Buffer address reload signals
*WE1~WE4: Write enable for pixel
*TMS0: Buffer order selection
*CK1~CK4: Stepping clocks
*DOGE: [[Watchdog]] enable (internal pullup)
*SS1/SS2: ?
*FLIP: Flip display horizontally ? Always tied to ground
*LD1/LD2: Odd/Even scanline load ? Changes according to sprite list ?
*XMM, XTRE, XTWE: Test mode enable, direct read and write signals
*1H1: 3MHz clock ?
*TDO0~TDO11: Line buffers test data output
*TMS0: Line buffer selection (0/1)
*VCCON: [[Reset]] signal
*DOGE: Watchdog enable (internal pullup)


[[Category:Chips]]
[[Category:Chips]]

Latest revision as of 14:42, 21 May 2020

Package QFP160
Manufacturer
First use 1992 ?
Used on NEO-AES3-4 board...
(Damaged) B1 die showing pre-built memory cells.

The NEO-B1 chip is found in second generation cartridge-based systems.

Graphics

Both fix graphics from the S ROM and serialized sprite graphics from the C ROMs are fed to NEO-B1 for display on screen via 2 pairs of alternating line buffers. Sprite graphics come from the C ROM multiplexer (NEO-ZMC2, PRO-CT0 or NEO-CMC), while fix graphics come directly from the currently enabled fix ROM. Two pixels are written at a time.

Sprite rendering is done in the internal line buffers.

The chip outputs the palette RAM address to select colors for pixel output. The data output of the palette RAM is latched by a pair of 8bit registers, which in turn feed the video DAC. The NEO-B1 handles address bus switching between the 68k bus and palette RAM. Priority is always given to the 68k which results in harmless display glitches when games access palette RAM during active display.

Watchdog

The watchdog is integrated into NEO-B1. HALT and RESET are generated by this chip on power-on and whenever the 68k fails to kick the watchdog in time. The write to REG_DIPSW is decoded on the chip instead of using a signal from NEO-C1.

Watchdog can be disabled by bringing pin 94 DOGE to ground (J2 jumper on main board).

Pinout


Edit this pinout


Signals

  • A1~A21, A22I, A23I: 68k address bus and modified upper lines
  • FIX0~FIX7: Fix ROM data bus
  • PCK1/PCK2: Latch signals coming from LSPC2-A2
  • PA0~PA11: Palette RAM address bus
  • GAD0~GAD3, GBD0~GBD3: Sprite pixel data (2 pixels)
  • CK1~CK4: Clocks for each buffer
  • WE1~WE4: Write enable for each buffer
  • SS1/SS2: Mode select for each pair of buffers
  • LD1/LD2: Buffer address reload signals
  • TMS0: Buffer order selection
  • DOGE: Watchdog enable (internal pullup)
  • FLIP: Flip display horizontally ? Always tied to ground
  • XMM, XTRE, XTWE: Test mode enable, direct read and write signals
  • TDO0~TDO11: Line buffers test data output
  • VCCON: Reset signal