NEO-CMC: Difference between revisions

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[[File:brd_cmcnoref.jpg|thumb|"CMC50"]]
[[File:brd_cmcnoref.jpg|thumb|"CMC50"]]


Late SNK ASIC used as protection, banking and latching chip on [[CHAFIO]] [[CHA board]]s.
Late SNK custom chip used for protection, bankswitching and latching on [[CHAFIO]] [[CHA board]]s.


Scrambling/decryption infos can be found in [[http://mamedev.org/source/src/mame/machine/neocrypt.c.html MAME:neocrypt.c]]
Descrambling/decryption infos can be found in [[https://github.com/mamedev/mame/src/devices/bus/neogeo/prot_cmc.cpp  MAME:prot_cmc.c]]


==Versions==
==Versions==
This chip is a TC190G series Toshiba ASIC developed between 1990 and 1994.
This chip is a TC190G series Toshiba ASIC developed between 1990 and 1994.
The evolution of this series can be found at [[http://www.toshiba-components.com/ASIC/Technology.html Toshiba Technology RoadMap]].


The datasheet apparently can't be found anymore for any of the known types:
The datasheet apparently can't be found anymore for any of the known types:
Line 17: Line 16:


SNK merged the following designs into this chip:
SNK merged the following designs into this chip:
*NEO-ZMC
*{{Chipname|NEO-ZMC}}
*NEO-273
*{{Chipname|NEO-273}}
*New scrambling system that interlaces M1 + (C* + S1) to decrypt all the graphics ROMs data in real time.
*New scrambling system that interlaces M1 + (C* + S1) to decrypt all the graphics ROMs data in real time.



Revision as of 04:37, 16 August 2016

"CMC42" chip on a MVS cartridge. Picture courtesy of [MVS-Scans].
File:Brd cmcnoref.jpg
"CMC50"

Late SNK custom chip used for protection, bankswitching and latching on CHAFIO CHA boards.

Descrambling/decryption infos can be found in [MAME:prot_cmc.c]

Versions

This chip is a TC190G series Toshiba ASIC developed between 1990 and 1994.

The datasheet apparently can't be found anymore for any of the known types:

  • TC190G06CF7008
  • TC190G06CF7042
  • TC190G06CF7050

(probably others...)

SNK merged the following designs into this chip:

  • NEO-ZMC
  • NEO-273
  • New scrambling system that interlaces M1 + (C* + S1) to decrypt all the graphics ROMs data in real time.

The first released NEO-MVS CHAFIO PCBs came out with the 042 version of NEO-CMC, on the following cartridges:

On this version only the S1 and C ROMs are encrypted and M1 remains unencrypted. Almost one year later, SNK decided to add one more layer, this time also encrypting M1. This new NEO-CMC chip had the 050 reference and was found in the following cartridges:

Until today, nobody has released a cloned chip on the underground market.

Fix handling

See fix bankswitching.

Encryption

Todo.

Pinout

OpenOffice Draw file: File:Neocmc 7050 7042.odg

Signals:

  • C_e_D[0..15]: C odd data bus
  • C_o_D[0..15]: C even data bus
  • CX A[0..21]: C1~8 address bus
  • Pins 87,88 contains a RC circuit clock driver like in a 8085 with X1 and X2 pinouts
  • Pins 89 and 92 are shorted.