NEO-DCR-T: Difference between revisions
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=Pinout= | =Pinout= | ||
[[File:Neo-dcr_pinout.png]] | [[File:Neo-dcr_pinout.png]] | ||
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* DIPRD0 and DIPRD1 go to a {{Chipname|NEO-BUF}} chip to gate the remaining DIP switch bits and RTC inputs | * DIPRD0 and DIPRD1 go to a {{Chipname|NEO-BUF}} chip to gate the remaining DIP switch bits and RTC inputs | ||
* Pin 85 might be an input | * Pin 85 might be an input | ||
* No [[memory card]] control signals ? | * No [[memory card]] control signals ? | ||
[[Category:Chips]] | [[Category:Chips]] | ||
Revision as of 04:19, 28 February 2017
| |
| Package | QFP100R |
| Manufacturer | 
|
| First use | 1995 ? |
| Used on | MV1B ... |
Chip found on late MVS boards and next to the DIP switches on ROM-Only boards.
- Address decoding
- Coin I/O
- System register
- Wait state generator
Pinout
Draft pinout: File:Neo-dcr.odg
- DIPRD0 and DIPRD1 go to a NEO-BUF chip to gate the remaining DIP switch bits and RTC inputs
- Pin 85 might be an input
- No memory card control signals ?