Difference between revisions of "NEO-E0"

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m (68k vector table swapping)
(Added chip position on board)
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==MV2F @ E1 pinout (to be confirmed)==

Revision as of 16:08, 6 January 2018

Aes e0.jpg
Package QFP64R
Manufacturer Logo fujitsu.jpg
First use 1991 ?
Used on NEO-AES3-3 ...

68k vector table swapping

The 68k vector table is swapped with the system ROM one by using REG_SWPBIOS or REG_SWPROM.

A22Z~A23Z are used to make the address appear to address decoding chips as a system ROM access instead of a P ROM access.

Address Maps to
VEC = 0 VEC = 1
$000000~$0000FF $C00000~$C000FF $000000~$0000FF
$000100~$BFFFFF $000100~$BFFFFF
$C00000~$C000FF $000000~$0000FF $C00000~$C000FF
$C00100~$FFFFFF $C00100~$FFFFFF

User:Kyuusaku: {A23Z,A22Z} = A[23:22] ^ 2{~|{A[21:7],^A[23:22],VEC}}


On the AES, the AND gate is used to get /SROMOE from /SROMOEL AND /SROMOEU.

MV2B @ H7 pinout

55 = sPCK1B 56 = sPCK2B

MV2B @ G2 pinout

Neo-e0 G2 pinout.png

OpenOffice Draw file: File:Neo-e0 mv2b G2.odg

MV2B @ F7 pinout

Neo-e0 F7 pinout.png

OpenOffice Draw file: File:Neo-e0 mv2b F7.odg

Acts just as a buffer.

  • s*: signals to both slots

MV2F @ E1 pinout (to be confirmed)

Neo-e0 pinout.png

OpenOffice Draw file: File:Neo-e0.odg

  • A1~A23: 68k address bus
  • Y0~Y23: memory card address bus
  • BNK0~BNK2: comes from NEO-D0, memory card banking
  • VEC: System ROM vector table swapping enable
  • ANI0, ANI1, AND0: AND gate used to generate ROMOE from ROMOEU and ROMOEL