NEO-E0: Difference between revisions

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The chip also ANDs the pair of 8bit output enable signals from the [[NEO-C1]] since there is only a single 16bit ROM used for the BIOS.
The chip also ANDs the pair of 8bit output enable signals from the [[NEO-C1]] since there is only a single 16bit ROM used for the BIOS.
==MV2B @ G2 pinout==
{|
|
[[File:Neo-e0_G2_pinout.png|512px]]
OpenOffice Draw file: [[File:Neo-e0_mv2b_G2.odg]]
|
*A1~A23: [[68k]] address bus
*MCA0~MCA23: [[memory card]] address bus
*BNK0~BNK2: memory card banking from [[NEO-D0]]
*VEC: [[BIOS]] vector table swapping enable
|}
==MV2B @ F7 pinout==
{|
|
[[File:Neo-e0_F7_pinout.png|512px]]
OpenOffice Draw file: [[File:Neo-e0_mv2b_F7.odg]]
|
Acts just as a buffer.
*s*: signals to both slots
|}


=Pinout=
=Pinout=


[[File:Neo-e0_pinout.png]]
{|
|
[[File:Neo-e0_pinout.png|512px]]


OpenOffice Draw file: [[File:neo-e0.odg]]
OpenOffice Draw file: [[File:neo-e0.odg]]
 
|
*A1~A23: 68k address bus
*A1~A23: 68k address bus
*Y0~Y23: memory card address bus
*Y0~Y23: memory card address bus
*BNK0~BNK2: comes from [[NEO-D0]], ?
*BNK0~BNK2: comes from [[NEO-D0]], [[memory card]] banking
*VEC: BIOS vector table swapping enable
*VEC: BIOS vector table swapping enable
*ANI0, ANI1, AND0: AND gate used to generate ROMOE from ROMOEU and ROMOEL
*ANI0, ANI1, AND0: AND gate used to generate ROMOE from ROMOEU and ROMOEL
|}


[[Category:Chips]]
[[Category:Chips]]

Revision as of 04:52, 14 August 2012

NEO-E0 chip found on a AES board.

Also found on MVS boards, even those without memory card slots.

BIOS vector table swapping

When 68k A8~A23 = 0 and the BIOS's vector table is chosen (by using the "system" memory mapped registers), A22I~A23I outputs are set to 1. This makes the address appear to address decoding chips as a BIOS access instead of a P ROM access.

Memory card address latch

On AES systems, BNK0~BNK2 are tied low. This makes the chip act just like a buffer ? What are BNK0~BNK2 used for ?


The chip also ANDs the pair of 8bit output enable signals from the NEO-C1 since there is only a single 16bit ROM used for the BIOS.

MV2B @ G2 pinout

OpenOffice Draw file: File:Neo-e0 mv2b G2.odg

  • A1~A23: 68k address bus
  • MCA0~MCA23: memory card address bus
  • BNK0~BNK2: memory card banking from NEO-D0
  • VEC: BIOS vector table swapping enable

MV2B @ F7 pinout

OpenOffice Draw file: File:Neo-e0 mv2b F7.odg

Acts just as a buffer.

  • s*: signals to both slots

Pinout

OpenOffice Draw file: File:Neo-e0.odg

  • A1~A23: 68k address bus
  • Y0~Y23: memory card address bus
  • BNK0~BNK2: comes from NEO-D0, memory card banking
  • VEC: BIOS vector table swapping enable
  • ANI0, ANI1, AND0: AND gate used to generate ROMOE from ROMOEU and ROMOEL