NEO-E0: Difference between revisions

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[[File:aes_e0.jpg|right|thumb|NEO-E0 chip found on a AES board.]]
{{ChipInfo
|picture=aes_e0.jpg
|pkg=QFP64R
|manu=fujitsu
|date=1991 ?
|gates=
|used_on={{PCB|NEO-AES3-3}} ...
}}


Also found on MVS boards, even those without memory card slots.
=68k vector table swapping=
The 68k vector table is swapped with the [[system ROM]] one by using {{Reg|REG_SWPBIOS}} or {{Reg|REG_SWPROM}}.


==BIOS vector table swapping==
A22Z~A23Z are used to make the address appear to address decoding chips as a system ROM access instead of a [[P ROM]] access.
When 68k A8~A23 = 0 and the [[BIOSes|BIOS]'s vector table is chosen (by using [[memory mapped registers#System registers|"system" memory mapped registers]]), A22I~A23I outputs are set to 1.  This makes the address appear to address decoding chips as a BIOS access instead of a [[P ROM]] access.


==Memory card address latch==
{|class="wikitable"
On AES systems, BNK0~BNK2 are tied low. This makes the chip act just like a buffer ?
!rowspan=2|Address||colspan=2|Maps to
What are BNK0~BNK2 used for ?
|-
!VEC = 0||VEC = 1
|-
|$000000~$00007F||$C00000~$C0007F||$000000~$00007F
|-
|$000080~$BFFFFF||colspan=2|$000080~$BFFFFF
|-
|$C00000~$C0007F||$000000~$00007F||$C00000~$C0007F
|-
|$C00080~$FFFFFF||colspan=2|$C00080~$FFFFFF
|}


[[User:Kyuusaku]]: {A23Z,A22Z} = A[23:22] ^ 2{~|{A[21:7],^A[23:22],VEC}}


The chip also ANDs the pair of 8bit output enable signals from the [[NEO-C1]] since there is only a single 16bit ROM used for the BIOS.
=Pinouts=


=Pinout=
On the AES, the AND gate is used to get /SROMOE from /SROMOEL AND /SROMOEU.


[[File:Neo-e0_pinout.png]]
==MV2B @ H7 pinout==


55 = sPCK1B
56 = sPCK2B
==MV2B @ G2 pinout==
{|
|
[[File:Neo-e0_G2_pinout.png|512px]]
OpenOffice Draw file: [[File:Neo-e0_mv2b_G2.odg]]
|
*A1~A23: [[68k]] address bus
*MCA0~MCA23: [[memory card]] address bus
*BNK0~BNK2: memory card banking from [[NEO-D0]]
*VEC: [[System ROM]] vector table swapping enable
|}
==MV2B @ F7 pinout==
{|
|
[[File:Neo-e0_F7_pinout.png|512px]]
OpenOffice Draw file: [[File:Neo-e0_mv2b_F7.odg]]
|
Acts just as a buffer.
*s*: signals to both slots
|}
==MV2F @ E1 pinout (to be confirmed)==
{|
|
[[File:Neo-e0_pinout.png|512px]]
OpenOffice Draw file: [[File:neo-e0.odg]]
|
*A1~A23: 68k address bus
*A1~A23: 68k address bus
*Y0~Y23: memory card address bus
*Y0~Y23: memory card address bus
*BNK0~BNK2: comes from [[NEO-D0]], ?
*BNK0~BNK2: comes from [[NEO-D0]], [[memory card]] banking
*VEC: BIOS vector table swapping enable
*VEC: System ROM vector table swapping enable
*ANI0, ANI1, AND0: AND gate used to generate ROMOE from ROMOEU and ROMOEL
*ANI0, ANI1, AND0: AND gate used to generate ROMOE from ROMOEU and ROMOEL
|}


[[Category:Chips]]
[[Category:Chips]]

Revision as of 03:42, 7 October 2018

Package QFP64R
Manufacturer
First use 1991 ?
Used on NEO-AES3-3 ...

68k vector table swapping

The 68k vector table is swapped with the system ROM one by using REG_SWPBIOS or REG_SWPROM.

A22Z~A23Z are used to make the address appear to address decoding chips as a system ROM access instead of a P ROM access.

Address Maps to
VEC = 0 VEC = 1
$000000~$00007F $C00000~$C0007F $000000~$00007F
$000080~$BFFFFF $000080~$BFFFFF
$C00000~$C0007F $000000~$00007F $C00000~$C0007F
$C00080~$FFFFFF $C00080~$FFFFFF

User:Kyuusaku: {A23Z,A22Z} = A[23:22] ^ 2{~|{A[21:7],^A[23:22],VEC}}

Pinouts

On the AES, the AND gate is used to get /SROMOE from /SROMOEL AND /SROMOEU.

MV2B @ H7 pinout

55 = sPCK1B 56 = sPCK2B

MV2B @ G2 pinout

OpenOffice Draw file: File:Neo-e0 mv2b G2.odg

MV2B @ F7 pinout

OpenOffice Draw file: File:Neo-e0 mv2b F7.odg

Acts just as a buffer.

  • s*: signals to both slots

MV2F @ E1 pinout (to be confirmed)

OpenOffice Draw file: File:Neo-e0.odg

  • A1~A23: 68k address bus
  • Y0~Y23: memory card address bus
  • BNK0~BNK2: comes from NEO-D0, memory card banking
  • VEC: System ROM vector table swapping enable
  • ANI0, ANI1, AND0: AND gate used to generate ROMOE from ROMOEU and ROMOEL