NEO-E0: Difference between revisions

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[[File:aes_e0.jpg|right|thumb|NEO-E0 chip found on a AES board.]]
{{ChipInfo
|picture=aes_e0.jpg
|pkg=QFP64R
|manu=fujitsu
|date=1991 ?
|gates=
|used_on={{PCB|NEO-AES3-3}} ...
}}


Also found in MVS systems. Probably grouped glue logic, as early AES boards had plenty of 74HC chips instead.
Just a 24-bit buffer and logic for [[68k vector table]] swapping.


BIOS vector table swapping is handled by this chip.  When 68k A8~A23 = 0 and the appropriate 74HC259 input (determined by [[memory mapped registers]]) is active, A22I~A23I outputs are set to 1.  This makes the address appear to address decoding chips as a [[BIOSes|BIOS]] access instead of a [[P ROM]] access.
=68k vector table swapping=
The 68k vector table is selected between the one from the game, or the on from the [[system ROM]] by writing to {{Reg|REG_SWPROM}} or {{Reg|REG_SWPBIOS}}.


It also ANDs the pair of 8bit output enable signals from the [[NEO-C1]] since there is only a single 16bit ROM used for the BIOS.
A22Z and A23Z are used in place of A22 and A23 to make the address appear to address decoding chips as a system ROM access instead of a [[P ROM]] access.


What is Y0~Y23 for? attached to memory card in AES / multislots?
The {{Sig|VEC|VEC}} signal comes from the 74H259 system latch.


{|class="wikitable"
!rowspan=2|Address||colspan=2|Maps to
|-
!VEC = 0||VEC = 1
|-
|$000000~$00007F||$C00000~$C0007F||$000000~$00007F
|-
|$000080~$BFFFFF||colspan=2|$000080~$BFFFFF
|-
|$C00000~$C0007F||$000000~$00007F||$C00000~$C0007F
|-
|$C00080~$FFFFFF||colspan=2|$C00080~$FFFFFF
|}
Verilog from [[User:Kyuusaku]]:
<pre>{A23Z,A22Z} = A[23:22] ^ 2{~|{A[21:7],^A[23:22],VEC}}</pre>
=Pinouts=
==Input to output map=
* 64 -> 5
* 1 -> 6
* 2 -> 7
* 3 -> 8
* 4 -> 9
* 15 -> 11
* 16 -> 12
* 17 -> 13
* 18 -> 14
* 19 -> 22
* 20 -> 23
* 21 -> 24
* 31 -> 27
* 32 -> 28
* 33 -> 29
* 34 -> 30
* 36 -> 39
* 37 -> 40
* 38 -> 41
* 48 -> 43
* 49 -> 44
* 50 -> 45
* 51 -> 46
* 52 -> 47
* 53 -> 55 if VEC is high
* 54 -> 56 if VEC is high
==Console==
On the AES, the AND gate is used to make /SROMOE from (/SROMOEL AND /SROMOEU).
==MV2B @ H7 pinout==
* 55 = sPCK1B
* 56 = sPCK2B
==MV2B @ G2 pinout==
{|
|
[[File:Neo-e0_G2_pinout.png|512px]]
OpenOffice Draw file: [[File:Neo-e0_mv2b_G2.odg]]
|
*A1~A23: [[68k]] address bus
*MCA0~MCA23: [[memory card]] address bus
*BNK0~BNK2: memory card banking from [[NEO-D0]]
*VEC: [[System ROM]] vector table swapping enable
|}
==MV2B @ F7 pinout==
{|
|
[[File:Neo-e0_F7_pinout.png|512px]]
OpenOffice Draw file: [[File:Neo-e0_mv2b_F7.odg]]
|
Acts just as a buffer.
*s*: signals to both slots
|}
==MV2F @ E1 pinout (to be confirmed)==
{|
|
[[File:Neo-e0_pinout.png|512px]]
OpenOffice Draw file: [[File:neo-e0.odg]]
|
*A1~A23: 68k address bus
*Y0~Y23: memory card address bus
*BNK0~BNK2: comes from [[NEO-D0]], [[memory card]] bank
*VEC: System ROM vector table swapping
*ANI0, ANI1, AND0: AND gate used to generate ROMOE from (ROMOEU and ROMOEL)
|}


[[Category:Chips]]
[[Category:Chips]]

Revision as of 14:57, 7 June 2019

Package QFP64R
Manufacturer
First use 1991 ?
Used on NEO-AES3-3 ...

Just a 24-bit buffer and logic for 68k vector table swapping.

68k vector table swapping

The 68k vector table is selected between the one from the game, or the on from the system ROM by writing to REG_SWPROM or REG_SWPBIOS.

A22Z and A23Z are used in place of A22 and A23 to make the address appear to address decoding chips as a system ROM access instead of a P ROM access.

The VEC signal comes from the 74H259 system latch.

Address Maps to
VEC = 0 VEC = 1
$000000~$00007F $C00000~$C0007F $000000~$00007F
$000080~$BFFFFF $000080~$BFFFFF
$C00000~$C0007F $000000~$00007F $C00000~$C0007F
$C00080~$FFFFFF $C00080~$FFFFFF

Verilog from User:Kyuusaku:

{A23Z,A22Z} = A[23:22] ^ 2{~|{A[21:7],^A[23:22],VEC}}

Pinouts

=Input to output map

  • 64 -> 5
  • 1 -> 6
  • 2 -> 7
  • 3 -> 8
  • 4 -> 9
  • 15 -> 11
  • 16 -> 12
  • 17 -> 13
  • 18 -> 14
  • 19 -> 22
  • 20 -> 23
  • 21 -> 24
  • 31 -> 27
  • 32 -> 28
  • 33 -> 29
  • 34 -> 30
  • 36 -> 39
  • 37 -> 40
  • 38 -> 41
  • 48 -> 43
  • 49 -> 44
  • 50 -> 45
  • 51 -> 46
  • 52 -> 47
  • 53 -> 55 if VEC is high
  • 54 -> 56 if VEC is high

Console

On the AES, the AND gate is used to make /SROMOE from (/SROMOEL AND /SROMOEU).

MV2B @ H7 pinout

  • 55 = sPCK1B
  • 56 = sPCK2B

MV2B @ G2 pinout

OpenOffice Draw file: File:Neo-e0 mv2b G2.odg

MV2B @ F7 pinout

OpenOffice Draw file: File:Neo-e0 mv2b F7.odg

Acts just as a buffer.

  • s*: signals to both slots

MV2F @ E1 pinout (to be confirmed)

OpenOffice Draw file: File:Neo-e0.odg

  • A1~A23: 68k address bus
  • Y0~Y23: memory card address bus
  • BNK0~BNK2: comes from NEO-D0, memory card bank
  • VEC: System ROM vector table swapping
  • ANI0, ANI1, AND0: AND gate used to generate ROMOE from (ROMOEU and ROMOEL)