NEO-E0: Difference between revisions

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=[[System ROM]] vector table swapping=
Just a 24-bit buffer and logic for [[68k vector table]] swapping.
When 68k A8~A23 = 0 and the [[System ROM]]'s vector table is chosen (by using {{Reg|REG_SWPBIOS}} or {{Reg|REG_SWPROM}}), A22I~A23I outputs are set to 1.  This makes the address appear to address decoding chips as a system ROM access instead of a [[P ROM]] access.


[[User:Kyuusaku]]: {A23Z,A22Z} = A[23:22] ^ 2{~|{A[21:7],^A[23:22],VEC}}
=68k vector table swapping=
The 68k vector table is selected between the one from the game, or the on from the [[system ROM]] by writing to {{Reg|REG_SWPROM}} or {{Reg|REG_SWPBIOS}}.


On the AES, the AND gate is used to get /SROMOE from /SROMOEL AND /SROMOEU.
A22Z and A23Z are used in place of A22 and A23 to make the address appear to address decoding chips as a system ROM access instead of a [[P ROM]] access.
 
The {{Sig|VEC|VEC}} signal comes from the 74H259 system latch.
 
{|class="wikitable"
!rowspan=2|Address||colspan=2|Maps to
|-
!VEC = 0||VEC = 1
|-
|$000000~$00007F||$C00000~$C0007F||$000000~$00007F
|-
|$000080~$BFFFFF||colspan=2|$000080~$BFFFFF
|-
|$C00000~$C0007F||$000000~$00007F||$C00000~$C0007F
|-
|$C00080~$FFFFFF||colspan=2|$C00080~$FFFFFF
|}
 
Verilog from [[User:Kyuusaku]]:
<pre>{A23Z,A22Z} = A[23:22] ^ 2{~|{A[21:7],^A[23:22],VEC}}</pre>


=Pinouts=
=Pinouts=


==MV2B @ H7 pinout==
==Input to output map=
 
* 64 -> 5
* 1 -> 6
* 2 -> 7
* 3 -> 8
* 4 -> 9
* 15 -> 11
* 16 -> 12
* 17 -> 13
* 18 -> 14
* 19 -> 22
* 20 -> 23
* 21 -> 24
* 31 -> 27
* 32 -> 28
* 33 -> 29
* 34 -> 30
* 36 -> 39
* 37 -> 40
* 38 -> 41
* 48 -> 43
* 49 -> 44
* 50 -> 45
* 51 -> 46
* 52 -> 47
* 53 -> 55 if VEC is high
* 54 -> 56 if VEC is high
 
==Console==
 
On the AES, the AND gate is used to make /SROMOE from (/SROMOEL AND /SROMOEU).
 
==MV2B & MV2-01 @ H7 pinout==


55 = sPCK1B
* 55 = sPCK1B
56 = sPCK2B
* 56 = sPCK2B
[[P_bus]] buffer


==MV2B @ G2 pinout==
==MV2B @ G2 pinout==
Line 49: Line 102:
|}
|}


=Pinout=
==MV2F @ E1 pinout (to be confirmed)==


{|
{|
Line 59: Line 112:
*A1~A23: 68k address bus
*A1~A23: 68k address bus
*Y0~Y23: memory card address bus
*Y0~Y23: memory card address bus
*BNK0~BNK2: comes from [[NEO-D0]], [[memory card]] banking
*BNK0~BNK2: comes from [[NEO-D0]], [[memory card]] bank
*VEC: System ROM vector table swapping enable
*VEC: System ROM vector table swapping
*ANI0, ANI1, AND0: AND gate used to generate ROMOE from ROMOEU and ROMOEL
*ANI0, ANI1, AND0: AND gate used to generate ROMOE from (ROMOEU and ROMOEL)
|}
|}


[[Category:Chips]]
[[Category:Chips]]

Revision as of 21:17, 3 July 2019

Package QFP64R
Manufacturer
First use 1991 ?
Used on NEO-AES3-3 ...

Just a 24-bit buffer and logic for 68k vector table swapping.

68k vector table swapping

The 68k vector table is selected between the one from the game, or the on from the system ROM by writing to REG_SWPROM or REG_SWPBIOS.

A22Z and A23Z are used in place of A22 and A23 to make the address appear to address decoding chips as a system ROM access instead of a P ROM access.

The VEC signal comes from the 74H259 system latch.

Address Maps to
VEC = 0 VEC = 1
$000000~$00007F $C00000~$C0007F $000000~$00007F
$000080~$BFFFFF $000080~$BFFFFF
$C00000~$C0007F $000000~$00007F $C00000~$C0007F
$C00080~$FFFFFF $C00080~$FFFFFF

Verilog from User:Kyuusaku:

{A23Z,A22Z} = A[23:22] ^ 2{~|{A[21:7],^A[23:22],VEC}}

Pinouts

=Input to output map

  • 64 -> 5
  • 1 -> 6
  • 2 -> 7
  • 3 -> 8
  • 4 -> 9
  • 15 -> 11
  • 16 -> 12
  • 17 -> 13
  • 18 -> 14
  • 19 -> 22
  • 20 -> 23
  • 21 -> 24
  • 31 -> 27
  • 32 -> 28
  • 33 -> 29
  • 34 -> 30
  • 36 -> 39
  • 37 -> 40
  • 38 -> 41
  • 48 -> 43
  • 49 -> 44
  • 50 -> 45
  • 51 -> 46
  • 52 -> 47
  • 53 -> 55 if VEC is high
  • 54 -> 56 if VEC is high

Console

On the AES, the AND gate is used to make /SROMOE from (/SROMOEL AND /SROMOEU).

MV2B & MV2-01 @ H7 pinout

  • 55 = sPCK1B
  • 56 = sPCK2B

P_bus buffer

MV2B @ G2 pinout

OpenOffice Draw file: File:Neo-e0 mv2b G2.odg

MV2B @ F7 pinout

OpenOffice Draw file: File:Neo-e0 mv2b F7.odg

Acts just as a buffer.

  • s*: signals to both slots

MV2F @ E1 pinout (to be confirmed)

OpenOffice Draw file: File:Neo-e0.odg

  • A1~A23: 68k address bus
  • Y0~Y23: memory card address bus
  • BNK0~BNK2: comes from NEO-D0, memory card bank
  • VEC: System ROM vector table swapping
  • ANI0, ANI1, AND0: AND gate used to generate ROMOE from (ROMOEU and ROMOEL)