Difference between revisions of "NEO-G0"

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m (direction)
m (Internal logic)
 
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[[File:Aes_g0.jpg|right|thumb|NEO-G0 chip found on an AES board.]]
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{{ChipInfo
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|picture=Aes_g0.jpg
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|pkg=QFP64R
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|manu=fujitsu
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|date=1992 ?
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|gates=
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|used_on={{PCB|MV2B}} ...
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}}
  
Gates the [[68k]] data bus to the memory card slot and palette RAM. Only found in AES systems ?
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Quadruple 245 with additional OR and AND gates. Predecessor of {{Chipname|NEO-BUF}}.
  
PROG B22 (AES cart ROMOE ?) = ROMOEU AND ROMOEL like in [[NEO-E0]] ?
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=Internal logic=
  
PALWE = PAL OR R/W.
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Schematic is wrong: A and B sides are flipped !
  
=Pinout=
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{|
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|
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[[File:neo-g0_internal.png]]
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|
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*Pin 51 is enable for MCD0~MCD15
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*Pin 39 is enable for PALD0~PALD15
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*Pin 40 is direction select for D0~D7
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*Pin 52 is direction select for D8~D15
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|}
  
[[File:Neo-g0_pinout.png]]
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=Pinouts=
  
OpenOffice Draw file: [[File:neo-g0.odg]]
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==AES==
  
*D0~D15: 68k data bus
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Palette RAM and memory card access. Palette RAM /WE and P1 ROM /OE generation.
*PALD0~PALD7: lower byte of palette data
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*PAUD0~PAUD7: upper byte of palette data
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{|
*MCD0~MCD15: memory card data bus
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|
*(51) is "enable MCD0~MCD15" pin
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{{Pinout|NEO-G0_aes|512}}
*(39) is "enable PALD0~PALD15" pin (confirmed on MV-2F chip used as ADPCM-A multiplexer):
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|
**NEO-F0 -> NEO-G0 @ K9:
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*D0~D15: [[68k]] data bus
**SLOT0(48) -> SEL?(51)
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*PALD0~PALD7: Lower [[palette RAM]] data bus
**SLOT1(49) -> "PAL"(39)
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*PAUD0~PAUD7: Upper palette RAM data bus
*(40) is a direction select for "D0~D7" (negated /ROE from 2610 sent here and RAD0~RAD7 connected to "D0~D7" of G0
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*MCD0~MCD15: [[Memory card]] data bus
*(52) is a direction select for "D8~D15" (negated /POE sent here, PAD0~PAD7 connected to "D8~D15"
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*PAL: Palette RAM address decode from [[NEO-C1]]
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*R/W: R/W from 68k
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*PALWE: Palette RAM /WE, output made from PAL OR R/W
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*ROMOEL, ROMOEU: from PRO-C0
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*ROMOE: Cartridge [[P ROM]] /OE, output made from ROMOEU AND ROMOEL
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|}
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<div style="clear: left;"></div>
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==MV2B==
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<gallery>
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File:Neo-g0_J4_pinout.png|J4: 68k data bus access for both slots. DS0,DS1: Slot 68k data enables from [[NEO-I0]]. OpenOffice Draw file: [[File:neo-g0_mv2b_J4.odg]]
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File:Neo-g0_J12_pinout.png|J12: ADPCM buses access for both slots. 10 AS04: negated /ROE from YM2610, 12 AS04: negated /POE from YM2610. SLOT0, SLOT1: enables from [[NEO-F0]]. OpenOffice Draw file: [[File:neo-g0_mv2b_J12.odg]]
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File:Neo-g0_C7_pinout.png|B7: Palette RAM and memory card access. Palette RAM /WE and System ROM /OE generation. 28 C0 (PAL ?):Palette RAM address decode from [[PRO-C0]]. OpenOffice Draw file: [[File:neo-g0_mv2b_C7.odg]]
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</gallery>
  
 
[[Category:Chips]]
 
[[Category:Chips]]

Latest revision as of 19:35, 2 May 2020

Aes g0.jpg
Package QFP64R
Manufacturer Logo fujitsu.jpg
First use 1992 ?
Used on MV2B ...

Quadruple 245 with additional OR and AND gates. Predecessor of NEO-BUF.

Internal logic

Schematic is wrong: A and B sides are flipped !

Neo-g0 internal.png

  • Pin 51 is enable for MCD0~MCD15
  • Pin 39 is enable for PALD0~PALD15
  • Pin 40 is direction select for D0~D7
  • Pin 52 is direction select for D8~D15

Pinouts

AES

Palette RAM and memory card access. Palette RAM /WE and P1 ROM /OE generation.

NEO-G0 aes pinout.png
Edit this pinout

  • D0~D15: 68k data bus
  • PALD0~PALD7: Lower palette RAM data bus
  • PAUD0~PAUD7: Upper palette RAM data bus
  • MCD0~MCD15: Memory card data bus
  • PAL: Palette RAM address decode from NEO-C1
  • R/W: R/W from 68k
  • PALWE: Palette RAM /WE, output made from PAL OR R/W
  • ROMOEL, ROMOEU: from PRO-C0
  • ROMOE: Cartridge P ROM /OE, output made from ROMOEU AND ROMOEL

MV2B