Difference between revisions of "NEO-G0"

From NeoGeo Development Wiki
Jump to: navigation, search
m
m (Internal logic)
 
(7 intermediate revisions by 3 users not shown)
Line 1: Line 1:
[[File:Aes_g0.jpg|right|thumb]]
+
{{ChipInfo
 +
|picture=Aes_g0.jpg
 +
|pkg=QFP64R
 +
|manu=fujitsu
 +
|date=1992 ?
 +
|gates=
 +
|used_on={{PCB|MV2B}} ...
 +
}}
  
Quadruple 245 with OR and AND gates. Predecessor of [[NEO-BUF]].
+
Quadruple 245 with additional OR and AND gates. Predecessor of {{Chipname|NEO-BUF}}.
  
 
=Internal logic=
 
=Internal logic=
 +
 +
Schematic is wrong: A and B sides are flipped !
  
 
{|
 
{|
Line 15: Line 24:
 
|}
 
|}
  
=AES pinout=
+
=Pinouts=
 +
 
 +
==AES==
  
 
Palette RAM and memory card access. Palette RAM /WE and P1 ROM /OE generation.
 
Palette RAM and memory card access. Palette RAM /WE and P1 ROM /OE generation.
Line 21: Line 32:
 
{|
 
{|
 
|
 
|
[[File:Neo-g0_aes_pinout.png|512px|]]
+
{{Pinout|NEO-G0_aes|512}}
 
 
OpenOffice Draw file: [[File:neo-g0_aes.odg]]
 
 
|
 
|
 
*D0~D15: [[68k]] data bus
 
*D0~D15: [[68k]] data bus
Line 40: Line 49:
 
<div style="clear: left;"></div>
 
<div style="clear: left;"></div>
  
=MV2B @ J4 pinout=
+
==MV2B==
 
 
68k data bus access for both slots.
 
 
 
{|
 
|
 
[[File:Neo-g0_J4_pinout.png|512px]]
 
 
 
OpenOffice Draw file: [[File:neo-g0_mv2b_J4.odg]]
 
|
 
*D0~D15: [[68k]] data bus
 
*1D0~1D15: Slot 1 68k data bus
 
*2D0~2D15: Slot 2 68k data bus
 
 
 
*DS0,DS1: Slot 68k data enables from [[NEO-I0]]
 
*R/W: R/W from 68k
 
|}
 
 
 
<div style="clear: left;"></div>
 
 
 
 
 
=MV2B @ J12 pinout=
 
 
 
ADPCM buses access for both slots.
 
 
 
{|
 
|
 
[[File:Neo-g0_J12_pinout.png|512px]]
 
 
 
OpenOffice Draw file: [[File:neo-g0_mv2b_J12.odg]]
 
|
 
*SDRAD0~SDRAD7: ADPCM-A data bus from [[YM2610]]
 
*1SDRAD0~1SDRAD7: ADPCM-A data bus for slot 1
 
*2SDRAD0~2SDRAD7: ADPCM-A data bus for slot 2
 
  
*SDPAD0~SDPAD7: ADPCM-B data bus from YM2610
+
<gallery>
*1SDPAD0~1SDPAD7: ADPCM-B data bus for slot 1
+
File:Neo-g0_J4_pinout.png|J4: 68k data bus access for both slots. DS0,DS1: Slot 68k data enables from [[NEO-I0]]. OpenOffice Draw file: [[File:neo-g0_mv2b_J4.odg]]
*2SDPAD0~2SDPAD7: ADPCM-B data bus for slot 2
+
File:Neo-g0_J12_pinout.png|J12: ADPCM buses access for both slots. 10 AS04: negated /ROE from YM2610, 12 AS04: negated /POE from YM2610. SLOT0, SLOT1: enables from [[NEO-F0]]. OpenOffice Draw file: [[File:neo-g0_mv2b_J12.odg]]
 
+
File:Neo-g0_C7_pinout.png|B7: Palette RAM and memory card access. Palette RAM /WE and System ROM /OE generation. 28 C0 (PAL ?):Palette RAM address decode from [[PRO-C0]]. OpenOffice Draw file: [[File:neo-g0_mv2b_C7.odg]]
*10 AS04: negated /ROE from YM2610
+
</gallery>
*12 AS04: negated /POE from YM2610
 
*SLOT0, SLOT1: enables from [[NEO-F0]]
 
 
 
|}
 
 
 
<div style="clear: left;"></div>
 
 
 
=MV2B @ C7 pinout=
 
 
 
Palette RAM and memory card access. Palette RAM /WE and BIOS /OE generation.
 
 
 
{|
 
|
 
[[File:Neo-g0_C7_pinout.png|512px]]
 
 
 
OpenOffice Draw file: [[File:neo-g0_mv2b_C7.odg]]
 
|
 
Very similar connections with the one used in the AES.
 
*D0~D15: [[68k]] data bus
 
*PALD0~PALD7: Lower [[palette RAM]] data bus
 
*PAUD0~PAUD7: Upper palette RAM data bus
 
*MCD0~MCD15: [[Memory card]] data bus
 
 
 
*28 C0 (PAL ?):Palette RAM address decode from [[PRO-C0]]
 
*R/W: R/W from 68k
 
*PALWE: Palette RAM /WE, output made from PAL OR R/W
 
 
 
*SROMOEL, SROMOEU: from PRO-C0, BIOS byte /OE
 
*ROMOE: [[BIOS]] ROM /OE, output made from SROMOEU AND SROMOEL
 
 
 
|}
 
 
 
<div style="clear: left;"></div>
 
  
 
[[Category:Chips]]
 
[[Category:Chips]]

Latest revision as of 19:35, 2 May 2020

Aes g0.jpg
Package QFP64R
Manufacturer Logo fujitsu.jpg
First use 1992 ?
Used on MV2B ...

Quadruple 245 with additional OR and AND gates. Predecessor of NEO-BUF.

Internal logic

Schematic is wrong: A and B sides are flipped !

Neo-g0 internal.png

  • Pin 51 is enable for MCD0~MCD15
  • Pin 39 is enable for PALD0~PALD15
  • Pin 40 is direction select for D0~D7
  • Pin 52 is direction select for D8~D15

Pinouts

AES

Palette RAM and memory card access. Palette RAM /WE and P1 ROM /OE generation.

NEO-G0 aes pinout.png
Edit this pinout

  • D0~D15: 68k data bus
  • PALD0~PALD7: Lower palette RAM data bus
  • PAUD0~PAUD7: Upper palette RAM data bus
  • MCD0~MCD15: Memory card data bus
  • PAL: Palette RAM address decode from NEO-C1
  • R/W: R/W from 68k
  • PALWE: Palette RAM /WE, output made from PAL OR R/W
  • ROMOEL, ROMOEU: from PRO-C0
  • ROMOE: Cartridge P ROM /OE, output made from ROMOEU AND ROMOEL

MV2B