Difference between revisions of "NEO-G0"

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[[File:Aes_g0.jpg|right|thumb|NEO-G0 chip found on an AES board.]]
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[[File:Aes_g0.jpg|right|thumb]]
  
Gates the [[68k]] data bus to the memory card slot and palette RAM. Only found in AES systems ?
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Quadruple 245 with OR and AND gates. Predecessor of [[NEO-BUF]].
  
PROG B22 (AES cart ROMOE ?) = ROMOEU AND ROMOEL like in [[NEO-E0]] ?
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=Internal logic=
  
PALWE = PAL OR R/W.
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{|
 +
|
 +
[[File:neo-g0_internal.png]]
 +
|
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*Pin 51 is enable for MCD0~MCD15
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*Pin 39 is enable for PALD0~PALD15
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*Pin 40 is direction select for D0~D7
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*Pin 52 is direction select for D8~D15
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|}
  
=Pinout=
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=AES pinout=
  
[[File:Neo-g0_pinout.png]]
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{|
 +
|
 +
[[File:Neo-g0_aes_pinout.png|512px|]]
  
OpenOffice Draw file: [[File:neo-g0.odg]]
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OpenOffice Draw file: [[File:neo-g0_aes.odg]]
 +
|
 +
*D0~D15: [[68k]] data bus
 +
*PALD0~PALD7: Lower [[palette RAM]] data bus
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*PAUD0~PAUD7: Upper palette RAM data bus
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*MCD0~MCD15: [[Memory card]] data bus
  
*D0~D15: 68k data bus
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*PAL: Palette RAM address decode from [[PRO-C0]]
*PALD0~PALD7: lower byte of palette data
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*R/W: R/W from 68k
*PAUD0~PAUD7: upper byte of palette data
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*PALWE: Palette RAM /WE, output made from PAL OR R/W
*MCD0~MCD15: memory card data bus
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*(51) is "enable MCD0~MCD15" pin
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*ROMOEL, ROMOEU: from PRO-C0
*(39) is "enable PALD0~PALD15" pin (confirmed on MV-2F chip used as ADPCM-A multiplexer):
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*ROMOE: Cartridge [[P ROM]] /OE, output made from ROMOEU AND ROMOEL
**NEO-F0 -> NEO-G0 @ K9:
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|}
**SLOT0(48) -> SEL?(51)
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**SLOT1(49) -> "PAL"(39)
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<div style="clear: left;"></div>
*(40) is a direction select for "D0~D7" (negated /ROE from 2610 sent here and RAD0~RAD7 connected to "D0~D7" of G0
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*(52) is a direction select for "D8~D15" (negated /POE sent here, PAD0~PAD7 connected to "D8~D15"
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=MV2B @ J4 pinout=
 +
 
 +
{|
 +
|
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[[File:Neo-g0_J4_pinout.png|512px]]
 +
 
 +
OpenOffice Draw file: [[File:neo-g0_mv2b_J4.odg]]
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|
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*D0~D15: [[68k]] data bus
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*1D0~1D15: Slot 1 68k data bus
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*2D0~2D15: Slot 2 68k data bus
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 +
*DS0,DS1: Slot 68k data enables from [[NEO-I0]]
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*R/W: R/W from 68k
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|}
 +
 
 +
<div style="clear: left;"></div>
 +
 
 +
 
 +
=MV2B @ J12 pinout=
 +
 
 +
{|
 +
|
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[[File:Neo-g0_J12_pinout.png|512px]]
 +
 
 +
OpenOffice Draw file: [[File:neo-g0_mv2b_J12.odg]]
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|
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*SDRAD0~SDRAD7: ADPCM-A data bus from [[YM2610]]
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*1SDRAD0~1SDRAD7: ADPCM-A data bus for slot 1
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*2SDRAD0~2SDRAD7: ADPCM-A data bus for slot 2
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 +
*SDPAD0~SDPAD7: ADPCM-B data bus from YM2610
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*1SDPAD0~1SDPAD7: ADPCM-B data bus for slot 1
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*2SDPAD0~2SDPAD7: ADPCM-B data bus for slot 2
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 +
*10 AS04: negated /ROE from YM2610
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*12 AS04: negated /POE from YM2610
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*SLOT0, SLOT1: enables from [[NEO-F0]]
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 +
|}
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 +
<div style="clear: left;"></div>
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 +
=MV2B @ C7 pinout=
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 +
{|
 +
|
 +
[[File:Neo-g0_C7_pinout.png|512px]]
 +
 
 +
OpenOffice Draw file: [[File:neo-g0_mv2b_C7.odg]]
 +
|
 +
Very similar connections with the one used in the AES.
 +
*D0~D15: [[68k]] data bus
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*PALD0~PALD7: Lower [[palette RAM]] data bus
 +
*PAUD0~PAUD7: Upper palette RAM data bus
 +
*MCD0~MCD15: [[Memory card]] data bus
 +
 
 +
*28 C0 (PAL ?): from [[PRO-C0]]
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*4 J2: ?
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*R/W: R/W from 68k
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 +
*SROMOEL, SROMOEU: from PRO-C0, BIOS byte /OE
 +
*ROMOE: [[BIOS]] ROM /OE, output made from SROMOEU AND SROMOEL
 +
 
 +
|}
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 +
<div style="clear: left;"></div>
  
 
[[Category:Chips]]
 
[[Category:Chips]]

Revision as of 18:23, 13 August 2012

Aes g0.jpg

Quadruple 245 with OR and AND gates. Predecessor of NEO-BUF.

Internal logic

Neo-g0 internal.png

  • Pin 51 is enable for MCD0~MCD15
  • Pin 39 is enable for PALD0~PALD15
  • Pin 40 is direction select for D0~D7
  • Pin 52 is direction select for D8~D15

AES pinout

File:Neo-g0 aes pinout.png

OpenOffice Draw file: File:Neo-g0 aes.odg

  • D0~D15: 68k data bus
  • PALD0~PALD7: Lower palette RAM data bus
  • PAUD0~PAUD7: Upper palette RAM data bus
  • MCD0~MCD15: Memory card data bus
  • PAL: Palette RAM address decode from PRO-C0
  • R/W: R/W from 68k
  • PALWE: Palette RAM /WE, output made from PAL OR R/W
  • ROMOEL, ROMOEU: from PRO-C0
  • ROMOE: Cartridge P ROM /OE, output made from ROMOEU AND ROMOEL

MV2B @ J4 pinout

Neo-g0 J4 pinout.png

OpenOffice Draw file: File:Neo-g0 mv2b J4.odg

  • D0~D15: 68k data bus
  • 1D0~1D15: Slot 1 68k data bus
  • 2D0~2D15: Slot 2 68k data bus
  • DS0,DS1: Slot 68k data enables from NEO-I0
  • R/W: R/W from 68k


MV2B @ J12 pinout

Neo-g0 J12 pinout.png

OpenOffice Draw file: File:Neo-g0 mv2b J12.odg

  • SDRAD0~SDRAD7: ADPCM-A data bus from YM2610
  • 1SDRAD0~1SDRAD7: ADPCM-A data bus for slot 1
  • 2SDRAD0~2SDRAD7: ADPCM-A data bus for slot 2
  • SDPAD0~SDPAD7: ADPCM-B data bus from YM2610
  • 1SDPAD0~1SDPAD7: ADPCM-B data bus for slot 1
  • 2SDPAD0~2SDPAD7: ADPCM-B data bus for slot 2
  • 10 AS04: negated /ROE from YM2610
  • 12 AS04: negated /POE from YM2610
  • SLOT0, SLOT1: enables from NEO-F0

MV2B @ C7 pinout

Neo-g0 C7 pinout.png

OpenOffice Draw file: File:Neo-g0 mv2b C7.odg

Very similar connections with the one used in the AES.

  • D0~D15: 68k data bus
  • PALD0~PALD7: Lower palette RAM data bus
  • PAUD0~PAUD7: Upper palette RAM data bus
  • MCD0~MCD15: Memory card data bus
  • 28 C0 (PAL ?): from PRO-C0
  • 4 J2: ?
  • R/W: R/W from 68k
  • SROMOEL, SROMOEU: from PRO-C0, BIOS byte /OE
  • ROMOE: BIOS ROM /OE, output made from SROMOEU AND SROMOEL