Difference between revisions of "NEO-G0"

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m (corrected pins)
m (direction)
Line 22: Line 22:
 
**SLOT0(48) -> SEL?(51)
 
**SLOT0(48) -> SEL?(51)
 
**SLOT1(49) -> "PAL"(39)
 
**SLOT1(49) -> "PAL"(39)
 +
*(40) is a direction select for "D0~D7" (negated /ROE from 2610 sent here and RAD0~RAD7 connected to "D0~D7" of G0
 +
*(52) is a direction select for "D8~D15" (negated /POE sent here, PAD0~PAD7 connected to "D8~D15"
  
 
[[Category:Chips]]
 
[[Category:Chips]]

Revision as of 05:28, 10 May 2012

NEO-G0 chip found on an AES board.

Gates the 68k data bus to the memory card slot and palette RAM. Only found in AES systems ?

PROG B22 (AES cart ROMOE ?) = ROMOEU AND ROMOEL like in NEO-E0 ?

PALWE = PAL OR R/W.

Pinout

File:Neo-g0 pinout.png

OpenOffice Draw file: File:Neo-g0.odg

  • D0~D15: 68k data bus
  • PALD0~PALD7: lower byte of palette data
  • PAUD0~PAUD7: upper byte of palette data
  • MCD0~MCD15: memory card data bus
  • (51) is "enable MCD0~MCD15" pin
  • (39) is "enable PALD0~PALD15" pin (confirmed on MV-2F chip used as ADPCM-A multiplexer):
    • NEO-F0 -> NEO-G0 @ K9:
    • SLOT0(48) -> SEL?(51)
    • SLOT1(49) -> "PAL"(39)
  • (40) is a direction select for "D0~D7" (negated /ROE from 2610 sent here and RAD0~RAD7 connected to "D0~D7" of G0
  • (52) is a direction select for "D8~D15" (negated /POE sent here, PAD0~PAD7 connected to "D8~D15"