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Revision as of 19:35, 2 May 2020 by Furrtek (talk | contribs) (Internal logic)
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Aes g0.jpg
Package QFP64R
Manufacturer Logo fujitsu.jpg
First use 1992 ?
Used on MV2B ...

Quadruple 245 with additional OR and AND gates. Predecessor of NEO-BUF.

Internal logic

Schematic is wrong: A and B sides are flipped !

Neo-g0 internal.png

  • Pin 51 is enable for MCD0~MCD15
  • Pin 39 is enable for PALD0~PALD15
  • Pin 40 is direction select for D0~D7
  • Pin 52 is direction select for D8~D15



Palette RAM and memory card access. Palette RAM /WE and P1 ROM /OE generation.

NEO-G0 aes pinout.png
Edit this pinout

  • D0~D15: 68k data bus
  • PALD0~PALD7: Lower palette RAM data bus
  • PAUD0~PAUD7: Upper palette RAM data bus
  • MCD0~MCD15: Memory card data bus
  • PAL: Palette RAM address decode from NEO-C1
  • R/W: R/W from 68k
  • PALWE: Palette RAM /WE, output made from PAL OR R/W
  • ROMOE: Cartridge P ROM /OE, output made from ROMOEU AND ROMOEL