PCM: Difference between revisions
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[[File:crt_pcm.jpg|right|thumb|NEO-PCM chip found in a MVS cartridge. Picture courtesy of [[http://www.mvs-scans.com MVS-Scans]].]] | [[File:crt_pcm.jpg|right|thumb|NEO-PCM chip found in a MVS cartridge. Picture courtesy of [[http://www.mvs-scans.com MVS-Scans]].]] | ||
[[V ROM]] banking and | Early cartridges had separate ADPCM-A and ADPCM-B sound ROMs. Since one was often emptier than the other, SNK devised a way to mix both types in the same ROM chip to reduce cost. | ||
PCM (not "'''NEO'''-PCM" for some reason) is a [[V ROM]] banking and demultiplexing chip, found in AES and MVS [[cartridges]], and on [[ROM-Only boards|ROM-only]] arcade boards. Used to demultiplex V ROM (ADPCM-A and ADPCM-B) data from mixed-content ROM chips. | |||
[[NEO-PCM2]] can also be found in late cartridges and with [[NEO-YSA2]]. | [[NEO-PCM2]] can also be found in late cartridges and with [[NEO-YSA2]]. | ||
On some [[:Category:cartridge boards|Cartridge boards]], | On some [[:Category:cartridge boards|Cartridge boards]], VA20~VA22 can be used to select which of the 4 possible V ROMs to use (decoded by a LS139). | ||
Uses several latches for address and data, as well as a 4-bit counter on {{Sig|68KCLKB|68KCLKB}} for synchronisation. | |||
=Internal logic= | =Internal logic= | ||
Revision as of 18:38, 15 January 2016
Early cartridges had separate ADPCM-A and ADPCM-B sound ROMs. Since one was often emptier than the other, SNK devised a way to mix both types in the same ROM chip to reduce cost.
PCM (not "NEO-PCM" for some reason) is a V ROM banking and demultiplexing chip, found in AES and MVS cartridges, and on ROM-only arcade boards. Used to demultiplex V ROM (ADPCM-A and ADPCM-B) data from mixed-content ROM chips.
NEO-PCM2 can also be found in late cartridges and with NEO-YSA2.
On some Cartridge boards, VA20~VA22 can be used to select which of the 4 possible V ROMs to use (decoded by a LS139).
Uses several latches for address and data, as well as a 4-bit counter on 68KCLKB for synchronisation.
Internal logic
Takes advantage of the asynchronous reading from the YM2610. See YM2610 bus timing.
Verilog: todo.
Pinout
OpenOffice Draw file: File:Pcm.odg
Has an inverting gate on pins 26 and 27.
- SDPOE, SDROE, SDPMPX, SDRMPX: from the YM2610
- SDRAD0~SDRAD7: ADPCM-A multiplexed bus part
- SDPAD0~SDPAD7: ADPCM-B multiplexed bus part
- SDRA8,SDRA9,SDRA20~SDRA23: ADPCM-A address bus
- SDPA8~SDPA11: ADPCM-B address bus
- V D0~V D7: V ROM(s) data bus
- V A-1~V A22: V ROM(s) address bus