Difference between revisions of "Signals"

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m (CPU (68k))
 
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*4M, 6M, 12M, 24M: 4MHz, 6MHz, 12MHz, and 24MHz clock signals
+
Most names come from the official [[schematics]].
*2H1: S ROM A3
+
 
*4MB: 4MHz inverted
+
=Clocks=
*A1~A23: [[68k]] address bus
+
{| class="regdef"
*A22I,A23I: A22 and A23 modified for [[68k vector table]] swap
+
|'''Name'''
*AS: 68k Address Strobe
+
|'''Description'''
*BNK0~2: [[Memory card]] bank selection
+
|'''Type'''
*CA4: C ROM A4
+
|'''Comes from'''
*C* or CR0~CR31: [[C ROM]]s data bus (2*16bits), holds data for one 8 pixels line
+
|'''Fault consequence'''
*D0~D15: 68k data bus
+
|-
*/DTACK: 68k Data Transmit ACKnowledge
+
|24M
*FIXD0~FIXD7: S ROM data bus
+
|24MHz master clock
*P0~P23: C ROM, [[S ROM]] and [[LO ROM]] address/data bus (multiplexed)
+
|[[Clock]]
*PCK1B: Clock to latch C ROM address from P0~P23 ([[NEO-273|mapping]]) on rising edge
+
|{{Chipname|NEO-D0}}
*PCK2B: Clock to latch S ROM address from P0~P15 ([[NEO-273|mapping]]) on rising edge
+
|Nothing works, no video at all
*/PORTADRS: $200000-$2FFFFF (P2+ ROM/Security chip) any access
+
|-
*/PORTOEL: $200000-$2FFFFF (P2+ ROM/[[PRO-CT0|Security chip]]) odd byte read
+
|12M
*/PORTOEU: $200000-$2FFFFF (P2+ ROM/Security chip) even byte read
+
|12MHz clock (24/2) non-inverted
*/PORTWEL: $200000-$2FFFFF (P2+ ROM/Security chip) odd byte write
+
|Clock
*/PORTWEU: $200000-$2FFFFF (P2+ ROM/Security chip) even byte write
+
|{{Chipname|NEO-D0}}
*/PWAIT0, /PWAIT1: adds 0 to 3 cycle delay for [[P ROM|P2 ROM]] reads
+
|Bad graphics
*R/W: 68k Read/Write
+
|-
*/ROMOE: $000000-$0FFFFF ([[P ROM|P1 ROM]]) read
+
|8M
*/ROMOEL: $000000-$0FFFFF (P1 ROM) odd byte read
+
|8MHz clock (24/3) non-inverted
*/ROMOEU: $000000-$0FFFFF (P1 ROM) even byte read
+
|Clock
*/ROMWAIT: add 1-cycle delay for [[P ROM|P1 ROM]] reads
+
|{{Chipname|LSPC}}
*/SROMOE: $C00000-$CFFFFF ([[BIOS]]) read
+
|No sound
*/SROMOEL: $C00000-$CFFFFF (BIOS) odd byte read
+
|-
*/SROMOEU: $C00000-$CFFFFF (BIOS) even byte read
+
|6MB
 +
|6MHz clock (24/4) inverted
 +
|Clock
 +
|{{Chipname|NEO-D0}}
 +
|Black screen ?
 +
|-
 +
|4M
 +
|4MHz clock (24/6) non-inverted
 +
|Clock
 +
|{{Chipname|LSPC}}
 +
|No sound
 +
|-
 +
|4MB
 +
|4MHz clock (24/6) inverted
 +
|Clock
 +
|{{Chipname|LSPC}} + inverter
 +
|?
 +
|-
 +
|1MB
 +
|'''3MHz''' (!) clock (24/8) inverted
 +
|Clock
 +
|{{Chipname|NEO-D0}}
 +
|?
 +
|-
 +
|68KCLK
 +
|12MHz clock (24/2) non-inverted
 +
|Clock
 +
|{{Chipname|NEO-D0}}
 +
|[[Click of death]]
 +
|-
 +
|68KCLKB
 +
|12MHz clock (24/2) inverted
 +
|Clock
 +
|{{Chipname|NEO-D0}}
 +
|Bad ADPCM-B instruments in games using {{Chipname|PCM}}
 +
|}
 +
 
 +
=CPU ([[68k]])=
 +
{| class="regdef"
 +
|'''Name'''
 +
|'''Description'''
 +
|'''Type'''
 +
|'''Comes from'''
 +
|'''Fault consequence'''
 +
|-
 +
|A1~A23
 +
|[[68k]] address bus
 +
|Address
 +
|{{Chipname|68k}}
 +
|Click of death
 +
|-
 +
|A22I,A23I
 +
|Altered address lines for [[68k vector table]] swap
 +
|Address
 +
|{{Chipname|NEO-E0}}
 +
|Probably click of death
 +
|-
 +
|/AS
 +
|68k Address Strobe
 +
|Control
 +
|{{Chipname|68k}}
 +
|Probably click of death
 +
|-
 +
|D0~D15
 +
|68k data bus
 +
|Data
 +
|Multiple
 +
|Click of death
 +
|-
 +
|/DTACK
 +
|68k Data Transmit ACKnowledge (see [[wait cycle]])
 +
|Control
 +
|{{Chipname|NEO-C1}}
 +
|Click of death ?
 +
|-
 +
|/PORTADRS
 +
|$200000-$2FFFFF (P2 ROM/[[PRO-CT0|Security chip]]) any access
 +
|Control
 +
|{{Chipname|NEO-C1}}
 +
|Game freezes, bad graphics
 +
|-
 +
|/PORTOEL
 +
|$200000-$2FFFFF (P2 ROM/Security chip) odd byte read
 +
|Control
 +
|{{Chipname|NEO-C1}}
 +
|Game freezes, bad graphics
 +
|-
 +
|/PORTOEU
 +
|$200000-$2FFFFF (P2 ROM/Security chip) even byte read
 +
|Control
 +
|{{Chipname|NEO-C1}}
 +
|Game freezes, bad graphics
 +
|-
 +
|/PORTWEL
 +
|$200000-$2FFFFF (P2 ROM/Security chip) odd byte write
 +
|Control
 +
|{{Chipname|NEO-C1}}
 +
|Game freezes, [[multiplayer]] comm. error
 +
|-
 +
|/PORTWEU
 +
|$200000-$2FFFFF (P2 ROM/Security chip) even byte write
 +
|Control
 +
|{{Chipname|NEO-C1}}
 +
|Game freezes, bad graphics
 +
|-
 +
|/PWAIT0, /PWAIT1
 +
|Delay configuration for [[P ROM|P2 ROM]] reads, see [[wait cycle]]
 +
|Control
 +
|{{Chipname|NEO-C1}}
 +
|Game freezes (very likely)
 +
|-
 +
|R/W
 +
|68k Read/Write
 +
|Control
 +
|{{Chipname|68k}}
 +
|Click of death
 +
|-
 +
|/ROMOE
 +
|$000000-$0FFFFF ([[P ROM|P1 ROM]]) read
 +
|Control
 +
|{{Chipname|NEO-C1}} + AND
 +
|Game doesn't start
 +
|-
 +
|/ROMOEL
 +
|$000000-$0FFFFF (P1 ROM) odd byte read
 +
|Control
 +
|{{Chipname|NEO-C1}}
 +
|Game doesn't start
 +
|-
 +
|/ROMOEU
 +
|$000000-$0FFFFF (P1 ROM) even byte read
 +
|Control
 +
|{{Chipname|NEO-C1}}
 +
|Game doesn't start
 +
|-
 +
|/ROMWAIT
 +
|Add 1-cycle delay for P1 ROM reads
 +
|Control
 +
|{{Chipname|NEO-C1}}
 +
|Game freezes (unlikely)
 +
|-
 +
|/SROMOE
 +
|$C00000-$CFFFFF ([[System ROM]]) read
 +
|Control
 +
|{{Chipname|NEO-E0}}
 +
|Click of death
 +
|-
 +
|/SROMOEL
 +
|$C00000-$CFFFFF (System ROM) odd byte read
 +
|Control
 +
|{{Chipname|NEO-C1}}
 +
|Click of death
 +
|-
 +
|/SROMOEU
 +
|$C00000-$CFFFFF (System ROM) even byte read
 +
|Control
 +
|{{Chipname|NEO-C1}}
 +
|Click of death
 +
|-
 +
|}
 +
 
 +
=Graphics=
 +
{| class="regdef"
 +
|'''Name'''
 +
|'''Description'''
 +
|'''Type'''
 +
|'''Comes from'''
 +
|'''Fault consequence'''
 +
|-
 +
|2H1
 +
|[[S ROM]] A3
 +
|Address
 +
|{{Chipname|LSPC}}
 +
|Bad fix graphics
 +
|-
 +
|CA4
 +
|[[C ROM]]s A4
 +
|Address
 +
|{{Chipname|LSPC}}
 +
|Bad sprite graphics
 +
|-
 +
|C* or CR0~CR31
 +
|C ROMs data bus (2*16bits), data for one 8-pixels line
 +
|Data
 +
|{{Chipname|C ROM}}
 +
|Bad sprite graphics
 +
|-
 +
|FIXD0~FIXD7
 +
|[[Fix layer]] data bus, data for 2 pixels
 +
|Data
 +
|{{Chipname|S ROM}}
 +
|[[Graphic glitches|Static vertical lines]], solid color screen
 +
|-
 +
|P0~P23
 +
|Multiplexed [[P bus]]
 +
|Muxed
 +
|Multiple
 +
|Garbled or absent graphics
 +
|-
 +
|PA0~PA11
 +
|[[Palette RAM]] address bus
 +
|Address
 +
|{{Chipname|NEO-B1}}
 +
|Bad colors, snow, black screen
 +
|}
 +
 
 +
=Misc.=
 +
{| class="regdef"
 +
|'''Name'''
 +
|'''Description'''
 +
|'''Type'''
 +
|'''Comes from'''
 +
|'''Fault consequence'''
 +
|-
 +
|BNK0~2
 +
|[[Memory card]] bank selection
 +
|Control
 +
|{{Chipname|NEO-D0}}
 +
|Errors on access to big memory cards
 +
|}
 +
 
 +
=CPU ([[Z80]])=
 +
=Sound=
 +
 
 +
*PAL: Palette RAM address decode for 68k access
 +
*PCK1B: Low 55ns, high 610 (1.5MHz) Clock to latch C ROM address from P0~P23 ([[NEO-273|mapping]]) on rising edge.
 +
*PCK2B: Low 55ns, high 610 (1.5MHz) Clock to latch S ROM address from P0~P15 ([[NEO-273|mapping]]) on rising edge.
 
*SDA0~SDA15 : [[Z80]] address bus
 
*SDA0~SDA15 : [[Z80]] address bus
 
*SDD0~SDD7: Z80 data bus
 
*SDD0~SDD7: Z80 data bus
Line 36: Line 262:
 
*SYSTEM: low when onboard ROMs selected
 
*SYSTEM: low when onboard ROMs selected
 
*SYSTEMB: inverted SYSTEM
 
*SYSTEMB: inverted SYSTEM
*PA0~PA11: [[Palette RAM]] address bus
 
 
  
 
[[Category:Chips]]
 
[[Category:Chips]]
 +
[[Category:Repairs]]

Latest revision as of 05:46, 28 December 2018

Most names come from the official schematics.

Clocks

Name Description Type Comes from Fault consequence
24M 24MHz master clock Clock NEO-D0 Nothing works, no video at all
12M 12MHz clock (24/2) non-inverted Clock NEO-D0 Bad graphics
8M 8MHz clock (24/3) non-inverted Clock LSPC No sound
6MB 6MHz clock (24/4) inverted Clock NEO-D0 Black screen ?
4M 4MHz clock (24/6) non-inverted Clock LSPC No sound
4MB 4MHz clock (24/6) inverted Clock LSPC + inverter ?
1MB 3MHz (!) clock (24/8) inverted Clock NEO-D0 ?
68KCLK 12MHz clock (24/2) non-inverted Clock NEO-D0 Click of death
68KCLKB 12MHz clock (24/2) inverted Clock NEO-D0 Bad ADPCM-B instruments in games using PCM

CPU (68k)

Name Description Type Comes from Fault consequence
A1~A23 68k address bus Address 68k Click of death
A22I,A23I Altered address lines for 68k vector table swap Address NEO-E0 Probably click of death
/AS 68k Address Strobe Control 68k Probably click of death
D0~D15 68k data bus Data Multiple Click of death
/DTACK 68k Data Transmit ACKnowledge (see wait cycle) Control NEO-C1 Click of death ?
/PORTADRS $200000-$2FFFFF (P2 ROM/Security chip) any access Control NEO-C1 Game freezes, bad graphics
/PORTOEL $200000-$2FFFFF (P2 ROM/Security chip) odd byte read Control NEO-C1 Game freezes, bad graphics
/PORTOEU $200000-$2FFFFF (P2 ROM/Security chip) even byte read Control NEO-C1 Game freezes, bad graphics
/PORTWEL $200000-$2FFFFF (P2 ROM/Security chip) odd byte write Control NEO-C1 Game freezes, multiplayer comm. error
/PORTWEU $200000-$2FFFFF (P2 ROM/Security chip) even byte write Control NEO-C1 Game freezes, bad graphics
/PWAIT0, /PWAIT1 Delay configuration for P2 ROM reads, see wait cycle Control NEO-C1 Game freezes (very likely)
R/W 68k Read/Write Control 68k Click of death
/ROMOE $000000-$0FFFFF (P1 ROM) read Control NEO-C1 + AND Game doesn't start
/ROMOEL $000000-$0FFFFF (P1 ROM) odd byte read Control NEO-C1 Game doesn't start
/ROMOEU $000000-$0FFFFF (P1 ROM) even byte read Control NEO-C1 Game doesn't start
/ROMWAIT Add 1-cycle delay for P1 ROM reads Control NEO-C1 Game freezes (unlikely)
/SROMOE $C00000-$CFFFFF (System ROM) read Control NEO-E0 Click of death
/SROMOEL $C00000-$CFFFFF (System ROM) odd byte read Control NEO-C1 Click of death
/SROMOEU $C00000-$CFFFFF (System ROM) even byte read Control NEO-C1 Click of death

Graphics

Name Description Type Comes from Fault consequence
2H1 S ROM A3 Address LSPC Bad fix graphics
CA4 C ROMs A4 Address LSPC Bad sprite graphics
C* or CR0~CR31 C ROMs data bus (2*16bits), data for one 8-pixels line Data C ROM Bad sprite graphics
FIXD0~FIXD7 Fix layer data bus, data for 2 pixels Data S ROM Static vertical lines, solid color screen
P0~P23 Multiplexed P bus Muxed Multiple Garbled or absent graphics
PA0~PA11 Palette RAM address bus Address NEO-B1 Bad colors, snow, black screen

Misc.

Name Description Type Comes from Fault consequence
BNK0~2 Memory card bank selection Control NEO-D0 Errors on access to big memory cards

CPU (Z80)

Sound

  • PAL: Palette RAM address decode for 68k access
  • PCK1B: Low 55ns, high 610 (1.5MHz) Clock to latch C ROM address from P0~P23 (mapping) on rising edge.
  • PCK2B: Low 55ns, high 610 (1.5MHz) Clock to latch S ROM address from P0~P15 (mapping) on rising edge.
  • SDA0~SDA15 : Z80 address bus
  • SDD0~SDD7: Z80 data bus
  • SDRAD0~SDRAD7: ADPCM-A ROM multiplexed bus (data/address)
  • SDRA8,SDRA9,SDRA20~SDRA23: ADPCM-A ROM address bus
  • SDPAD0~SDPAD7: ADPCM-B ROM multiplexed bus (data/address)
  • SDPA8,SDPA9,SDPA10,SDPA11: ADPCM-B ROM address bus
  • SYSTEM: low when onboard ROMs selected
  • SYSTEMB: inverted SYSTEM