Vector address on cart systems: $68. On CD systems: $64.
This interrupt is triggered when the 32bit timer counter reaches 0 (is this timer completly internal to the LSPC ?). The value of this counter is decremented by the pixel clock (every 166.7ns), and reloaded with the specified value in REG_TIMERHIGH ($3C0008) and REG_TIMERLOW ($3C000A) each time one of these 3 selectable events occur:
- When REG_TIMERLOW register is set.
- At the beginning of the frame blanking period.
- When the timer counter reaches 0.
This interrupt needs to be acknowledged by the following instruction:
The REG_LSPCMODE ($3C0006.w) register is used to configure the timer's operation:
- Bit 7 = 1: Load timer counter when it becomes 0.
- Bit 6 = 1: Load timer counter at the beginning of the HBlank of the first VBlank line.
- Bit 5 = 1: Load timer counter as soon as REG_TIMERLOW is written to.
- Bit 4 = 1: Enable timer interrupt.
REG_TIMERHIGH and REG_TIMERLOW registers should never be set to 0.
To trigger interrupts for every N pixels, set the timer registers to N-1, and set bits 4 and 7 of REG_LSPCMODE.
To trigger interrupts when the scanning reaches multiple arbitrary display locations, set bits 4, 5 and 7 of REG_LSPCMODE. Then, in the interrupt handler routine, set the interval between the next interrupt and the following in the timer registers.