Timer interrupt

Vector address on cart systems: $68. On CD systems: $64.

This interrupt is triggered when the 32bit down-counter internal to LSPC reaches 0. The value of this counter is decremented by the pixel clock (6MHz, every 166.7ns), and reloaded with the specified value in REG_TIMERHIGH and REG_TIMERLOW each time one of these 3 selectable events occur:

• When REG_TIMERLOW register is written to.
• At the beginning of the frame blanking period.
• When the counter reaches 0 (repeat).

This interrupt needs to be acknowledged by the following instruction:

M0VE.W     #2,$3C000C

The REG_LSPCMODE ($3C0006.w) register is used to configure the timer's operation:

• Bit 7 = 1: Load counter when it becomes 0.
• Bit 6 = 1: Load counter at the beginning of the HBlank of the first VBlank line.
• Bit 5 = 1: Load counter as soon as REG_TIMERLOW is written to.
• Bit 4 = 1: Enable timer interrupt.

If bit 5 is set (load on value write), either bit 6, 7 or both must also be set to 1.

REG_TIMERHIGH and REG_TIMERLOW registers should never be set to 0.

To trigger interrupts for every N pixels, set the timer registers to N-1, and set bits 4 and 7 of REG_LSPCMODE.

To trigger interrupts when the scanning reaches multiple arbitrary display locations, set bits 4, 5 and 7 of REG_LSPCMODE. Then, in the interrupt handler routine, set the interval between the next interrupt and the following in the timer registers.