Video DAC: Difference between revisions

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[[File:aes_viddac_schematic.png]]
[[File:aes_viddac_schematic.png]]


Each color component has its own set of 7 resistors. 6 of them are used with the actual color value (5 + 1 [[Palettes|common bit]]). The last (SHADOW signal) is related to the {{Reg|REG_SHADOW}} and {{Reg|REG_NOSHADOW}} registers (74HC259 latch).
Each color component has its own set of 7 resistors. 6 of them are used with the actual color value (5 + 1 [[Colors|common bit]]). The last (SHADOW signal) is related to the {{Reg|REG_SHADOW}} and {{Reg|REG_NOSHADOW}} registers (74HC259 latch).


The output voltage is then divided by 2200 / (6800 + 2200) = 4.1 (considered Voh of 74LS ?), to obtain a 1Vp-p max signal, which can be fed to the [[video encoder]].
The output voltage is then divided by 2200 / (6800 + 2200) = 4.1 (considered Voh of 74LS ?), to obtain a 1Vp-p max signal, which can be fed to the [[video encoder]].

Revision as of 04:07, 12 October 2016

File:Mvs viddac.jpg
Resistor array forming the video DAC on a 1FZS.

The NeoGeo uses a discrete video Digital-to-Analog Converter made of resistors and two 74LS273 latches which store the color value from the palette RAM while the pixel has to be displayed. This is controlled by either NEO-B1, NEO-GRC or NEO-GRZ.

File:Aes viddac.png
Video DAC on a AES board.

File:Aes viddac schematic.png

Each color component has its own set of 7 resistors. 6 of them are used with the actual color value (5 + 1 common bit). The last (SHADOW signal) is related to the REG_SHADOW and REG_NOSHADOW registers (74HC259 latch).

The output voltage is then divided by 2200 / (6800 + 2200) = 4.1 (considered Voh of 74LS ?), to obtain a 1Vp-p max signal, which can be fed to the video encoder.