Difference between revisions of "Wait cycle"

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(Created page with "A wait cycle is a 68k bus cycle with no effects, the purpose of it is to allow the use of slow memories by "waiting" for them. The NeoGeo provides wait state generation...")
 
 
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A wait cycle is a [[68k]] bus cycle with no effects, the purpose of it is to allow the use of slow memories by "waiting" for them.  
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The [[68k]] is able to wait for data by making it insert wait cycles during bus access. This allows the use of slow, cheaper memories.
  
 
The NeoGeo provides wait state generation for 3 [[68k memory map|memory zones]]:
 
The NeoGeo provides wait state generation for 3 [[68k memory map|memory zones]]:
  
* 000000~0FFFFF: [[P ROM]] - Configurable, 0 or 1 cycle
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* 000000~0FFFFF: ROM zone ([[P ROM]]) - Configurable, 0 or 1 cycle
* 200000~2FFFFF: [[P ROM]] - Configurable, 0, 1 or more cycles
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* 200000~2FFFFF: PORT zone ([[P ROM]] or special chips) - Configurable, 0, 1, 2 or more cycles
 
* 800000~BFFFFF: [[Memory card]] - Fixed, 2 cycles
 
* 800000~BFFFFF: [[Memory card]] - Fixed, 2 cycles
  
Configuration is done by setting levels of the following [[pinouts|cartridge pins]]:
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=Configuration=
* ROMWAIT for 1 cycle in 000000~0FFFFF
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* PWAIT0 for 1 cycle in 200000~2FFFFF ?
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Configuration is done by setting the levels of the following [[pinouts|cartridge pins]]. '1' means pulled to 5V, '0' means pulled to ground. All signals are active low.
* PWAIT1 to enable PDTACK as a DTACK for 200000~2FFFFF ?
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{|class="wikitable"
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!ROMWAIT||ROM zone wait
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|-
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|1||Full speed
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|-
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|0||1 cycle
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|}
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{|class="wikitable"
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!PWAIT1||PWAIT0||PORT zone wait
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|-
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|1||1||Full speed
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|-
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|1||0||1 cycle
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|-
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|0||1||2 cycles
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|-
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|0||0||As long as PDTACK is high
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|}
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=Use cases=
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Some games rely on wait cycles to perform sufficiently spaced [[VRAM]] accesses. Disabling the wait on those cartridges causes the accesses to become too close to each other and results in graphics corruption.
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No originally released cartridges are known to use PDTACK.
  
 
[[Category:Base system]]
 
[[Category:Base system]]

Latest revision as of 08:50, 25 August 2019

The 68k is able to wait for data by making it insert wait cycles during bus access. This allows the use of slow, cheaper memories.

The NeoGeo provides wait state generation for 3 memory zones:

  • 000000~0FFFFF: ROM zone (P ROM) - Configurable, 0 or 1 cycle
  • 200000~2FFFFF: PORT zone (P ROM or special chips) - Configurable, 0, 1, 2 or more cycles
  • 800000~BFFFFF: Memory card - Fixed, 2 cycles

Configuration

Configuration is done by setting the levels of the following cartridge pins. '1' means pulled to 5V, '0' means pulled to ground. All signals are active low.

ROMWAIT ROM zone wait
1 Full speed
0 1 cycle
PWAIT1 PWAIT0 PORT zone wait
1 1 Full speed
1 0 1 cycle
0 1 2 cycles
0 0 As long as PDTACK is high

Use cases

Some games rely on wait cycles to perform sufficiently spaced VRAM accesses. Disabling the wait on those cartridges causes the accesses to become too close to each other and results in graphics corruption.

No originally released cartridges are known to use PDTACK.