Difference between revisions of "YM2610 registers"

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m (FM part)
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See [[FM]] for details on this part's operation.
 
See [[FM]] for details on this part's operation.
 
==Common FM registers==
 
 
{| class="regdef"
 
|'''Address (Z80 port 4)'''
 
|'''Data (Z80 port 5)'''
 
|
 
|-
 
|$22
 
|{{8BitRegister|-|4|On|1|Control|3}}
 
| LFO Frequency
 
|-
 
|$28
 
|{{8BitRegister|Slot|4|-|1|Channel|3|}}
 
| Key On/Off
 
|}
 
 
LFO frequency values are as follows:
 
*0 – 3.98Hz
 
*1 – 5.56Hz
 
*2 – 6.02Hz
 
*3 – 6.37Hz
 
*4 – 6.88Hz
 
*5 – 9.63Hz
 
*6 – 48.1Hz
 
*7 – 72.2Hz
 
 
==Overall channel registers==
 
The first value listed in the Address column is for channels 1/3; the second is for channels 2/4.
 
 
{|class="regdef"
 
| '''Address (Z80 port 4 or 6)''' || '''Data (Z80 port 5 or 7)''' ||
 
|-
 
| $A1,$A2
 
| {{8BitRegister|F-Num 1|8}}
 
| F-Numbers and Block (1/2)
 
|-
 
| $A5,$A6
 
| {{8BitRegister|-|2|Block|3|F-Num 2|3}}
 
| F-Numbers and Block (2/2)<br/>(must set this first)
 
|-
 
| $A9,$AA
 
| {{8BitRegister|2CH * F-Num 1|8}}
 
| 2CH - 2 Slot F-Numbers/Block (1/2)
 
|-
 
| $AD,$AE
 
| {{8BitRegister|-|2|2CH * Block|3|2CH * F-Num 2|3}}
 
| 2CH - 2 Slot F-Numbers/Block (1/2)<br/>(must set this first)
 
|-
 
| $B1,$B2
 
| {{8BitRegister|-|2|FB|3|ALGO|3}}
 
| Feedback (FB) and Algorithm (ALGO)
 
|-
 
| $B5,B6
 
| {{8BitRegister|L|1|R|1|AMS|2|-|1|PMS|3}}
 
| Left (L)/Right (R) output, AM Sense (AMS), and PM Sense (PMS)
 
|}
 
 
==Channel registers==
 
Depending on which channel you want to write to, the ports used are different:
 
* Channels 1 & 2: Ports 4/5
 
* Channels 3 & 4: Ports 6/7
 
 
===Per-operator registers===
 
The ranges given for the address represent all of the parameter values. Each channel's operators are laid out as follows:
 
 
{|class="wikitable"
 
! Operator || 1 || 2 || 3 || 4
 
|-
 
! Channels 1, 3
 
| $x1 || $x5 || $x9 || $xD
 
|-
 
! Channels 2, 4
 
| $x2 || $x6 || $xA || $xE
 
|}
 
 
{|class="regdef"
 
| '''Address (Z80 port 4 or 6)''' || '''Data (Z80 port 5 or 7)''' || &nbsp;
 
|-
 
| $31-$3E
 
| {{8BitRegister|-|1|DT|3|MUL|4}}
 
| Detune (DT) and Multiple (MUL)
 
|-
 
| $41-$4E
 
| {{8BitRegister|-|1|Total Level|7|}}
 
| Total Level (Volume)
 
|-
 
| $51-$5E
 
| {{8BitRegister|KS|2|-|1|AR|5}}
 
| Key Scale (KS) and Attack Rate (AR)
 
|-
 
| $61-$6E
 
| {{8BitRegister|AM|1|-|2|DR|5}}
 
| AM On (AM) and Decay Rate (DR)
 
|-
 
| $71-$7E
 
| {{8BitRegister|-|3|SR|5}}
 
| Sustain Rate (SR)
 
|-
 
| $81-$8E
 
| {{8BitRegister|SL|4|RR|4}}
 
| Sustain Level (SL) and Release Rate (RR)
 
|-
 
| $91-$9E
 
| {{8BitRegister|-|4|SSG-EG|4}}
 
| SSG-EG
 
|}
 
  
 
=ADPCM part=
 
=ADPCM part=

Revision as of 10:44, 18 February 2017

Summary: ...

Timers

See YM2610 timers.

SSG part

See SSG for details on this part's operation.

FM part

See FM for details on this part's operation.

ADPCM part

See ADPCM for details on this part's operation.

Reading

The only writable registers that can also be read are from the SSG. All other ports and addresses return different data.

Z80 port # Data Notes
$04
Bit 7 6 5 4 3 2 1 0
Def Busy -Timer B flagTimer A flag
When a timer expires and IRQ is enabled for the timer, the respective bit is set
$05
Bit 7 6 5 4 3 2 1 0
Def SSG register data
Attempting to read non-SSG registers will fail
$06
Bit 7 6 5 4 3 2 1 0
Def ADPCM-B end -CH6 endCH5 endCH4 endCH3 endCH2 endCH1 end
When a channel has reached the end address and stops, the respective bit is set, unless masked
$07 not implemented Always returns $00