Difference between revisions of "YM2610 registers"

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m (FM part)
m (Moved FM registers to dedicated page)
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Summary:
 
...
 
 
 
=Timers=
 
=Timers=
  
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=Reading=
 
=Reading=
  
The only writable registers that can also be read are from the SSG.  All other ports and addresses return different data.
+
The only writable registers that can also be read are the SSG ones.
  
 
{| class="regdef"
 
{| class="regdef"
|'''Z80 port #'''
+
|'''Z80 port'''
 
|'''Data'''
 
|'''Data'''
 
|Notes
 
|Notes
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|$04
 
|$04
 
|{{8BitRegister|Busy|1|-|5|Timer B flag|1|Timer A flag|1}}
 
|{{8BitRegister|Busy|1|-|5|Timer B flag|1|Timer A flag|1}}
|When a timer expires and IRQ is enabled for the timer, the respective bit is set
+
|When a timer expires and IRQ is enabled for the timer, the respective flag is set.
 
|-
 
|-
 
|$05
 
|$05
 
|{{8BitRegister|SSG register data|8}}
 
|{{8BitRegister|SSG register data|8}}
|Attempting to read non-SSG registers will fail
+
|Attempting to read non-SSG registers will fail.
 
|-
 
|-
 
|$06
 
|$06
 
|{{8BitRegister|ADPCM-B end|1|-|1|CH6 end|1|CH5 end|1|CH4 end|1|CH3 end|1|CH2 end|1|CH1 end|1}}
 
|{{8BitRegister|ADPCM-B end|1|-|1|CH6 end|1|CH5 end|1|CH4 end|1|CH3 end|1|CH2 end|1|CH1 end|1}}
|When a channel has reached the end address and stops, the respective bit is set, unless masked
+
|When a channel has reached the end address and stops, the respective bit is set (unless masked).
 
|-
 
|-
 
|$07
 
|$07
|not implemented
+
|Not implemented
 
|Always returns $00
 
|Always returns $00
 
|-
 
|-

Revision as of 10:47, 18 February 2017

Timers

See YM2610 timers.

SSG part

See SSG for details on this part's operation.

FM part

See FM for details on this part's operation.

ADPCM part

See ADPCM for details on this part's operation.

Reading

The only writable registers that can also be read are the SSG ones.

Z80 port Data Notes
$04
Bit 7 6 5 4 3 2 1 0
Def Busy -Timer B flagTimer A flag
When a timer expires and IRQ is enabled for the timer, the respective flag is set.
$05
Bit 7 6 5 4 3 2 1 0
Def SSG register data
Attempting to read non-SSG registers will fail.
$06
Bit 7 6 5 4 3 2 1 0
Def ADPCM-B end -CH6 endCH5 endCH4 endCH3 endCH2 endCH1 end
When a channel has reached the end address and stops, the respective bit is set (unless masked).
$07 Not implemented Always returns $00