YM2610 ADPCM bus
The YM2610's accesses to the ADPCM V ROM(s) are made via dedicated multiplexed buses, which for some reason don't have both the exact same address bit mapping. This method saved pins on both the YM2610 chip and the cartridges.
The SDRMPX and SDPMPX signals are used to control latches or the PCM chip in cartridges to demultiplex addresses. When SDROE or SDPOE go low, SDRAD* and SDPAD* carry the ROM(s) output data.
Both demultiplexed address are 24 bits, allowing for a maximum of 16MiB V ROM data. No original game used bankswitching to extend this limit.
ADPCM-A bus
Address bit mapping:
| SDRMPX edge | SDRAD* | SDRA* | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 20 | 21 | 22 | 23 | |
| Low to high | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | ? | ? | ? | ? |
| High to low | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 |
Access to the ADPCM-A data for each channel are done sequentially (in the channels order ?). Steps are based on a ~667kHz clock derived from the YM2610's 8MHz clock by dividing it by 12.
- Period 0: The address LSBs are set
- Period 1: SDRMPX goes high
- Period 2: The address MSBs are set
- Period 3: SDRMPX goes low
- Period 4: SDROE goes low, RAD0~7 on YM2610 become inputs
- Period 5: ROM outputs data, latched on the rising edge of SDROE
Each period is 1.5us, a complete read cycle is 6 * 1.5 = 9us.
ADPCM-B bus
Address bit mapping:
| SDPMPX edge | SDPAD* | SDPA* | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | |||
| Low to high | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | ||
| High to low | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | ||
Access sequences to the ADPCM-B data are more or less spaced apart depending on the channel's delta setting. Steps are based on a 4MHz clock, much shorter than those for ADPCM-A.
- Period 0: The address LSBs are set
- Period 1: SDPMPX goes high
- Period 2: The address MSBs are set
- Period 3: SDPMPX goes low
- Period 4: SDPOE goes low, PAD0~7 on YM2610 become inputs
- Period 5: ROM outputs data, latched on the rising edge of SDPOE
Each period is 250ns, each complete read cycle is 6 * 250 = 1.5us. Reads can happen every 2 ADPCM-A reads at most (55.5kHz samplerate).