Latest revision as of 11:34, 29 December 2018

Seems to be the sixth and latest board revision.

Some (all ?) units appear to be heavily shielded with a metal cover and conductive coating on the plastic shell.

Differences with the NEO-AES3-6 board

The power supply circuit was (finally) moved next to the power connector.
Most through-hole chips were replaced by their surface mount versions.
The PLCC version of the 68k CPU was used. Also tiny Z80.
The SP1 ROM is an OTP part.
Resistor networks were added on bus lines, maybe as an attempt to reduce radiated noise.
TC9018P composite sync generator.
SYNC/NEW-SYNC jumper.
BNKB/RBNKB jumper.

@@ Line 1: / Line 1: @@
-Seems to be the sixth and latest board revision. Some (all?) units have a metal shield.
+[[File:4-1.jpg|thumb|Neo Geo AES 4-1 board]]
-[[File:4-1.jpg]]
+Seems to be the sixth and latest board revision.
+Some (all ?) units appear to be heavily shielded with a metal cover and conductive coating on the plastic shell.
+=Differences with the [[NEO-AES3-6 board]]=
+* The power supply circuit was (finally) moved next to the power connector.
+* Most through-hole chips were replaced by their surface mount versions.
+* The PLCC version of the [[68k]] CPU was used. Also tiny Z80.
+* The [[System_ROM|SP1 ROM]] is an OTP part.
+* Resistor networks were added on bus lines, maybe as an attempt to reduce radiated noise.
+* TC9018P composite sync generator.
+* {{Sig|SYNC|SYNC}}/NEW-SYNC jumper.
+* {{Sig|BNKB|BNKB}}/RBNKB jumper.
+[[Category:Cartridge_systems]]