NEO-CMC: Difference between revisions

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[[File:crt_cmc.jpg|thumb|"CMC42" chip on a MVS [[cartridges|cartridge]]. Picture courtesy of [[http://www.mvs-scans.com MVS-Scans]].]]
{{ChipInfo
|picture=crt_cmc.jpg
|pkg=QFP180
|manu=toshiba
|date=1999 ?
|gates=A lot
|used_on={{PCB|CHAFIO}}...
}}
 
[[File:brd_cmcnoref.jpg|thumb|"CMC50"]]
[[File:brd_cmcnoref.jpg|thumb|"CMC50"]]


Late SNK custom chip used for protection, bankswitching and latching on [[CHAFIO]] [[CHA board]]s.
Late SNK custom chip used for protection, bankswitching and latching on [[CHAFIO]] [[CHA board]]s.


Descrambling/decryption infos can be found in [[https://github.com/mamedev/mame/src/devices/bus/neogeo/prot_cmc.cpp  MAME:prot_cmc.c]]
Descrambling/decryption infos can be found in [[https://github.com/mamedev/mame/blob/master/src/devices/bus/neogeo/prot_cmc.cpp  MAME:prot_cmc.c]]


==Versions==
==Versions==
Line 17: Line 25:
SNK merged the following designs into this chip:
SNK merged the following designs into this chip:
*{{Chipname|NEO-ZMC}}
*{{Chipname|NEO-ZMC}}
*{{Chipname|NEO-ZMC2}}
*{{Chipname|NEO-273}}
*{{Chipname|NEO-273}}
*New scrambling system that interlaces M1 + (C* + S1) to decrypt all the graphics ROMs data in real time.
*{{Chipname|PRO-CT0}}
*New scrambling system that interlaces M1 + (C* + S1) to decrypt all the graphics ROMs data in real time (NEOCMC42).
*New scrambling system that interlaces M1 + (C* + S1) to decrypt all the graphics ROMs data and Sound Driver ROM data in real time (NEOCMC50).


The first released NEO-MVS CHAFIO PCBs came out with the '''042''' version of NEO-CMC, on the following cartridges:
The first released NEO-MVS CHAFIO PCBs came out with the '''042''' version of NEO-CMC, on the following cartridges:
Line 62: Line 73:
OpenOffice Draw file: [[File:Neocmc_7050_7042.odg]]
OpenOffice Draw file: [[File:Neocmc_7050_7042.odg]]


Signals:
'''Signals:'''
*C_e_D[0..15]: C odd data bus
CXe_D[0..15]: C odd data bus
*C_o_D[0..15]: C even data bus
CXo_D[0..15]: C even data bus
*CX A[0..21]: C1~8 address bus
CX_A[0..21]: C1~8 address bus
*Pins 87,88 contains a RC circuit clock driver like in a 8085 with X1 and X2 pinouts
*Pins 89 and 92 are shorted.
Pin : 32 connects to Mitsumi (PST600D) reset generator to re-initialize the NEO-CMC in case of power failure.
Pins: 87 and 88 contains a RC circuit clock driver like in a 8085 with X1 and X2 pinouts
Pins: 89 and 92 are interconnected.
Pin : 94 is configured in:
      NEO-MVS CHAFIO as NC
      NEO-AEG CHAFIO as 12M
Pin :147 is configured in:
      '''NEO-MVS CHAFIO''' (2003.07.24) as M1_CE
      '''NEO-MVS CHAFIO''' (1999.06.14) as NC
      NEO-AEG CHAFIO (2003.07.24) as M1_CE
      NEO-AEG CHAFIO (1999.08.10) as NC
 
 
'''Comparing MVS and AES Cartridges vs MVH PCBs:'''
Pin :147 is configured in:
      NEO-MVH MVOC  (2003.11.03) as M1_CE (KOF2003 pcb)
      NEO-MVH MVOBR  (2003.08.04) as M1_CE (MSLUG5 pcb)
      '''NEO-MVS CHAFIO (2003.07.24) as M1_CE'''
      '''NEO-AEG CHAFIO (2003.07.24) as M1_CE'''
      NEO-MVS MVOB  (2003.07.09) as NC    (SVC pcb - '''fixed by wirewrap''')
      NEO-MVS MVO    (2003.06.05) as NC    (SVC pcb)
      '''NEO-MVS CHAFIO (1999.06.14) as NC'''
      '''NEO-AEG CHAFIO (1999.08.10) as NC'''
Pin : 152 is configured in:
      NEO-MVH (MVOC) as VCC
      NEO-MVH (MVO, MVOB, MVOBR) as GND
      '''NEO-MVS (ALL) as GND'''
      '''NEO-AEG (ALL) as GND'''
 
'''Final Notes'''
'''NOTE1:''' There are no pinout differences between NEO-CMC42 and NEO-CMC50 however, differences can be spotted between previous and later board releases with respect to some setup lines and pin 147. A substantial setup difference can be found comparing the boards of AES and MVS releases. The way the chip access and delivery the graphic data is different between them and both configurations are available inside the NEO-CMC that is configured by the setup of the board itself. So the NEO-CMC is '''interchangeable between boards''' between MVS, AES, and MVH embedded. See the releases at ([[CHAFIO]])
'''NOTE2:''' In case somebody wonders, it's impossible to downgrade or upgrade NEO-CMCs between different versions (from 42 to 50 and vice-versa). The reason is that it's impossible without preparing the game for that and the algorithm to do it is unknown.
 
 
[[Category:Chips]]
[[Category:Chips]]

Latest revision as of 18:35, 28 July 2023

Package QFP180
Manufacturer
First use 1999 ?
Used on CHAFIO...
File:Brd cmcnoref.jpg
"CMC50"

Late SNK custom chip used for protection, bankswitching and latching on CHAFIO CHA boards.

Descrambling/decryption infos can be found in [MAME:prot_cmc.c]

Versions

This chip is a TC190G series Toshiba ASIC developed between 1990 and 1994.

The datasheet apparently can't be found anymore for any of the known types:

  • TC190G06CF7008
  • TC190G06CF7042
  • TC190G06CF7050

(probably others...)

SNK merged the following designs into this chip:

  • NEO-ZMC
  • NEO-ZMC2
  • NEO-273
  • PRO-CT0
  • New scrambling system that interlaces M1 + (C* + S1) to decrypt all the graphics ROMs data in real time (NEOCMC42).
  • New scrambling system that interlaces M1 + (C* + S1) to decrypt all the graphics ROMs data and Sound Driver ROM data in real time (NEOCMC50).

The first released NEO-MVS CHAFIO PCBs came out with the 042 version of NEO-CMC, on the following cartridges:

On this version only the S1 and C ROMs are encrypted and M1 remains unencrypted. Almost one year later, SNK decided to add one more layer, this time also encrypting M1. This new NEO-CMC chip had the 050 reference and was found in the following cartridges:

Until today, nobody has released a cloned chip on the underground market.

Fix handling

See fix bankswitching.

Encryption

Todo.

Pinout

OpenOffice Draw file: File:Neocmc 7050 7042.odg

Signals: 

CXe_D[0..15]: C odd data bus
CXo_D[0..15]: C even data bus
CX_A[0..21]: C1~8 address bus

Pin : 32 connects to Mitsumi (PST600D) reset generator to re-initialize the NEO-CMC in case of power failure.
Pins: 87 and 88 contains a RC circuit clock driver like in a 8085 with X1 and X2 pinouts
Pins: 89 and 92 are interconnected.
Pin : 94 is configured in:
     NEO-MVS CHAFIO as NC 
     NEO-AEG CHAFIO as 12M
Pin :147 is configured in:
     NEO-MVS CHAFIO (2003.07.24) as M1_CE
     NEO-MVS CHAFIO (1999.06.14) as NC
     NEO-AEG CHAFIO (2003.07.24) as M1_CE
     NEO-AEG CHAFIO (1999.08.10) as NC


Comparing MVS and AES Cartridges vs MVH PCBs: 

Pin :147 is configured in:
     NEO-MVH MVOC   (2003.11.03) as M1_CE (KOF2003 pcb)
     NEO-MVH MVOBR  (2003.08.04) as M1_CE (MSLUG5 pcb)
     NEO-MVS CHAFIO (2003.07.24) as M1_CE
     NEO-AEG CHAFIO (2003.07.24) as M1_CE
     NEO-MVS MVOB   (2003.07.09) as NC    (SVC pcb - fixed by wirewrap)
     NEO-MVS MVO    (2003.06.05) as NC    (SVC pcb) 
     NEO-MVS CHAFIO (1999.06.14) as NC
     NEO-AEG CHAFIO (1999.08.10) as NC

Pin : 152 is configured in:
     NEO-MVH (MVOC) as VCC
     NEO-MVH (MVO, MVOB, MVOBR) as GND
     NEO-MVS (ALL) as GND
     NEO-AEG (ALL) as GND

Final Notes 

NOTE1: There are no pinout differences between NEO-CMC42 and NEO-CMC50 however, differences can be spotted between previous and later board releases with respect to some setup lines and pin 147. A substantial setup difference can be found comparing the boards of AES and MVS releases. The way the chip access and delivery the graphic data is different between them and both configurations are available inside the NEO-CMC that is configured by the setup of the board itself. So the NEO-CMC is interchangeable between boards between MVS, AES, and MVH embedded. See the releases at (CHAFIO)

NOTE2: In case somebody wonders, it's impossible to downgrade or upgrade NEO-CMCs between different versions (from 42 to 50 and vice-versa). The reason is that it's impossible without preparing the game for that and the algorithm to do it is unknown.
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