NEO-CMC: Difference between revisions

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[[File:crt_cmc.jpg|thumb|"CMC42" chip on a MVS [[cartridges|cartridge]]. Picture courtesy of [[http://www.mvs-scans.com MVS-Scans]].]]
{{ChipInfo
|picture=crt_cmc.jpg
|pkg=QFP180
|manu=toshiba
|date=1999 ?
|gates=A lot
|used_on={{PCB|CHAFIO}}...
}}


The most "basic" information published can be found at [[http://mamedev.org/source/src/mame/machine/neocrypt.c.html MAME:neocrypt.c]]
[[File:brd_cmcnoref.jpg|thumb|"CMC50"]]
 
Late SNK custom chip used for protection, bankswitching and latching on [[CHAFIO]] [[CHA board]]s.
 
Descrambling/decryption infos can be found in [[https://github.com/mamedev/mame/blob/master/src/devices/bus/neogeo/prot_cmc.cpp  MAME:prot_cmc.c]]


Bellow the detailed information:
==Versions==
This chip is a TC190G series Toshiba ASIC developed between 1990 and 1994. Two versions of the chip are known to exist:


The NEO-CMC Chip is a Asic (Application Specific Integrated Circuit). This device can be programmed only once after be created severals prototypes until reach the stable condiction, using FPGA (Field Programmable Gate Array).
*TC190G06CF7'''042'''
The Asci must be considerated a final step from this process.
*TC190G06CF7'''050'''


To get a intuition about costs related, please read this:
They contain the logic for:
[[http://www.design-reuse.com/articles/9010/fpga-s-vs-asic-s.html FPGA vs ASICs production and design]]
*{{Chipname|NEO-ZMC2}}
*{{Chipname|NEO-273}}
*New scrambling system that interlaces M1 + (C* + S1) to decrypt all the graphics ROMs data in real time (042 version).
*New scrambling system that interlaces M1 + (C* + S1) to decrypt all the graphics ROMs data and Sound Driver ROM data in real time (050 version).


SNK had planned to put his next protection to try avoid NeoGeo piracy using the NEOCMC algorithm and the new PCB '''NEO-MVS CHAFIO'''.
The first released NEO-MVS CHAFIO PCBs came out with the '''042''' version of NEO-CMC, on the following cartridges:
*[[Zupapa!]]
*[[The King of Fighters '99 - Millennium Battle]]
*[[Ganryu]]
*[[Garou - Mark of the Wolves]]
*[[Strikers 1945 Plus]]
*[[Prehistoric Isle 2]]
*[[Metal Slug 3]]
*[[Bang Bead]]
*[[Nightmare in the Dark]]
*[[Sengoku 3]]


Because Toshiba was partner and not only made solution to hold data on it's Mask Roms (TC5xxxx), they has used its technology in Asic solutions to help to create this Chip. Until 1995 Toshiba had a line of Asics called TC190G series, the evolution of this series can be found at [[http://www.toshiba-components.com/ASIC/Technology.html Toshiba Technology RoadMap]].
On this version only the [[S ROM|S1]] and [[C ROM]]s are encrypted and M1 remains unencrypted. Almost one year later, SNK decided to add one more layer, this time also encrypting M1. This new NEO-CMC chip had the '''050''' reference and was found in the following cartridges:
*[[Jockey Grand Prix]]
*[[The King of Fighters 2000]]
*[[The King of Fighters 2001]]
*[[Metal Slug 4]]
*[[Rage of the Dragons]]
*[[The King of Fighters 2002]]
*[[Matrimelee]]
*[[Pochi and Nyaa]]
*[[Metal Slug 5]]
*[[SNK vs. Capcom - SVC Chaos]]
*[[Samurai Shodown V]]
*[[The King of Fighters 2003]]
*[[Samurai Shodown V Special]]


The serie that SNK get advantage to build a valuable chip with it's algorithm to protect Cs and S1 initially was the serie TC190G:
Until today, nobody has released a cloned chip on the underground market.


The series TC190G cannot be found in datasheets anymore, but in past years had these models:
==Fix handling==
*TC190G06CF7008
*TC1'''90G06CF7042'''
*TC1'''90G06CF7050'''
and more...


Apparently the last two models was used because the number of internal number of gates acceptable to the logic SNK have developed:
See [[fix bankswitching]].
*NEO-ZMC
*NEO-273
*And a new scrambling system for that interlaces M1 + (CX + S1) ROM data


Inicially the released model of CMC was '''NEO-CMC42''' on the following cartridges:
==Encryption==
{|
|'''CART ID'''
|'''TITLE NAME'''
|-
|070
|Zupapa
|-
|251
|King Of Fighters 99
|-
|252
|Ganryu
|-
|253
|Garou Mark Of the Wolves
|-
|254
|Strikers 1945
|-
|255
|Prehistoric Isle 2
|-
|256
|Metal Slug 3
|-
|259
|Bang Bead
|-
|260
|Nightmare in the Dark
|-
|261
|Sengoku 3
|-
|}


This version had only S1 and CRoms Encrypted and M1 remained in normal condition (unencrypted).
Todo.
This was just a "test", to see if SNK and Toshiba could be more further in protection.
Almost one year later SNK decided release one more layer on the algorithm, to encrypt M1 on the mixer.  


So they released the model '''NEO-CMC50''' on the following cartridges:
=Pinout=
{|
[[File:Neocmc_7050_7042_pinout.png|x600px]]
|'''CART ID'''
|'''TITLE NAME'''
|-
|008
|Jockey Grand Prix
|-
|257
|King Of Figthers 2000
|-
|262
|King Of Figthers 2001
|-
|263
|Metal Slug 4
|-
|264
|Rage of the Dragons
|-
|265
|King Of Fighters 2002
|-
|266
|Power Instinct - Matrimele
|-
|267
|Pochi to Nyaa
|-
|268
|Metal Slug 5
|-
|269
|SNK vs Capcom Chaos
|-
|270
|Samurai Showdown Zero / Samurai Showdown 5
|-
|271
|King of Fighters 2003
|-
|272
|Samurai Showdown Zero Special / Samurai Showdown 5 Special
|-
|}


Some peoples talk about Jockey Grand Prix not be a official game, but it´s not true.
OpenOffice Draw file: [[File:Neocmc_7050_7042.odg]]
At least it's production was official of the card was official, because they had used the real encryption that cannot be mocked easily.
Only the Toshiba and SNK knew the encryption. And until today "NO ONE" piracy goes so forensic to mock it. They prefer just Dump and use the dumped version on its own solution rater use the same chips.
That explain why several M1 Rom release over the web wasn't correct until Andreas Naive create a mathematical algorithm and publish. This made capable to create a correct DUMPED version of the M1, but the actual released algorithm will not help anybody that desire to put other unencrypted game in the encrypted condition over '''NEO-MVS CHANFIO''' PCB. This will not work!!! Explanation Later.


'''Signals:'''
CXe_D[0..15]: C odd data bus
CXo_D[0..15]: C even data bus
CX_A[0..21]: C1~8 address bus
Pin : 32 connects to Mitsumi (PST600D) reset generator to re-initialize the NEO-CMC in case of power failure.
Pins: 87 and 88 contains a RC circuit clock driver like in a 8085 with X1 and X2 pinouts
Pins: 89 and 92 are interconnected.
Pin : 94 is configured in:
      NEO-MVS CHAFIO as NC
      NEO-AEG CHAFIO as 12M
Pin :147 is configured in:
      '''NEO-MVS CHAFIO''' (2003.07.24) as M1_CE
      '''NEO-MVS CHAFIO''' (1999.06.14) as NC
      NEO-AEG CHAFIO (2003.07.24) as M1_CE
      NEO-AEG CHAFIO (1999.08.10) as NC




[[File:brd_cmcnoref.jpg|thumb|"CMC50"]]
'''Comparing MVS and AES Cartridges vs MVH PCBs:'''
Pin :147 is configured in:
      NEO-MVH MVOC  (2003.11.03) as M1_CE (KOF2003 pcb)
      NEO-MVH MVOBR  (2003.08.04) as M1_CE (MSLUG5 pcb)
      '''NEO-MVS CHAFIO (2003.07.24) as M1_CE'''
      '''NEO-AEG CHAFIO (2003.07.24) as M1_CE'''
      NEO-MVS MVOB  (2003.07.09) as NC    (SVC pcb - '''fixed by wirewrap''')
      NEO-MVS MVO    (2003.06.05) as NC    (SVC pcb)
      '''NEO-MVS CHAFIO (1999.06.14) as NC'''
      '''NEO-AEG CHAFIO (1999.08.10) as NC'''
Pin : 152 is configured in:
      NEO-MVH (MVOC) as VCC
      NEO-MVH (MVO, MVOB, MVOBR) as GND
      '''NEO-MVS (ALL) as GND'''
      '''NEO-AEG (ALL) as GND'''
 
'''Final Notes'''
'''NOTE1:''' There are no pinout differences between NEO-CMC42 and NEO-CMC50 however, differences can be spotted between previous and later board releases with respect to some setup lines and pin 147. A substantial setup difference can be found comparing the boards of AES and MVS releases. The way the chip access and delivery the graphic data is different between them and both configurations are available inside the NEO-CMC that is configured by the setup of the board itself. So the NEO-CMC is '''interchangeable between boards''' between MVS, AES, and MVH embedded. See the releases at ([[CHAFIO]])
'''NOTE2:''' In case somebody wonders, it's impossible to downgrade or upgrade NEO-CMCs between different versions (from 42 to 50 and vice-versa). The reason is that it's impossible without preparing the game for that and the algorithm to do it is unknown.


Also found on [[ROM-Only boards|ROM-only]] arcade boards, without the "NEO-CMC" marking.
=Pinout=
[[File:Neocmc_7050_7042_pinout.png]]


Notes:
*C_e_D[0-15]: C1/C3/C5/C7 data bus
*C_o_D[0-15]: C2/C4/C6/C8 data bus
*CX A[0-21]: C1/C2/C3/C4/C5/C6/C7/C8 address bus
*Pins 87,88 contains a RC circuit clock driver like in a 8085 with X1 and X2 pinouts
*Pins 89 and 92 are short circuited in Cartridge board.
[[Category:Chips]]
[[Category:Chips]]

Latest revision as of 03:56, 24 November 2024

Package QFP180
Manufacturer
First use 1999 ?
Used on CHAFIO...
File:Brd cmcnoref.jpg
"CMC50"

Late SNK custom chip used for protection, bankswitching and latching on CHAFIO CHA boards.

Descrambling/decryption infos can be found in [MAME:prot_cmc.c]

Versions

This chip is a TC190G series Toshiba ASIC developed between 1990 and 1994. Two versions of the chip are known to exist:

  • TC190G06CF7042
  • TC190G06CF7050

They contain the logic for:

  • NEO-ZMC2
  • NEO-273
  • New scrambling system that interlaces M1 + (C* + S1) to decrypt all the graphics ROMs data in real time (042 version).
  • New scrambling system that interlaces M1 + (C* + S1) to decrypt all the graphics ROMs data and Sound Driver ROM data in real time (050 version).

The first released NEO-MVS CHAFIO PCBs came out with the 042 version of NEO-CMC, on the following cartridges:

On this version only the S1 and C ROMs are encrypted and M1 remains unencrypted. Almost one year later, SNK decided to add one more layer, this time also encrypting M1. This new NEO-CMC chip had the 050 reference and was found in the following cartridges:

Until today, nobody has released a cloned chip on the underground market.

Fix handling

See fix bankswitching.

Encryption

Todo.

Pinout

OpenOffice Draw file: File:Neocmc 7050 7042.odg

Signals: 

CXe_D[0..15]: C odd data bus
CXo_D[0..15]: C even data bus
CX_A[0..21]: C1~8 address bus

Pin : 32 connects to Mitsumi (PST600D) reset generator to re-initialize the NEO-CMC in case of power failure.
Pins: 87 and 88 contains a RC circuit clock driver like in a 8085 with X1 and X2 pinouts
Pins: 89 and 92 are interconnected.
Pin : 94 is configured in:
     NEO-MVS CHAFIO as NC 
     NEO-AEG CHAFIO as 12M
Pin :147 is configured in:
     NEO-MVS CHAFIO (2003.07.24) as M1_CE
     NEO-MVS CHAFIO (1999.06.14) as NC
     NEO-AEG CHAFIO (2003.07.24) as M1_CE
     NEO-AEG CHAFIO (1999.08.10) as NC


Comparing MVS and AES Cartridges vs MVH PCBs: 

Pin :147 is configured in:
     NEO-MVH MVOC   (2003.11.03) as M1_CE (KOF2003 pcb)
     NEO-MVH MVOBR  (2003.08.04) as M1_CE (MSLUG5 pcb)
     NEO-MVS CHAFIO (2003.07.24) as M1_CE
     NEO-AEG CHAFIO (2003.07.24) as M1_CE
     NEO-MVS MVOB   (2003.07.09) as NC    (SVC pcb - fixed by wirewrap)
     NEO-MVS MVO    (2003.06.05) as NC    (SVC pcb) 
     NEO-MVS CHAFIO (1999.06.14) as NC
     NEO-AEG CHAFIO (1999.08.10) as NC

Pin : 152 is configured in:
     NEO-MVH (MVOC) as VCC
     NEO-MVH (MVO, MVOB, MVOBR) as GND
     NEO-MVS (ALL) as GND
     NEO-AEG (ALL) as GND

Final Notes 

NOTE1: There are no pinout differences between NEO-CMC42 and NEO-CMC50 however, differences can be spotted between previous and later board releases with respect to some setup lines and pin 147. A substantial setup difference can be found comparing the boards of AES and MVS releases. The way the chip access and delivery the graphic data is different between them and both configurations are available inside the NEO-CMC that is configured by the setup of the board itself. So the NEO-CMC is interchangeable between boards between MVS, AES, and MVH embedded. See the releases at (CHAFIO)

NOTE2: In case somebody wonders, it's impossible to downgrade or upgrade NEO-CMCs between different versions (from 42 to 50 and vice-versa). The reason is that it's impossible without preparing the game for that and the algorithm to do it is unknown.
Retrieved from "https://wiki.neogeodev.org/index.php?title=NEO-CMC&oldid=8416"