NEO-CMC: Difference between revisions

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[[File:crt_cmc.jpg|thumb|"CMC42" chip on a MVS [[cartridges|cartridge]]. Picture courtesy of [[http://www.mvs-scans.com MVS-Scans]].]]
{{ChipInfo
|picture=crt_cmc.jpg
|pkg=QFP180
|manu=toshiba
|date=1999 ?
|gates=A lot
|used_on={{PCB|CHAFIO}}...
}}


The most "basic" information published can be found at [[http://mamedev.org/source/src/mame/machine/neocrypt.c.html MAME:neocrypt.c]]
[[File:brd_cmcnoref.jpg|thumb|"CMC50"]]


Bellow the detailed information:
Late SNK custom chip used for protection, bankswitching and latching on [[CHAFIO]] [[CHA board]]s.


The NEO-CMC Chip is a Asic (Application Specific Integrated Circuit). This device can be programmed only once after be created severals prototypes until reach the stable condiction, using FPGA (Field Programmable Gate Array).  
Descrambling/decryption infos can be found in [[https://github.com/mamedev/mame/blob/master/src/devices/bus/neogeo/prot_cmc.cpp  MAME:prot_cmc.c]]
The Asci must be considerated a final step from this process.


To get a intuition about costs related, please read this:
==Versions==
[[http://www.design-reuse.com/articles/9010/fpga-s-vs-asic-s.html FPGA vs ASICs production and design]]
This chip is a TC190G series Toshiba ASIC developed between 1990 and 1994. Two versions of the chip are known to exist:


SNK had planned to put his next protection to try avoid NeoGeo piracy using the NEOCMC algorithm.
*TC190G06CF7'''042'''
*TC190G06CF7'''050'''


Because Toshiba was partner and not only made solution to hold data on it's Mask Roms (TC5xxxx), they has used its technology in Asic solutions to help to create this Chip. Until 1995 Toshiba had a line of Asics called TC190G series, the evolution of this series can be found at [[http://www.toshiba-components.com/ASIC/Technology.html Toshiba Technology RoadMap]].
They contain the logic for:
*{{Chipname|NEO-ZMC2}}
*{{Chipname|NEO-273}}
*New scrambling system that interlaces M1 + (C* + S1) to decrypt all the graphics ROMs data in real time (042 version).
*New scrambling system that interlaces M1 + (C* + S1) to decrypt all the graphics ROMs data and Sound Driver ROM data in real time (050 version).


The serie that SNK get advantage to build a valuable chip with it's algorithm to protect Cs and S1 initially was the serie TC190G:
The first released NEO-MVS CHAFIO PCBs came out with the '''042''' version of NEO-CMC, on the following cartridges:
*[[Zupapa!]]
*[[The King of Fighters '99 - Millennium Battle]]
*[[Ganryu]]
*[[Garou - Mark of the Wolves]]
*[[Strikers 1945 Plus]]
*[[Prehistoric Isle 2]]
*[[Metal Slug 3]]
*[[Bang Bead]]
*[[Nightmare in the Dark]]
*[[Sengoku 3]]


The series TC190G cannot be found in datasheets anymore, but in past years had these models:
On this version only the [[S ROM|S1]] and [[C ROM]]s are encrypted and M1 remains unencrypted. Almost one year later, SNK decided to add one more layer, this time also encrypting M1. This new NEO-CMC chip had the '''050''' reference and was found in the following cartridges:
*TC190G06CF7008
*[[Jockey Grand Prix]]
*TC1'''90G06CF7042'''
*[[The King of Fighters 2000]]
*TC1'''90G06CF7050'''
*[[The King of Fighters 2001]]
and more...
*[[Metal Slug 4]]
*[[Rage of the Dragons]]
*[[The King of Fighters 2002]]
*[[Matrimelee]]
*[[Pochi and Nyaa]]
*[[Metal Slug 5]]
*[[SNK vs. Capcom - SVC Chaos]]
*[[Samurai Shodown V]]
*[[The King of Fighters 2003]]
*[[Samurai Shodown V Special]]


Apparently the last two models was used because the number of internal number of gates acceptable to the logic SNK have developed:
To this day, no one has produced a reproduction of these chips.
*NEO-ZMC
*NEO-273
*And a new scrambling system for that interlaces M1 + (CX + S1) ROM data


inicially the released model of CMC was '''NEO-CMC42''' on the following cartridges:
==Fix handling==
{|
|'''CART ID'''
|'''TITLE NAME'''
|-
|070
|Zupapa
|-
|251
|King Of Fighters 99
|-
|252
|Ganryu
|-
|253
|Garou Mark Of the Wolves
|-
|254
|Strikers 1945
|-
|255
|Prehistoric Isle 2
|-
|256
|Metal Slug 3
|-
|259
|Bang Bead
|-
|260
|Nightmare in the Dark
|-
|261
|Sengoku 3
|-
|}


This version had only S1 and CRoms Encrypted and M1 remained in normal condition (unencrypted)
See [[fix bankswitching]].


This was just a "test", to see if SNK and Toshiba could be more further in protection.
==Encryption==


Almost one year later SNK decided release one more layer on the algorithm, to encrypt M1 on the mixer.
Todo.
So they released the model NEO-CMC50 on the following cartridges:
{|
|'''CART ID'''
|'''TITLE NAME'''
|-
|008
|Jockey Grand Prix
|-
|257
|King Of Figthers 2000
|-
|262
|King Of Figthers 2001
|-
|263
|Metal Slug 4
|-
|264
|Rage of the Dragons
|-
|265
|King Of Fighters 2002
|-
|266
|Power Instinct - Matrimele
|-
|267
|Pochi to Nyaa
|-
|268
|Metal Slug 5
|-
|269
|SNK vs Capcom Chaos
|-
|270
|Samurai Showdown Zero / Samurai Showdown 5
|-
|271
|King of Fighters 2003
|-
|272
|Samurai Showdown Zero Special / Samurai Showdown 5 Special
|-
|}
About Jockey Gran Prix, some peoples say this game is not official release but it´s not true.
At least its production of the card is official, because they had used the REAL Encryption that cannot be mocked easly.
Only the Toshiba and SNK knew the encryption and until today "NO ONE" piracy goes so forensic to mock it.
Explanation Later.


=Pinout=
[[File:Neocmc_7050_7042_pinout.png|x600px]]


OpenOffice Draw file: [[File:Neocmc_7050_7042.odg]]


[[File:brd_cmcnoref.jpg|thumb|"CMC50"]]
'''Signals:'''
CXe_D[0..15]: C odd data bus
CXo_D[0..15]: C even data bus
CX_A[0..21]: C1~8 address bus (NEO-MVS & NEO-AEG)
CX_A[0..'''22''']: C1~4 address bus ('''NEO-MVH only''')
Pin : 32 connects to Mitsumi (PST600D) reset generator to re-initialize the NEO-CMC in case of power failure.
Pins: 87 and 88 contains a RC circuit clock driver like in a 8085 with X1 and X2 pinouts
Pins: 89 and 92 are interconnected.
-----------------------------------------------
Pins: 62~69, 71~78, 80~84 are configured in:
      '''NEO-MVS CHAFIO''' as '''CR31~CR24, CR23~CR16, CR15~CR11''' respectively
      NEO-AEG CHAFIO as '''  NC~NC  ,  NC~NC  ,  NC~NC'''
-----------------------------------------------
Pins: 102, 103~106, 107~110, 112~113 are configured in:
      '''NEO-MVS CHAFIO''' as '''CR10, CR9~CR6 ,  CR5~CR2 ,  CR1~CR0'''
      NEO-AEG CHAFIO as '''NC  ,GBD3~GBD0, GAD3~GAD0, DOTB~DOTA'''
-----------------------------------------------
Pin : 94 is configured in:
      '''NEO-MVS CHAFIO''' as '''NC '''
      NEO-AEG CHAFIO as '''12M'''
-----------------------------------------------
Pin :147 is configured in:
      '''NEO-MVS CHAFIO''' (2003.07.24) as M1_CE
      '''NEO-MVS CHAFIO''' (1999.06.14) as NC
      NEO-AEG CHAFIO (2003.07.24) as M1_CE
      NEO-AEG CHAFIO (1999.08.10) as NC
-----------------------------------------------
Pin :153 is configured in:
      NEO-MVS (ALL) as '''VCC'''
      NEO-AEG (ALL) as GND
 
'''Comparing MVH PCBs vs MVS & AES Cartridges'''
Pin :147 is configured in:
      '''NEO-MVH MVOC  (2003.11.03)''' as '''M1_CE''' (KOF2003 pcb)
      '''NEO-MVH MVOBR  (2003.08.04)''' as '''M1_CE''' (MSLUG5 pcb)
      '''NEO-MVH MVOB  (2003.07.09)''' as '''NC  ''' (SVC pcb) - '''M1_CE (fixed by wirewrapps)'''
      '''NEO-MVH MVO    (2003.06.05)''' as '''NC  ''' (SVC pcb)
      NEO-MVS CHAFIO (2003.07.24) as M1_CE
      NEO-MVS CHAFIO (1999.06.14) as NC
      NEO-AEG CHAFIO (2003.07.24) as M1_CE
      NEO-AEG CHAFIO (1999.08.10) as NC
-----------------------------------------------
Pin :152 is configured in:
      '''NEO-MVH (MVOC)''' as '''VCC'''
      '''NEO-MVH (MVO, MVOB, MVOBR)''' as '''GND'''
      NEO-MVS (ALL) as GND
      NEO-AEG (ALL) as GND
-----------------------------------------------
Pin :153 is configured in:
      '''NEO-MVH (ALL)''' as '''VCC'''
      NEO-MVS (ALL) as '''VCC'''
      NEO-AEG (ALL) as GND
-----------------------------------------------
Pin :154 is configured in:
      '''NEO-MVH (MVO, MVOB, MVOBR, MVOC)''' as '''C2C1_OE'''
      NEO-MVS (ALL) as NC
      NEO-AEG (ALL) as NC
-----------------------------------------------
Pin :155 is configured in:
      '''NEO-MVH (MVO, MVOB, MVOBR, MVOC)''' as '''C4C3_OE'''
      NEO-MVS (ALL) as NC
      NEO-AEG (ALL) as NC
-----------------------------------------------
Pin :158 is configured in:
      '''NEO-MVH (MVO, MVOB, MVOBR, MVOC)''' as '''NC'''
      NEO-MVS (ALL) as C8C7_OE
      NEO-AEG (ALL) as C8C7_OE
-----------------------------------------------
Pin :159 is configured in:
      '''NEO-MVH (MVO, MVOB, MVOBR)''' as '''NC'''
      '''NEO-MVH (MVOC)''' as '''C6C5_OE'''
      NEO-MVS (ALL) as '''C6C5_OE'''
      NEO-AEG (ALL) as '''C6C5_OE'''
-----------------------------------------------
Pin :160 is configured in:
      '''NEO-MVH (MVO, MVOB, MVOBR)''' as '''NC'''
      '''NEO-MVH (MVOC)''' as '''C4C3_OE'''
      NEO-MVS (ALL) as '''C4C3_OE'''
      NEO-AEG (ALL) as '''C4C3_OE'''
-----------------------------------------------
Pin :161 is configured in:
      '''NEO-MVH (MVO, MVOB, MVOBR)''' as '''NC'''
      '''NEO-MVH (MVOC)''' as '''C2C1_OE'''
      NEO-MVS (ALL) as '''C2C1_OE'''
      NEO-AEG (ALL) as '''C2C1_OE'''
-----------------------------------------------
Pin :189 is configured in:
      '''NEO-MVH (MVO, MVOB, MVOBR, MVOC)''' as '''A22''' (128Mbit) (connected from CMC to the driver input and from output to C ROM's A22)
      NEO-MVS (ALL) as NC
      NEO-AEG (ALL) as NC
-----------------------------------------------
Pin :190 is connected from CMC to the driver input, but NC from it's output:
      '''NEO-MVH (MVO, MVOB, MVOBR, MVOC)''' as A23 (256Mbit) ('''assumption''' it's prepared for big size C ROMs )
      NEO-MVS (ALL) as NC
      NEO-AEG (ALL) as NC
-----------------------------------------------
Pin :191 is connected from CMC to the driver input, but NC from it's output:
      '''NEO-MVH (MVO, MVOB, MVOBR, MVOC)''' as A24 (512Mbit) ('''assumption''' it's prepared for big size C ROMs)
      NEO-MVS (ALL) as NC
      NEO-AEG (ALL) as NC


Also found on [[ROM-Only boards|ROM-only]] arcade boards, without the "NEO-CMC" marking.
'''Final Notes'''
=Pinout=
'''NOTE1:''' There are no pinout differences between NEO-CMC42 and NEO-CMC50 however, differences can be spotted between previous and later board releases with respect to some setup lines and pin 147. A substantial setup difference can be found comparing the boards of AES and MVS releases. The way the chip access and delivery the graphic data is different between them and both configurations are available inside the NEO-CMC that is configured by the setup of the board itself. So the NEO-CMC is '''interchangeable between boards''' between MVS, AES, and MVH embedded. See the releases at ([[CHAFIO]])
[[File:Neocmc_7050_7042_pinout.png]]
'''NOTE2:''' In case somebody wonders, it's impossible to downgrade or upgrade NEO-CMCs between different versions (from 42 to 50 and vice-versa). The reason is that it's impossible without preparing the game for that and the algorithm to do it is unknown.
'''NOTE3:''' In MVH with embedded CHAFIO the NEO-CMC50 (pin 147 as M1_CE) is native present on the follow releases: 2003.08.04 (MSLUG 5) and 2003.11.03 (KOF2003). However on releases 2003.06.05 and 2003.07.09, both from SVCChaos (set1 and set2), that pin is natively configured as NC, but artificially fixed on set2 by wirewraps.
'''NOTE4:''' In MVH release '''2003.11.03 (KOF2003) only''', there is one configuration change that not appear in any other board AES, MVS or MVH. '''The pin 152 is connected to VCC'''. This require further investigation to check what's being switched. Perhaps from 64mbits to 128Mbits?
'''NOTE5:''' In MVH (ALL) the pins:
        189 is connected to through buffer driver to A22 (128Mbit),
        190 and 191 are pre-connected to the buffer drivers and left as NCs from there.
        The assumption here is that the CMC is ready for bigger C Roms (256Mbit and 512Mbit).  
        Question: Would be easy left them shorted to VCC or GND. Why make parallel tracks without necessity?).


Notes:
*C_e_D[0-15]: C1/C3/C5/C7 data bus
*C_o_D[0-15]: C2/C4/C6/C8 data bus
*CX A[0-21]: C1/C2/C3/C4/C5/C6/C7/C8 address bus
*Pins 87,88 contains a RC circuit clock driver like in a 8085 with X1 and X2 pinouts
*Pins 89 and 92 are short circuited in Cartridge board.
[[Category:Chips]]
[[Category:Chips]]

Latest revision as of 05:42, 3 January 2025

Package QFP180
Manufacturer
First use 1999 ?
Used on CHAFIO...
File:Brd cmcnoref.jpg
"CMC50"

Late SNK custom chip used for protection, bankswitching and latching on CHAFIO CHA boards.

Descrambling/decryption infos can be found in [MAME:prot_cmc.c]

Versions

This chip is a TC190G series Toshiba ASIC developed between 1990 and 1994. Two versions of the chip are known to exist:

  • TC190G06CF7042
  • TC190G06CF7050

They contain the logic for:

  • NEO-ZMC2
  • NEO-273
  • New scrambling system that interlaces M1 + (C* + S1) to decrypt all the graphics ROMs data in real time (042 version).
  • New scrambling system that interlaces M1 + (C* + S1) to decrypt all the graphics ROMs data and Sound Driver ROM data in real time (050 version).

The first released NEO-MVS CHAFIO PCBs came out with the 042 version of NEO-CMC, on the following cartridges:

On this version only the S1 and C ROMs are encrypted and M1 remains unencrypted. Almost one year later, SNK decided to add one more layer, this time also encrypting M1. This new NEO-CMC chip had the 050 reference and was found in the following cartridges:

To this day, no one has produced a reproduction of these chips.

Fix handling

See fix bankswitching.

Encryption

Todo.

Pinout

OpenOffice Draw file: File:Neocmc 7050 7042.odg

Signals: 

CXe_D[0..15]: C odd data bus
CXo_D[0..15]: C even data bus
CX_A[0..21]: C1~8 address bus (NEO-MVS & NEO-AEG)
CX_A[0..22]: C1~4 address bus (NEO-MVH only)

Pin : 32 connects to Mitsumi (PST600D) reset generator to re-initialize the NEO-CMC in case of power failure.
Pins: 87 and 88 contains a RC circuit clock driver like in a 8085 with X1 and X2 pinouts
Pins: 89 and 92 are interconnected.
-----------------------------------------------
Pins: 62~69, 71~78, 80~84 are configured in:
     NEO-MVS CHAFIO as CR31~CR24, CR23~CR16, CR15~CR11 respectively
     NEO-AEG CHAFIO as   NC~NC  ,   NC~NC  ,   NC~NC
-----------------------------------------------
Pins: 102, 103~106, 107~110, 112~113 are configured in:
     NEO-MVS CHAFIO as CR10, CR9~CR6 ,  CR5~CR2 ,  CR1~CR0
     NEO-AEG CHAFIO as NC  ,GBD3~GBD0, GAD3~GAD0, DOTB~DOTA
-----------------------------------------------
Pin : 94 is configured in:
     NEO-MVS CHAFIO as NC 
     NEO-AEG CHAFIO as 12M
-----------------------------------------------
Pin :147 is configured in:
     NEO-MVS CHAFIO (2003.07.24) as M1_CE
     NEO-MVS CHAFIO (1999.06.14) as NC
     NEO-AEG CHAFIO (2003.07.24) as M1_CE
     NEO-AEG CHAFIO (1999.08.10) as NC
-----------------------------------------------
Pin :153 is configured in:
     NEO-MVS (ALL) as VCC
     NEO-AEG (ALL) as GND

Comparing MVH PCBs vs MVS & AES Cartridges 

Pin :147 is configured in:
     NEO-MVH MVOC   (2003.11.03) as M1_CE (KOF2003 pcb)
     NEO-MVH MVOBR  (2003.08.04) as M1_CE (MSLUG5 pcb)
     NEO-MVH MVOB   (2003.07.09) as NC    (SVC pcb) - M1_CE (fixed by wirewrapps)
     NEO-MVH MVO    (2003.06.05) as NC    (SVC pcb) 
     NEO-MVS CHAFIO (2003.07.24) as M1_CE
     NEO-MVS CHAFIO (1999.06.14) as NC
     NEO-AEG CHAFIO (2003.07.24) as M1_CE
     NEO-AEG CHAFIO (1999.08.10) as NC
-----------------------------------------------
Pin :152 is configured in:
     NEO-MVH (MVOC) as VCC
     NEO-MVH (MVO, MVOB, MVOBR) as GND
     NEO-MVS (ALL) as GND
     NEO-AEG (ALL) as GND
-----------------------------------------------
Pin :153 is configured in:
     NEO-MVH (ALL) as VCC
     NEO-MVS (ALL) as VCC
     NEO-AEG (ALL) as GND
-----------------------------------------------
Pin :154 is configured in:
     NEO-MVH (MVO, MVOB, MVOBR, MVOC) as C2C1_OE
     NEO-MVS (ALL) as NC
     NEO-AEG (ALL) as NC
-----------------------------------------------
Pin :155 is configured in:
     NEO-MVH (MVO, MVOB, MVOBR, MVOC) as C4C3_OE
     NEO-MVS (ALL) as NC
     NEO-AEG (ALL) as NC
-----------------------------------------------
Pin :158 is configured in:
     NEO-MVH (MVO, MVOB, MVOBR, MVOC) as NC
     NEO-MVS (ALL) as C8C7_OE
     NEO-AEG (ALL) as C8C7_OE
-----------------------------------------------
Pin :159 is configured in:
     NEO-MVH (MVO, MVOB, MVOBR) as NC
     NEO-MVH (MVOC) as C6C5_OE
     NEO-MVS (ALL) as C6C5_OE
     NEO-AEG (ALL) as C6C5_OE
-----------------------------------------------
Pin :160 is configured in:
     NEO-MVH (MVO, MVOB, MVOBR) as NC
     NEO-MVH (MVOC) as C4C3_OE
     NEO-MVS (ALL) as C4C3_OE
     NEO-AEG (ALL) as C4C3_OE
-----------------------------------------------
Pin :161 is configured in:
     NEO-MVH (MVO, MVOB, MVOBR) as NC
     NEO-MVH (MVOC) as C2C1_OE
     NEO-MVS (ALL) as C2C1_OE
     NEO-AEG (ALL) as C2C1_OE
-----------------------------------------------
Pin :189 is configured in:
     NEO-MVH (MVO, MVOB, MVOBR, MVOC) as A22 (128Mbit) (connected from CMC to the driver input and from output to C ROM's A22)
     NEO-MVS (ALL) as NC
     NEO-AEG (ALL) as NC
-----------------------------------------------
Pin :190 is connected from CMC to the driver input, but NC from it's output:
     NEO-MVH (MVO, MVOB, MVOBR, MVOC) as A23 (256Mbit) (assumption it's prepared for big size C ROMs )
     NEO-MVS (ALL) as NC
     NEO-AEG (ALL) as NC
-----------------------------------------------
Pin :191 is connected from CMC to the driver input, but NC from it's output:
     NEO-MVH (MVO, MVOB, MVOBR, MVOC) as A24 (512Mbit) (assumption it's prepared for big size C ROMs)
     NEO-MVS (ALL) as NC
     NEO-AEG (ALL) as NC

Final Notes 

NOTE1: There are no pinout differences between NEO-CMC42 and NEO-CMC50 however, differences can be spotted between previous and later board releases with respect to some setup lines and pin 147. A substantial setup difference can be found comparing the boards of AES and MVS releases. The way the chip access and delivery the graphic data is different between them and both configurations are available inside the NEO-CMC that is configured by the setup of the board itself. So the NEO-CMC is interchangeable between boards between MVS, AES, and MVH embedded. See the releases at (CHAFIO)

NOTE2: In case somebody wonders, it's impossible to downgrade or upgrade NEO-CMCs between different versions (from 42 to 50 and vice-versa). The reason is that it's impossible without preparing the game for that and the algorithm to do it is unknown.

NOTE3: In MVH with embedded CHAFIO the NEO-CMC50 (pin 147 as M1_CE) is native present on the follow releases: 2003.08.04 (MSLUG 5) and 2003.11.03 (KOF2003). However on releases 2003.06.05 and 2003.07.09, both from SVCChaos (set1 and set2), that pin is natively configured as NC, but artificially fixed on set2 by wirewraps.

NOTE4: In MVH release 2003.11.03 (KOF2003) only, there is one configuration change that not appear in any other board AES, MVS or MVH. The pin 152 is connected to VCC. This require further investigation to check what's being switched. Perhaps from 64mbits to 128Mbits?

NOTE5: In MVH (ALL) the pins: 
       189 is connected to through buffer driver to A22 (128Mbit), 
       190 and 191 are pre-connected to the buffer drivers and left as NCs from there. 
       The assumption here is that the CMC is ready for bigger C Roms (256Mbit and 512Mbit). 
       Question: Would be easy left them shorted to VCC or GND. Why make parallel tracks without necessity?).
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