Latest revision as of 18:31, 17 January 2024


Package	QFP80R
Manufacturer
First use	1994 ?
Used on	MV1FZS Cartridges...

NEO-ZMC and PRO-CT0 in one package.

Can address up to 4MiB of M1 ROM.

Found in second revision MVS boards (for the PRO-CT0 logic only), and AES cartridges.

Pinout

Edit this pinout

NEO-ZMC part:

SDA0,SDA1,SDA8~SDA15: Z80 address bus
MA11~MA21: M ROM address outputs

PRO-CT0 part, inputs:

12M: 12MHz clock, outputs next pixel on falling edge.
C0~C31: C ROM data bus (2*16 bits). Gives all the pixel data needed for a 8 pixel line.
H: When high, reverse bit order of pixels shifted out (used for sprites horizontal flipping)
EVEN: Swap A/B pixels.
LOAD: Latch C ROM data on rising edge of 12M.

Outputs:

DOTA: High when pixel A is opaque (color > 0)
DOTB: High when pixel B is opaque (color > 0)
GAD0~GAD3: Pixel A color index
GBD0~GBD3: Pixel B color index

@@ Line 1: / Line 1: @@
-[[File:mvs_zmc2.jpg|right|thumb|NEO-ZMC2 chip found on a 1FZS MVS board.]]
+{{ChipInfo
+|picture=mvs_zmc2.jpg
+|pkg=QFP80R
+|manu=fujitsu
+|date=1994 ?
+|gates=
+|used_on={{PCB|MV1FZS}} [[Cartridges]]...
+}}
-[[NEO-ZMC]] and [[PRO-CT0]] in one package. The PRO-CT0 is a network of shift registers and multiplexers (32-bit [[C ROM]] bus to two [[sprite graphics format|4 bpp]] pixel outputs).
+{{Chipname|NEO-ZMC}} and {{Chipname|PRO-CT0}} in one package.
-Found in second revision MVS boards (for the PRO-CT0 logic only) and AES carts.
+Can address up to 4MiB of [[M1 ROM]].
-== Pinout ==
+Found in second revision [[MVS hardware|MVS]] boards (for the PRO-CT0 logic only), and AES cartridges.
-[[File:Neo-zmc2 pinout.png]]
+=Pinout=
-OpenOffice Draw file: [[File:neo-zmc2.odg]]
+{{Pinout|NEO-ZMC2|640px}}
 NEO-ZMC part:
-*A0,A1,A8~A15: [[Z80]] address bus
+*SDA0,SDA1,SDA8~SDA15: [[Z80]] address bus
-*MA11~M21: M ROM address outputs (NEO-ZMC part)
+*MA11~MA21: M ROM address outputs
-PRO-CT0 part:
+PRO-CT0 part, inputs:
-*12M: Input, 12MHz clock, outputs next pixel on falling edge
+*12M: 12MHz clock, outputs next pixel on falling edge.
-*GAD0~GAD3: Outputs, pixel A color data
+*C0~C31: C ROM data bus (2*16 bits). Gives all the pixel data needed for a 8 pixel line.
-*GBD0~GBD3: Outputs, pixel B color data
+*H: When high, reverse bit order of pixels shifted out (used for [[sprites]] horizontal flipping)
-*LOAD: Input, latch C ROM data (on rising edge ?)
+*EVEN: Swap A/B pixels.
-*C0~C31: Inputs, C ROM data bus (2*16 bits). Gives all the pixel data needed for a 8 pixel line.
+*LOAD: Latch C ROM data on rising edge of 12M.
-*H: Input, when high, reverse bit order of pixels (used for [[sprites]] horizontal flipping)
+Outputs:
-*DOTA: Output, high when pixel A is opaque
+*DOTA: High when pixel A is opaque (color > 0)
-*DOTB: Output, high when pixel B is opaque
+*DOTB: High when pixel B is opaque (color > 0)
+*GAD0~GAD3: Pixel A color index
+*GBD0~GBD3: Pixel B color index
 [[Category:Chips]]

NEO-ZMC2: Difference between revisions

Latest revision as of 18:31, 17 January 2024

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