CD drive: Difference between revisions

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[[File:Cd2_cdboard1.jpg|thumb|right|CD2 CD drive board.]]
[[File:Cd2_cdboard1.jpg|thumb|right|Top-loading drive control board.]]


Or "CD drive". The part that fails before everything else in [[CD systems]]. Also see [[optical pickups]].
The part that makes you wait and fails in [[CD systems]]. The ones used in the NeoGeo consoles are very similar to those found in the Sega CD. They're basically enhanced audio CD drives, which are also able to read CD-ROM data tracks.
 
Made of a control board and an [[optical pickups|optical pickup]].


The NeoGeo CD top-loading model drive was made by Sony. The [[CDZ]] one was made by Sharp ?
The NeoGeo CD top-loading model drive was made by Sony. The [[CDZ]] one was made by Sharp ?


It is made of:
The control board has:
* A 4-bit MPU (CXP5084), taking care of sequencing and communication (command execution and status report)
* A 4-bit mask ROM MCU (Sony CXP5084), taking care of operation sequencing and communication with the NeoGeo.
* A DSP (CXD2500) to process analog data from the pickup
* A DSP (Sony CXD2500) to process analog data from the pickup.
* A servo controler (CXA1372) to drive the pickup coils for tracking and focus
* A servo controler (Sony CXA1372) to drive the pickup coils for tracking and focus.
* A spindle motor driver (Rohm BA6396)
* A spindle, sled (and tray) motor driver.
 
=Connections=


==Communication==
Some say the protocol was standard for the time, but clear information is hard to find. This was guessed from the [[system ROM]] disassembly, Sega CD documents and a logic analyzer.


Some say the protocol was "standard" for the time, but clear information is hard to find. This was guessed from the system ROM disassembly and confirmed with a logic analyzer.
==Top-loading model==


Mobo connector pinout:
Connector pinout, directions are from CDD (CD Drive) to CDC (CD Controller):


*1 CDCK (CD drive clock output)
{| class="regdef"
*2 High (?)
|'''Pin #'''
*3 IRQ (output)
|'''Name'''
*4 High (?)
|'''Type'''
*5 HOCK (Host clock input)
|'''Direction'''
*6 D0
|'''Description'''
*7 D1
|-
*8 D2
| 1
*9 D3
| CDCK
*10 ?
| Clock
*11 2.12MHz ? BCLK ?
| Output
*12 SDATA
| Communication clock to CDC
*13 LRCK (for audio)
|-
*14 High (Mute ?)
| 2
*15 Ground
| ?
*16 Logic power (5V)
| ?
*17 Motor power (voltage ?)
| ?
*18 Ground
| High ?
|-
| 3
| /IRQ
| Signal
| Output
| Asks the CDC for a data exchange (low pulse at ~64Hz)
|-
| 4
| ?
| ?
| ?
| High ?
|-
| 5
| HOCK
| Clock
| Input
| Communication clock from CDC
|-
| 6
| rowspan="4" | D0~3
| rowspan="4" | Data
| rowspan="4" | Both
| rowspan="4" | 4-bit command/status data bus
|-
| 7
|-
| 8
|-
| 9
|-
| 10
| ?
| ?
| ?
| ?
|-
| 11
| BCLK?
| Clock
| Output
| Serial bit clock, should be 44100 * 32 = 1.4112MHz
|-
| 12
| SDATA
| Data
| Output
| Serial data
|-
| 13
| LRCK
| Signal
| Output
| I2S word clock, should be 44100Hz. Audio L/R switch for the DAC.
|-
| 14
| D/M ?
| Signal
| Output
| Data/Music. Low during music playback ?
|-
| 15
| GND
| Power
| -
| Ground
|-
| 16
| 5V
| Power
| -
| +5V for logic
|-
| 17
| 9V
| Power
| -
| +9V for motors and coils
|-
| 18
| GND
| Power
| -
| Ground
|}


Some signal has to be "D/M", an output which indicates if SDATA is audio or data.
Missing: /RESET, C2PO, and 16MHz.


Done through [[NEO-MGA]] on a 4-bit bi-directional bus.
==Front-loading model==


[[File:Cdunit4bit.png]]
Connector pinout, directions are from CDD (CD Drive) to CDC (CD Controller):


More infos to come...
{| class="regdef"
|'''Pin #'''
|'''Name'''
|'''Type'''
|'''Direction'''
|'''Description'''
|-
| 1
| SGND
| Power
| -
| Ground
|-
| 2
| SVCC
| Power
| -
|
|-
| 3
| VCC
| Power
| -
|
|-
| 4
| WFCK
| Clock
| Output
| Write Frame Clock
|-
| 5
| GND
| Power
| -
| Ground
|-
| 6
| SCOR
| Pulse
| Output
| Subcode sync
|-
| 7
| MUTE
| ?
|
|
|-
| 8
| SBSO
| Data
| Output
| Subcode data
|-
| 9
| EXCK
| Clock
| Input
| Subcode clock
|-
| 10
| EMP
| ?
| ?
| EMPty ?
|-
| 11
| DOUT
| Data
| Output
| ?
|-
| 12
| 6MHz
| Clock
| ?
| ?
|-
| 13
| LRCK
| Clock
| Output
| DATA L or R channel (44100Hz)
|-
| 14
| DATA
| Data
| ?
| Data stream
|-
| 15
| BCLK
| Clock
| Output
| DATA bit clock (44100 * 24 * 2 = 2.12MHz)
|-
| 16
| C2PO
| Data
| Output
| Error flag
|-
| 17
| rowspan="4" | DB0~3
| rowspan="4" | Data
| rowspan="4" | Both
| rowspan="4" | 4-bit command/status data bus
|-
| 18
|-
| 19
|-
| 20
|-
| 21
| HOCK
| Clock
| Input
| Communication clock from CDC
|-
| 22
| RESET
| Pulse
| Input
| The name says it all
|-
| 23
| /IRQ
| Signal
| Output
| Asks the CDC for a data exchange
|-
| 24
| L-MUTE
| ?
|
|
|-
| 25
| CDCK
| Clock
| Output
| Communication clock to CDC
|}


==Adjustments==
==Adjustment pots==


To do !
To do !


[[Category:Chips]]
[[Category:Chips]]
[[Category:Repairs]]
[[Category:CD systems]]
[[Category:CD systems]]

Latest revision as of 18:48, 22 June 2019

File:Cd2 cdboard1.jpg
Top-loading drive control board.

The part that makes you wait and fails in CD systems. The ones used in the NeoGeo consoles are very similar to those found in the Sega CD. They're basically enhanced audio CD drives, which are also able to read CD-ROM data tracks.

Made of a control board and an optical pickup.

The NeoGeo CD top-loading model drive was made by Sony. The CDZ one was made by Sharp ?

The control board has:

  • A 4-bit mask ROM MCU (Sony CXP5084), taking care of operation sequencing and communication with the NeoGeo.
  • A DSP (Sony CXD2500) to process analog data from the pickup.
  • A servo controler (Sony CXA1372) to drive the pickup coils for tracking and focus.
  • A spindle, sled (and tray) motor driver.

Connections

Some say the protocol was standard for the time, but clear information is hard to find. This was guessed from the system ROM disassembly, Sega CD documents and a logic analyzer.

Top-loading model

Connector pinout, directions are from CDD (CD Drive) to CDC (CD Controller):

Pin # Name Type Direction Description
1 CDCK Clock Output Communication clock to CDC
2 ? ? ? High ?
3 /IRQ Signal Output Asks the CDC for a data exchange (low pulse at ~64Hz)
4 ? ? ? High ?
5 HOCK Clock Input Communication clock from CDC
6 D0~3 Data Both 4-bit command/status data bus
7
8
9
10 ? ? ? ?
11 BCLK? Clock Output Serial bit clock, should be 44100 * 32 = 1.4112MHz
12 SDATA Data Output Serial data
13 LRCK Signal Output I2S word clock, should be 44100Hz. Audio L/R switch for the DAC.
14 D/M ? Signal Output Data/Music. Low during music playback ?
15 GND Power - Ground
16 5V Power - +5V for logic
17 9V Power - +9V for motors and coils
18 GND Power - Ground

Missing: /RESET, C2PO, and 16MHz.

Front-loading model

Connector pinout, directions are from CDD (CD Drive) to CDC (CD Controller):

Pin # Name Type Direction Description
1 SGND Power - Ground
2 SVCC Power -
3 VCC Power -
4 WFCK Clock Output Write Frame Clock
5 GND Power - Ground
6 SCOR Pulse Output Subcode sync
7 MUTE ?
8 SBSO Data Output Subcode data
9 EXCK Clock Input Subcode clock
10 EMP ? ? EMPty ?
11 DOUT Data Output ?
12 6MHz Clock ? ?
13 LRCK Clock Output DATA L or R channel (44100Hz)
14 DATA Data ? Data stream
15 BCLK Clock Output DATA bit clock (44100 * 24 * 2 = 2.12MHz)
16 C2PO Data Output Error flag
17 DB0~3 Data Both 4-bit command/status data bus
18
19
20
21 HOCK Clock Input Communication clock from CDC
22 RESET Pulse Input The name says it all
23 /IRQ Signal Output Asks the CDC for a data exchange
24 L-MUTE ?
25 CDCK Clock Output Communication clock to CDC

Adjustment pots

To do !

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