NEO-I0: Difference between revisions
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[[File:neo-i0.jpg|right|thumb|NEO-I0 chip found on a [[MV2B]] MVS board.]] | |||
MVS specific chip that does a bunch of unrelated things. | MVS specific chip that does a bunch of unrelated things. | ||
Revision as of 12:47, 19 July 2012
MVS specific chip that does a bunch of unrelated things.
- S ROM address latch for SFIX, same as S ROM portion of NEO-273
- SM1 /CS output when Z80 is reading from ROM and SM1/SFIX is enabled (SM1CS = SDROM OR SYSTEM)
- /ROMOE output for PROG board (ROMOE = ROMOEU AND ROMEOU)
- Video sync output for JAMMA edge
- Coin counter and coin lockout output
Pinout
OpenOffice Draw file: File:Neo-i0.odg
- P0~P15: GPU multiplexed bus.
On a MV1F slot:
- Q00~Q18 are connected to the SFIX ROM address lines.
- SM1CS(ORO0) = SYSTEM(ORI0) OR SDROM(ORI1)
- SYNCOUT = SYNCIN XOR SYNCREV ?
- Q21,Q22:METER1,METER2
- Q23,Q24:LOCK1,LOCK2