NEO-E0: Difference between revisions
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[[File:aes_e0.jpg|right|thumb|NEO-E0 chip found on a AES board.]] | [[File:aes_e0.jpg|right|thumb|NEO-E0 chip found on a AES board.]] | ||
MVS specific chip. | |||
==BIOS vector table swapping== | ==BIOS vector table swapping== | ||
When 68k A8~A23 = 0 and the [[BIOSes|BIOS]]'s vector table is chosen (by using {{Reg|REG_SWPBIOS}} or {{Reg|REG_SWPROM}}), A22I~A23I outputs are set to 1. This makes the address appear to address decoding chips as a BIOS access instead of a [[P ROM]] access. | When 68k A8~A23 = 0 and the [[BIOSes|BIOS]]'s vector table is chosen (by using {{Reg|REG_SWPBIOS}} or {{Reg|REG_SWPROM}}), A22I~A23I outputs are set to 1. This makes the address appear to address decoding chips as a BIOS access instead of a [[P ROM]] access. | ||
On the AES, the AND gate is used for /SROMOE from /SROMOEL AND /SROMOEU. | |||
On AES | |||
==MV2B @ G2 pinout== | ==MV2B @ G2 pinout== |
Revision as of 04:56, 14 August 2012
MVS specific chip.
BIOS vector table swapping
When 68k A8~A23 = 0 and the BIOS's vector table is chosen (by using REG_SWPBIOS or REG_SWPROM), A22I~A23I outputs are set to 1. This makes the address appear to address decoding chips as a BIOS access instead of a P ROM access.
On the AES, the AND gate is used for /SROMOE from /SROMOEL AND /SROMOEU.
MV2B @ G2 pinout
OpenOffice Draw file: File:Neo-e0 mv2b G2.odg |
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MV2B @ F7 pinout
OpenOffice Draw file: File:Neo-e0 mv2b F7.odg |
Acts just as a buffer.
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Pinout
OpenOffice Draw file: File:Neo-e0.odg |
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