MVS to AES adapter: Difference between revisions
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Revision as of 03:30, 13 September 2012
See Open hardware MVS converter.
NEO TEAM Super MVS Converter II PLUS V7
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Prog board top
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Prog board bottom
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CHA board top
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CHA board bottom
Uses an Actel ProASIC V3 FPGA on each board. They're AES-decryption capable for SPI flash and fusemap update, and generally highly temper-proof.
Has two SPI ports for FPGA updates and one unrouted mini-USB port labelled "BIOS".
Boards dated May 2011. Seems to suffer of very bad soldering job on connectors.
NEO TEAM Super MVS Convertor II V5B
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Prog board top
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Prog board bottom
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CHA board top
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CHA board bottom
Uses a PAL18CV8 and two LS245 transceivers for the prog board. Two corresponding footprints for SIL pull-up resistors on the MVS side are left unpopulated.
Uses a custom chip "NEO CELL KS300 8436020333002 06-03" to simulate NEO-ZMC2. An RC circuit (potentiometer) is used for EVEN delay to make CMC games work correctly.
According to [these pictures], the chip would be a custom branded Altera MAX PLD. It's in fact en EPM240D (Boundary scan device ID reply with bus pirate: BB085040, reversed !) and the header on the back is for JTAG:
| TMS | TDO | GND |
| TDI | TCK | 3.3V |