YM2610 bus timing: Difference between revisions

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[[File:Ym2610timing.png|800px]]
==ADPCM-A bus==
[[File:Adpcm-a_timing.png]]


== ADPCM-A ROM access ==
Access to the [[ADPCM]]-A [[V ROM|ROMs]] for each channel is done sequentialy (in the channels order ?). A ~667kHz clock is derived from the {{Chipname|YM2610}}'s 8MHz [[clock]] by dividing it by 12.
The access to the [[V ROM]]s are done sequentialy (in the channels order ?). A 666kHz clock is derived from the 8MHz main clock by dividing it by 12. This times the access steps:


*Rising edge: The first address bits are set
* Period 0: The address LSBs are set
*Rising edge: SDRMPX goes high
* Period 1: SDRMPX goes high
*Falling edge <span style="color:#F00">'''A'''</span>: The first address bits are latched in cartridge
* Period 2: The address MSBs are set
*Rising edge: The last address bits are set
* Period 3: SDRMPX goes low
*Rising edge: SDRMPX goes low  
* Period 4: SDROE goes low, RAD0~7 becomes hi-z
*Falling edge <span style="color:#F00">'''B'''</span>: The last address bits are latched in cartridge
* Period 5: ROM outputs data (when is it latched ?)
*Rising edge <span style="color:#F00">'''C'''</span>: /SDROE goes low, RAD0~7 is tristated
*One clock pulse to wait for ROM
*Falling edge <span style="color:#F00">'''D'''</span>: ROM data is read


A complete read takes 9us. SDRMPX is 3us high, 6us low. /SDROE is 3us low, 6us high.
Each period is 1.5us, a complete read cycle is 6 * 1.5 = 9us.


== ADPCM-B ROM access ==
==ADPCM-B bus==
The access to the [[V ROM]]s are done synchronously with the ADPCM-A access. A 4MHz clock is derived from the 8MHz main clock. This times the access steps:
[[File:Adpcm-b_timing.png]]


*Rising edge: The first address bits are set
The access to the ADPCM-B ROMs is done synchronously with a 4MHz clock, derived from the 8MHz clock.
*Rising edge: SDPMPX goes high
*Falling edge <span style="color:#F00">'''E'''</span>: The first address bits are latched in cartridge
*Rising edge: The last address bits are set
*Rising edge: SDPMPX goes low
*Falling edge <span style="color:#F00">'''F'''</span>: The last address bits are latched in cartridge
*Rising edge <span style="color:#F00">'''G'''</span>: /SDPOE goes low, PAD0~7 is tristated
*One clock pulse to wait for ROM
*Falling edge <span style="color:#F00">'''H'''</span>: ROM data is read


A complete read takes 1.5us. SDPMPX is 500ns high, /SDPOE is 500ns low. Reads can happen every 2 ADPCM-A read at most (gives a 55.5kHz samplerate).
* Period 0: The address LSBs are set
* Period 1: SDPMPX goes high
* Period 2: The address MSBs are set
* Period 3: SDPMPX goes low
* Period 4: SDPOE goes low, PAD0~7 becomes hi-z
* Period 5: ROM outputs data (when is it latched ?)
 
Each period is 250ns, each complete read cycle is 6 * 250 = 1.5us. Reads can happen every 2 ADPCM-A read at most (gives a 55.5kHz samplerate).
 
==Cycle relation==
 
To do.


[[Category:Audio system]]
[[Category:Audio system]]

Revision as of 07:30, 7 November 2016

ADPCM-A bus

Access to the ADPCM-A ROMs for each channel is done sequentialy (in the channels order ?). A ~667kHz clock is derived from the YM2610's 8MHz clock by dividing it by 12.

  • Period 0: The address LSBs are set
  • Period 1: SDRMPX goes high
  • Period 2: The address MSBs are set
  • Period 3: SDRMPX goes low
  • Period 4: SDROE goes low, RAD0~7 becomes hi-z
  • Period 5: ROM outputs data (when is it latched ?)

Each period is 1.5us, a complete read cycle is 6 * 1.5 = 9us.

ADPCM-B bus

The access to the ADPCM-B ROMs is done synchronously with a 4MHz clock, derived from the 8MHz clock.

  • Period 0: The address LSBs are set
  • Period 1: SDPMPX goes high
  • Period 2: The address MSBs are set
  • Period 3: SDPMPX goes low
  • Period 4: SDPOE goes low, PAD0~7 becomes hi-z
  • Period 5: ROM outputs data (when is it latched ?)

Each period is 250ns, each complete read cycle is 6 * 250 = 1.5us. Reads can happen every 2 ADPCM-A read at most (gives a 55.5kHz samplerate).

Cycle relation

To do.

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