PCM: Difference between revisions
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The trick takes advantage of the asynchronous and predictable access to the ADPCM-A and APDCM-B data by the {{Chipname|YM2610}}. See [[YM2610 bus timing]]. | The trick takes advantage of the asynchronous and predictable access to the ADPCM-A and APDCM-B data by the {{Chipname|YM2610}}. See [[YM2610 bus timing]]. | ||
Verilog | [[https://github.com/neogeodev/SNKVerilog/tree/master/PCM Verilog definition]]. | ||
=Pinout= | =Pinout= | ||
Revision as of 03:31, 12 April 2018
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| Package | QFP80R |
| Manufacturer | 
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| First use | 1992 ? |
| Used on | Cartridges |
PCM (not "NEO-PCM" for some reason) is a V ROM banking and demultiplexing chip, found in AES and MVS cartridges, and on ROM-only arcade boards.
Early cartridges had separate ADPCM-A and ADPCM-B sound ROMs. Since one was often emptier than the other, SNK devised a way to mix both types in the same ROM chip to save space and reduce costs.
NEO-PCM2 can also be found in late cartridges, and with NEO-YSA2.
On some Cartridge boards, VA20~VA22 are used to select which of the 4 possible V ROMs to use (decoded by a LS139).
Uses several latches for address and data, as well as a counter clocked by 68KCLKB for synchronisation.
Internal logic
The trick takes advantage of the asynchronous and predictable access to the ADPCM-A and APDCM-B data by the YM2610. See YM2610 bus timing.
Pinout
OpenOffice Draw file: File:Pcm.odg
Has an inverter on pins 26 and 27.
- SDPOE, SDROE, SDPMPX, SDRMPX: from the YM2610.
- SDRAD0~SDRAD7: ADPCM-A multiplexed bus part
- SDPAD0~SDPAD7: ADPCM-B multiplexed bus part
- SDRA8, SDRA9, SDRA20~SDRA23: ADPCM-A address bus
- SDPA8~SDPA11: ADPCM-B address bus
- V D0~V D7: V ROM(s) data bus
- V A-1~V A22: V ROM(s) address bus