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| See [[ADPCM]] for details on this part's operation. | | See [[ADPCM]] for details on this part's operation. |
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| {| class="regdef"
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| |'''Address (Z80 port 4)'''
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| |'''Data (Z80 port 5)'''
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| |Value on [[reset]]
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| |-
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| |$1C
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| |{{8BitRegister|B|1|-|1|A6|1|A5|1|A4|1|A3|1|A2|1|A1|1|}}
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| |$00
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| |}
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|
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| * Write to flag control to reset/mask channel end flags
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| ** Write 1 to reset and/or mask selected flag
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| ** Write 0 to unmask selected flag
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| ** Masking a flag will prevent it from being raised when a channel reaches its end address. This means you have to write 1 to clear the flag, then 0 to keep it active.
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| ** Flags must be manually cleared, playing a new sample on the channel won't clear it.
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| ==ADPCM-A part==
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|
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| See [[ADPCM]] for details on this part's operation.
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| {| class="regdef"
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| |'''Address (Z80 port 6)'''
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| |'''Data (Z80 port 7)'''
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| |Value on [[reset]]
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| |
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| |-
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| |$00
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| |{{8BitRegister|Dump|1|-|1|CH6 ON|1|CH5 ON|1|CH4 ON|1|CH3 ON|1|CH2 ON |1|CH1 ON|1}}
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| |$00
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| |'Dump' is the key on/off bit. Write 0 to start playing specified channels and write 1 to stop playing.
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| |-
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| |$01
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| |{{8BitRegister|-|2|Master volume|6}}
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| |$00
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| |Actually an attenuator, 0 is the loudest.
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| |-
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| |$08~$0D (one for each channel)
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| |{{8BitRegister|L|1|R|1|-|1|Channel volume|5}}
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| |$00
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| |Actually an attenuator, 0 is the loudest. L/R routes the output to the left and/or right channels.
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| |-
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| |$10~$15 (one for each channel)
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| |{{8BitRegister|Sample's start address/256 LSB|8}}
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| |$00
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| |rowspan="4"|All ADPCM addresses must match a 256-byte boundary (bits 0~7 = 0)
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| |-
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| |$18~$1D (one for each channel)
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| |{{8BitRegister|Sample's start address/256 MSB|8}}
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| |$00
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| |-
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| |$20~$25 (one for each channel)
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| |{{8BitRegister|Sample's stop address/256 LSB|8}}
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| |$00
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| |-
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| |$28~$2D (one for each channel)
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| |{{8BitRegister|Sample's stop address/256 MSB|8}}
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| |$00
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| |}
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| ==ADPCM-B part==
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| See [[ADPCM]] for details on this part's operation.
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| {| class="regdef"
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| |'''Address (Z80 port 4)'''
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| |'''Data (Z80 port 5)'''
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| |Value on [[reset]]
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| |-
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| |$10
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| |{{8BitRegister|Start|1|-|2|Repeat|1|-|3|Reset|1|}}
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| |$00
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| |Repeat: loop when end address is reached. Reset: clears Start and Repeat.
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| |-
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| |$11
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| |{{8BitRegister|L|1|R|1|-|6|}}
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| |$00
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| |Left/Right channel output
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| |-
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| |$12
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| |{{8BitRegister|Sample's start address/256 LSB|8}}
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| |?
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| |rowspan="4"|All ADPCM addresses must match a 256-byte boundary (bits 0~7 = 0)
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| |-
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| |$13
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| |{{8BitRegister|Sample's start address/256 MSB|8}}
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| |?
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| |-
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| |$14
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| |{{8BitRegister|Sample's stop address/256 LSB|8}}
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| |?
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| |-
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| |$15
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| |{{8BitRegister|Sample's stop address/256 MSB|8}}
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| |?
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| |-
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| |$19
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| |{{8BitRegister|Delta-N (L)|8}}
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| |?
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| |rowspan="2"|Playback rate is f = 8M / 12 / 12 / (65535 / Delta-N) = 55555 * (Delta-N / 65535) Hz
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| |-
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| |$1A
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| |{{8BitRegister|Delta-N (H)|8}}
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| |?
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| |-
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| |$1B
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| |{{8BitRegister|ADPCM-B channel volume|8}}
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| |?
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| |Loudest is $FF
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| |}
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| =Reading= | | =Reading= |
Summary:
...
Timers
See YM2610 timers.
SSG part
See SSG for details on this part's operation.
FM part
See FM for details on this part's operation.
Common FM registers
| Address (Z80 port 4)
|
Data (Z80 port 5)
|
|
| $22
|
| Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Def |
- |
On | Control |
|
LFO Frequency
|
| $28
|
| Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Def |
Slot |
- | Channel |
|
Key On/Off
|
LFO frequency values are as follows:
- 0 – 3.98Hz
- 1 – 5.56Hz
- 2 – 6.02Hz
- 3 – 6.37Hz
- 4 – 6.88Hz
- 5 – 9.63Hz
- 6 – 48.1Hz
- 7 – 72.2Hz
Overall channel registers
The first value listed in the Address column is for channels 1/3; the second is for channels 2/4.
| Address (Z80 port 4 or 6) |
Data (Z80 port 5 or 7) |
|
| $A1,$A2
|
| Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Def |
F-Num 1 |
|
F-Numbers and Block (1/2)
|
| $A5,$A6
|
| Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Def |
- |
Block | F-Num 2 |
|
F-Numbers and Block (2/2)
(must set this first)
|
| $A9,$AA
|
| Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Def |
2CH * F-Num 1 |
|
2CH - 2 Slot F-Numbers/Block (1/2)
|
| $AD,$AE
|
| Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Def |
- |
2CH * Block | 2CH * F-Num 2 |
|
2CH - 2 Slot F-Numbers/Block (1/2)
(must set this first)
|
| $B1,$B2
|
| Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Def |
- |
FB | ALGO |
|
Feedback (FB) and Algorithm (ALGO)
|
| $B5,B6
|
| Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Def |
L |
R | AMS | - | PMS |
|
Left (L)/Right (R) output, AM Sense (AMS), and PM Sense (PMS)
|
Channel registers
Depending on which channel you want to write to, the ports used are different:
- Channels 1 & 2: Ports 4/5
- Channels 3 & 4: Ports 6/7
Per-operator registers
The ranges given for the address represent all of the parameter values. Each channel's operators are laid out as follows:
| Operator |
1 |
2 |
3 |
4
|
| Channels 1, 3
|
$x1 |
$x5 |
$x9 |
$xD
|
| Channels 2, 4
|
$x2 |
$x6 |
$xA |
$xE
|
| Address (Z80 port 4 or 6) |
Data (Z80 port 5 or 7) |
|
| $31-$3E
|
| Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Def |
- |
DT | MUL |
|
Detune (DT) and Multiple (MUL)
|
| $41-$4E
|
| Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Def |
- |
Total Level |
|
Total Level (Volume)
|
| $51-$5E
|
| Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Def |
KS |
- | AR |
|
Key Scale (KS) and Attack Rate (AR)
|
| $61-$6E
|
| Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Def |
AM |
- | DR |
|
AM On (AM) and Decay Rate (DR)
|
| $71-$7E
|
| Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Def |
- |
SR |
|
Sustain Rate (SR)
|
| $81-$8E
|
| Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Def |
SL |
RR |
|
Sustain Level (SL) and Release Rate (RR)
|
| $91-$9E
|
| Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Def |
- |
SSG-EG |
|
SSG-EG
|
ADPCM part
See ADPCM for details on this part's operation.
Reading
The only writable registers that can also be read are from the SSG. All other ports and addresses return different data.
| Z80 port #
|
Data
|
Notes
|
| $04
|
| Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Def |
Busy |
- | Timer B flag | Timer A flag |
|
When a timer expires and IRQ is enabled for the timer, the respective bit is set
|
| $05
|
| Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Def |
SSG register data |
|
Attempting to read non-SSG registers will fail
|
| $06
|
| Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Def |
ADPCM-B end |
- | CH6 end | CH5 end | CH4 end | CH3 end | CH2 end | CH1 end |
|
When a channel has reached the end address and stops, the respective bit is set, unless masked
|
| $07
|
not implemented
|
Always returns $00
|