Revision as of 18:23, 24 June 2017

Timers

See SSG for details on this part's operation.

See FM for details on this part's operation.

See ADPCM for details on this part's operation.

The only writable registers that can also be read are the SSG ones. To read register X, write X to Z80 port 4, then read Z80 port 5.

Z80 port

Data

Notes

$04

Bit	7	6	5	4	3	2	1	0
Def	Busy	-					Timer B flag	Timer A flag

When a timer expires and IRQ is enabled for the timer, the respective flag is set.

$05

Bit	7	6	5	4	3	2	1	0
Def	SSG register data

Attempting to read non-SSG registers will return 0.

$06

Bit	7	6	5	4	3	2	1	0
Def	ADPCM-B end	-	CH6 end	CH5 end	CH4 end	CH3 end	CH2 end	CH1 end

When a channel has reached the end address and stops, the respective bit is set (unless masked).

$07

Not implemented

Always returns $00

@@ Line 18: / Line 18: @@
 The only writable registers that can also be read are the SSG ones.
+To read register X, write X to Z80 port 4, then read Z80 port 5.
 {| class="regdef"
@@ Line 30: / Line 31: @@
 |$05
 |{{8BitRegister|SSG register data|8}}
-|Attempting to read non-SSG registers will fail.
+|Attempting to read non-SSG registers will return 0.
 |-
 |$06