Revision as of 18:32, 25 March 2011

Also found on MVS boards, even those without memory card slots.

BIOS vector table swapping

When 68k A8~A23 = 0 and the [[BIOSes|BIOS]'s vector table is chosen (by using "system" memory mapped registers), A22I~A23I outputs are set to 1. This makes the address appear to address decoding chips as a BIOS access instead of a P ROM access.

Memory card address latch

On AES systems, BNK0~BNK2 are tied low. This makes the chip act just like a buffer ? What are BNK0~BNK2 used for ?

The chip also ANDs the pair of 8bit output enable signals from the NEO-C1 since there is only a single 16bit ROM used for the BIOS.

Pinout

A1~A23: 68k address bus
Y0~Y23: memory card address bus
BNK0~BNK2: comes from NEO-D0, ?
VEC: BIOS vector table swapping enable
ANI0, ANI1, AND0: AND gate used to generate ROMOE from ROMOEU and ROMOEL

@@ Line 1: / Line 1: @@
 [[File:aes_e0.jpg|right|thumb|NEO-E0 chip found on a AES board.]]
-Also found in MVS systems. Probably grouped glue logic, as early AES boards had plenty of 74HC chips instead.
+Also found on MVS boards, even those without memory card slots.
-BIOS vector table swapping is handled by this chip.  When 68k A8~A23 = 0 and the appropriate 74HC259 input (determined by [[memory mapped registers]]) is active, A22I~A23I outputs are set to 1.  This makes the address appear to address decoding chips as a [[BIOSes|BIOS]] access instead of a [[P ROM]] access.
+==BIOS vector table swapping==
+When 68k A8~A23 = 0 and the [[BIOSes|BIOS]'s vector table is chosen (by using [[memory mapped registers#System registers|"system" memory mapped registers]]), A22I~A23I outputs are set to 1.  This makes the address appear to address decoding chips as a BIOS access instead of a [[P ROM]] access.
-It also ANDs the pair of 8bit output enable signals from the [[NEO-C1]] since there is only a single 16bit ROM used for the BIOS.
+==Memory card address latch==
+On AES systems, BNK0~BNK2 are tied low. This makes the chip act just like a buffer ?
+What are BNK0~BNK2 used for ?
-What is Y0~Y23 for? attached to memory card in AES / multislots?
+The chip also ANDs the pair of 8bit output enable signals from the [[NEO-C1]] since there is only a single 16bit ROM used for the BIOS.
+=Pinout=
+[[File:Neo-e0_pinout.png]]
+*A1~A23: 68k address bus
+*Y0~Y23: memory card address bus
+*BNK0~BNK2: comes from [[NEO-D0]], ?
+*VEC: BIOS vector table swapping enable
+*ANI0, ANI1, AND0: AND gate used to generate ROMOE from ROMOEU and ROMOEL
 [[Category:Chips]]

NEO-E0: Difference between revisions

Revision as of 18:32, 25 March 2011

BIOS vector table swapping

Memory card address latch

Pinout

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